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https://github.com/darlinghq/darling-gdb.git
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d9e3a135fa
and variable renaming due to macro insn additions. * mloop.in: Update to use CGEN_INSN_NUM. * cpu.x,modelx.c,readx.c,semx.c: Regenerated. * mloopx.in: Update to use CGEN_INSN_NUM.
352 lines
14 KiB
C
352 lines
14 KiB
C
/* Simulator model support for m32r.
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This file is machine generated with CGEN.
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Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
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This file is part of the GNU Simulators.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License along
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with this program; if not, write to the Free Software Foundation, Inc.,
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59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#define WANT_CPU
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#define WANT_CPU_M32R
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#include "sim-main.h"
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#include "cpu-sim.h"
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#include "cpu-opc.h"
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/* The profiling data is recorded here, but is accessed via the profiling
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mechanism. After all, this is information for profiling. */
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#if WITH_PROFILE_MODEL_P
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/* Track function unit usage for an instruction. */
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void
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m32r_model_profile_insn (SIM_CPU *current_cpu, ARGBUF *abuf)
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{
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const MODEL *model = CPU_MODEL (current_cpu);
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const INSN_TIMING *timing = MODEL_TIMING (model);
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const CGEN_INSN *insn = abuf->opcode;
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const UNIT *unit = &timing[CGEN_INSN_NUM (insn)].units[0];
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const UNIT *unit_end = unit + MAX_UNITS;
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PROFILE_DATA *profile = CPU_PROFILE_DATA (current_cpu);
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do
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{
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switch (unit->name)
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{
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case UNIT_M32R_D_U_STORE :
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PROFILE_MODEL_CYCLE_COUNT (profile) += unit->done;
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m32r_model_mark_unbusy_reg (current_cpu, abuf);
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break;
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case UNIT_M32R_D_U_LOAD :
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PROFILE_MODEL_CYCLE_COUNT (profile) += unit->done;
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m32r_model_mark_busy_reg (current_cpu, abuf);
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break;
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case UNIT_M32R_D_U_EXEC :
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PROFILE_MODEL_CYCLE_COUNT (profile) += unit->done;
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m32r_model_mark_unbusy_reg (current_cpu, abuf);
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break;
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case UNIT_TEST_U_EXEC :
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PROFILE_MODEL_CYCLE_COUNT (profile) += unit->done;
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break;
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}
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++unit;
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}
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while (unit != unit_end && unit->name != UNIT_NONE);
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}
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/* Track function unit usage for an instruction. */
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void
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m32r_model_profile_cti_insn (SIM_CPU *current_cpu, ARGBUF *abuf, int taken_p)
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{
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const MODEL *model = CPU_MODEL (current_cpu);
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const INSN_TIMING *timing = MODEL_TIMING (model);
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const CGEN_INSN *insn = abuf->opcode;
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const UNIT *unit = &timing[CGEN_INSN_NUM (insn)].units[0];
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const UNIT *unit_end = unit + MAX_UNITS;
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PROFILE_DATA *profile = CPU_PROFILE_DATA (current_cpu);
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do
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{
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switch (unit->name)
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{
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case UNIT_M32R_D_U_STORE :
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PROFILE_MODEL_CYCLE_COUNT (profile) += unit->done;
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m32r_model_mark_unbusy_reg (current_cpu, abuf);
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break;
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case UNIT_M32R_D_U_LOAD :
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PROFILE_MODEL_CYCLE_COUNT (profile) += unit->done;
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m32r_model_mark_busy_reg (current_cpu, abuf);
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break;
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case UNIT_M32R_D_U_EXEC :
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PROFILE_MODEL_CYCLE_COUNT (profile) += unit->done;
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if (taken_p) PROFILE_MODEL_CTI_STALL_COUNT (profile) += 2;
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m32r_model_mark_unbusy_reg (current_cpu, abuf);
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break;
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case UNIT_TEST_U_EXEC :
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PROFILE_MODEL_CYCLE_COUNT (profile) += unit->done;
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break;
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}
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if (taken_p)
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PROFILE_MODEL_TAKEN_COUNT (profile) += 1;
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else
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PROFILE_MODEL_UNTAKEN_COUNT (profile) += 1;
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++unit;
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}
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while (unit != unit_end && unit->name != UNIT_NONE);
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}
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/* We assume UNIT_NONE == 0 because the tables don't always terminate
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entries with it. */
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/* Model timing data for `m32r/d'. */
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static const INSN_TIMING m32r_d_timing[] = {
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{ { (UQI) UNIT_NONE } }, /* illegal insn */
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{ { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* add */
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{ { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* add3 */
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{ { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* and */
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{ { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* and3 */
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{ { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* or */
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{ { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* or3 */
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{ { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* xor */
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{ { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* xor3 */
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{ { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* addi */
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{ { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* addv */
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{ { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* addv3 */
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{ { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* addx */
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{ { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* bc8 */
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{ { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* bc24 */
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{ { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* beq */
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{ { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* beqz */
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{ { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* bgez */
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{ { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* bgtz */
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{ { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* blez */
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{ { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* bltz */
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{ { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* bnez */
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{ { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* bl8 */
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{ { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* bl24 */
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{ { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* bnc8 */
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{ { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* bnc24 */
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{ { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* bne */
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{ { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* bra8 */
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{ { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* bra24 */
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{ { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* cmp */
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{ { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* cmpi */
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{ { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* cmpu */
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{ { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* cmpui */
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{ { (UQI) UNIT_M32R_D_U_EXEC, 37, 37 } }, /* div */
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{ { (UQI) UNIT_M32R_D_U_EXEC, 37, 37 } }, /* divu */
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{ { (UQI) UNIT_M32R_D_U_EXEC, 37, 37 } }, /* rem */
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{ { (UQI) UNIT_M32R_D_U_EXEC, 37, 37 } }, /* remu */
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{ { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* jl */
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{ { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* jmp */
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{ { (UQI) UNIT_M32R_D_U_LOAD, 1, 1 } }, /* ld */
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{ { (UQI) UNIT_M32R_D_U_LOAD, 2, 2 } }, /* ld-d */
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{ { (UQI) UNIT_M32R_D_U_LOAD, 1, 1 } }, /* ldb */
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{ { (UQI) UNIT_M32R_D_U_LOAD, 2, 2 } }, /* ldb-d */
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{ { (UQI) UNIT_M32R_D_U_LOAD, 1, 1 } }, /* ldh */
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{ { (UQI) UNIT_M32R_D_U_LOAD, 2, 2 } }, /* ldh-d */
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{ { (UQI) UNIT_M32R_D_U_LOAD, 1, 1 } }, /* ldub */
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{ { (UQI) UNIT_M32R_D_U_LOAD, 2, 2 } }, /* ldub-d */
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{ { (UQI) UNIT_M32R_D_U_LOAD, 1, 1 } }, /* lduh */
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{ { (UQI) UNIT_M32R_D_U_LOAD, 2, 2 } }, /* lduh-d */
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{ { (UQI) UNIT_M32R_D_U_LOAD, 1, 1 } }, /* ld-plus */
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{ { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* ld24 */
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{ { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* ldi8 */
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{ { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* ldi16 */
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{ { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* lock */
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{ { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* machi */
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{ { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* maclo */
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{ { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* macwhi */
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{ { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* macwlo */
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{ { (UQI) UNIT_M32R_D_U_EXEC, 4, 4 } }, /* mul */
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{ { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* mulhi */
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{ { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* mullo */
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{ { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* mulwhi */
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{ { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* mulwlo */
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{ { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* mv */
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{ { (UQI) UNIT_M32R_D_U_EXEC, 2, 2 } }, /* mvfachi */
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{ { (UQI) UNIT_M32R_D_U_EXEC, 2, 2 } }, /* mvfaclo */
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{ { (UQI) UNIT_M32R_D_U_EXEC, 2, 2 } }, /* mvfacmi */
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{ { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* mvfc */
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{ { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* mvtachi */
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{ { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* mvtaclo */
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{ { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* mvtc */
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{ { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* neg */
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{ { (UQI) UNIT_M32R_D_U_EXEC, 0, 0 } }, /* nop */
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{ { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* not */
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{ { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* rac */
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{ { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* rach */
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{ { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* rte */
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{ { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* seth */
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{ { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* sll */
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{ { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* sll3 */
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{ { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* slli */
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{ { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* sra */
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{ { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* sra3 */
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{ { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* srai */
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{ { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* srl */
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{ { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* srl3 */
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{ { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* srli */
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{ { (UQI) UNIT_M32R_D_U_STORE, 1, 1 } }, /* st */
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{ { (UQI) UNIT_M32R_D_U_STORE, 2, 2 } }, /* st-d */
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{ { (UQI) UNIT_M32R_D_U_STORE, 1, 1 } }, /* stb */
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{ { (UQI) UNIT_M32R_D_U_STORE, 2, 2 } }, /* stb-d */
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{ { (UQI) UNIT_M32R_D_U_STORE, 1, 1 } }, /* sth */
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{ { (UQI) UNIT_M32R_D_U_STORE, 2, 2 } }, /* sth-d */
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{ { (UQI) UNIT_M32R_D_U_STORE, 1, 1 } }, /* st-plus */
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{ { (UQI) UNIT_M32R_D_U_STORE, 1, 1 } }, /* st-minus */
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{ { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* sub */
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{ { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* subv */
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{ { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* subx */
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{ { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* trap */
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{ { (UQI) UNIT_M32R_D_U_EXEC, 1, 1 } }, /* unlock */
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};
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/* Model timing data for `test'. */
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static const INSN_TIMING test_timing[] = {
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{ { (UQI) UNIT_NONE } }, /* illegal insn */
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{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* add */
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{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* add3 */
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{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* and */
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{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* and3 */
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{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* or */
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{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* or3 */
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{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* xor */
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{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* xor3 */
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{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* addi */
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{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* addv */
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{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* addv3 */
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{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* addx */
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{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* bc8 */
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{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* bc24 */
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{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* beq */
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{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* beqz */
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{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* bgez */
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{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* bgtz */
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{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* blez */
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{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* bltz */
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{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* bnez */
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{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* bl8 */
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{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* bl24 */
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{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* bnc8 */
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{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* bnc24 */
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{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* bne */
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{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* bra8 */
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{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* bra24 */
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{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* cmp */
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{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* cmpi */
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{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* cmpu */
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{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* cmpui */
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{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* div */
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{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* divu */
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{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* rem */
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{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* remu */
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{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* jl */
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{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* jmp */
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{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* ld */
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{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* ld-d */
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{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* ldb */
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{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* ldb-d */
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{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* ldh */
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{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* ldh-d */
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{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* ldub */
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{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* ldub-d */
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{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* lduh */
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{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* lduh-d */
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{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* ld-plus */
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{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* ld24 */
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{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* ldi8 */
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{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* ldi16 */
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{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* lock */
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{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* machi */
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{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* maclo */
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{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* macwhi */
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{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* macwlo */
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{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* mul */
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{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* mulhi */
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{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* mullo */
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{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* mulwhi */
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{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* mulwlo */
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{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* mv */
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{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* mvfachi */
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{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* mvfaclo */
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{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* mvfacmi */
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{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* mvfc */
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{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* mvtachi */
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{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* mvtaclo */
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{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* mvtc */
|
|
{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* neg */
|
|
{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* nop */
|
|
{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* not */
|
|
{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* rac */
|
|
{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* rach */
|
|
{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* rte */
|
|
{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* seth */
|
|
{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* sll */
|
|
{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* sll3 */
|
|
{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* slli */
|
|
{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* sra */
|
|
{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* sra3 */
|
|
{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* srai */
|
|
{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* srl */
|
|
{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* srl3 */
|
|
{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* srli */
|
|
{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* st */
|
|
{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* st-d */
|
|
{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* stb */
|
|
{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* stb-d */
|
|
{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* sth */
|
|
{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* sth-d */
|
|
{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* st-plus */
|
|
{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* st-minus */
|
|
{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* sub */
|
|
{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* subv */
|
|
{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* subx */
|
|
{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* trap */
|
|
{ { (UQI) UNIT_TEST_U_EXEC, 1, 1 } }, /* unlock */
|
|
};
|
|
|
|
#endif /* WITH_PROFILE_MODEL_P */
|
|
|
|
#if WITH_PROFILE_MODEL_P
|
|
#define TIMING_DATA(td) td
|
|
#else
|
|
#define TIMING_DATA(td) 0
|
|
#endif
|
|
|
|
const MODEL m32r_models[] = {
|
|
{ "m32r/d", &machs[MACH_M32R], TIMING_DATA (& m32r_d_timing[0]) },
|
|
{ "test", &machs[MACH_M32R], TIMING_DATA (& test_timing[0]) },
|
|
{ 0 }
|
|
};
|
|
|
|
/* The properties of this cpu's implementation. */
|
|
|
|
const IMP_PROPERTIES m32r_imp_properties = {
|
|
sizeof (SIM_CPU)
|
|
#if WITH_SCACHE
|
|
, sizeof (SCACHE)
|
|
#endif
|
|
};
|
|
|