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7621229598
* symfile.h (ADD_PSYMBOL_VT_TO_LIST), symfile.c (add_psymbol_to_list, add_psymbol_addr_to_list): No longer demangle partial symbols. * symtab.c (lookup_symbol, list_symbols): Handle mangled variables, e.g. C++ static members, via the minimal symbols. Handle reordered functions in an objfile, for Irix 5.2 shared libraries. * objfiles.h (OBJF_REORDERED): New bit in the objfile flags, set if the functions in an objfile are reordered. * mdebugread.c (parse_partial_symbols): Detect reordered functions in an objfile. * symtab.c (find_pc_psymtab, find_pc_symtab): Use expensive lookup algorithm if the functions in the objfile are reordered. * xcoffexec.c (exec_close): If the current target has a copy of the exec_ops sections, reflect the freeing of the sections in current_target. * valops.c (call_function_by_hand): Use `sizeof dummy1', not `sizeof dummy', for constructing the call dummy code. * config/sparc/tm-sparc.h: Add PARAMS declarations to all function declarations. * sparc-tdep.c (sparc_pop_frame): Cast result of read_memory_integer to CORE_ADDR when passing it to PC_ADJUST. * irix5-nat.c (enable_break): Set breakpoint at the entry point of the executable, to handle the case where main resides in a shared library. * irix5-nat.c (solib_create_inferior_hook): Reset stop_soon_quietly after shared library symbol reading, to get rid of a warning from heuristic_proc_start if the startup code has no symbolic debug info. * breakpoint.h (struct breakpoint): Add new fields language and input_radix, to enable breakpoint resetting with the proper language and radix. * breakpoint.c (set_raw_breakpoint): Initialize them. (breakpoint_re_set_one): Use them when resetting the breakpoint. (breakpoint_re_set): Preserve current language and input_radix across breakpoint_re_set_one calls. * symtab.c (decode_line_1): Do not build a canonical line specification for `*expr' line specifications. * breakpoint.h (bpstat_stop_status): Fix prototype declaration.
782 lines
23 KiB
C
782 lines
23 KiB
C
/* Target-dependent code for the SPARC for GDB, the GNU debugger.
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Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994
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Free Software Foundation, Inc.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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#include "defs.h"
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#include "frame.h"
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#include "inferior.h"
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#include "obstack.h"
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#include "target.h"
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#include "value.h"
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#ifdef USE_PROC_FS
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#include <sys/procfs.h>
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#endif
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#include "gdbcore.h"
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/* From infrun.c */
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extern int stop_after_trap;
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/* We don't store all registers immediately when requested, since they
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get sent over in large chunks anyway. Instead, we accumulate most
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of the changes and send them over once. "deferred_stores" keeps
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track of which sets of registers we have locally-changed copies of,
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so we only need send the groups that have changed. */
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int deferred_stores = 0; /* Cumulates stores we want to do eventually. */
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typedef enum
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{
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Error, not_branch, bicc, bicca, ba, baa, ticc, ta
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} branch_type;
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/* Simulate single-step ptrace call for sun4. Code written by Gary
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Beihl (beihl@mcc.com). */
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/* npc4 and next_pc describe the situation at the time that the
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step-breakpoint was set, not necessary the current value of NPC_REGNUM. */
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static CORE_ADDR next_pc, npc4, target;
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static int brknpc4, brktrg;
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typedef char binsn_quantum[BREAKPOINT_MAX];
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static binsn_quantum break_mem[3];
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/* Non-zero if we just simulated a single-step ptrace call. This is
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needed because we cannot remove the breakpoints in the inferior
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process until after the `wait' in `wait_for_inferior'. Used for
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sun4. */
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int one_stepped;
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/* single_step() is called just before we want to resume the inferior,
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if we want to single-step it but there is no hardware or kernel single-step
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support (as on all SPARCs). We find all the possible targets of the
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coming instruction and breakpoint them.
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single_step is also called just after the inferior stops. If we had
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set up a simulated single-step, we undo our damage. */
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void
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single_step (ignore)
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int ignore; /* pid, but we don't need it */
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{
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branch_type br, isannulled();
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CORE_ADDR pc;
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long pc_instruction;
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if (!one_stepped)
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{
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/* Always set breakpoint for NPC. */
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next_pc = read_register (NPC_REGNUM);
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npc4 = next_pc + 4; /* branch not taken */
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target_insert_breakpoint (next_pc, break_mem[0]);
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/* printf_unfiltered ("set break at %x\n",next_pc); */
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pc = read_register (PC_REGNUM);
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pc_instruction = read_memory_integer (pc, sizeof(pc_instruction));
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br = isannulled (pc_instruction, pc, &target);
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brknpc4 = brktrg = 0;
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if (br == bicca)
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{
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/* Conditional annulled branch will either end up at
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npc (if taken) or at npc+4 (if not taken).
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Trap npc+4. */
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brknpc4 = 1;
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target_insert_breakpoint (npc4, break_mem[1]);
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}
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else if (br == baa && target != next_pc)
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{
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/* Unconditional annulled branch will always end up at
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the target. */
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brktrg = 1;
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target_insert_breakpoint (target, break_mem[2]);
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}
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/* We are ready to let it go */
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one_stepped = 1;
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return;
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}
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else
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{
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/* Remove breakpoints */
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target_remove_breakpoint (next_pc, break_mem[0]);
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if (brknpc4)
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target_remove_breakpoint (npc4, break_mem[1]);
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if (brktrg)
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target_remove_breakpoint (target, break_mem[2]);
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one_stepped = 0;
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}
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}
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CORE_ADDR
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sparc_frame_chain (thisframe)
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FRAME thisframe;
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{
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char buf[MAX_REGISTER_RAW_SIZE];
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int err;
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CORE_ADDR addr;
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addr = thisframe->frame + FRAME_SAVED_I0 +
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REGISTER_RAW_SIZE (FP_REGNUM) * (FP_REGNUM - I0_REGNUM);
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err = target_read_memory (addr, buf, REGISTER_RAW_SIZE (FP_REGNUM));
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if (err)
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return 0;
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return extract_address (buf, REGISTER_RAW_SIZE (FP_REGNUM));
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}
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CORE_ADDR
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sparc_extract_struct_value_address (regbuf)
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char regbuf[REGISTER_BYTES];
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{
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return read_memory_integer (((int *)(regbuf))[SP_REGNUM]+(16*4),
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TARGET_PTR_BIT / TARGET_CHAR_BIT);
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}
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/* Find the pc saved in frame FRAME. */
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CORE_ADDR
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sparc_frame_saved_pc (frame)
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FRAME frame;
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{
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char buf[MAX_REGISTER_RAW_SIZE];
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CORE_ADDR addr;
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if (frame->signal_handler_caller)
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{
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/* This is the signal trampoline frame.
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Get the saved PC from the sigcontext structure. */
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#ifndef SIGCONTEXT_PC_OFFSET
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#define SIGCONTEXT_PC_OFFSET 12
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#endif
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CORE_ADDR sigcontext_addr;
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char scbuf[TARGET_PTR_BIT / HOST_CHAR_BIT];
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int saved_pc_offset = SIGCONTEXT_PC_OFFSET;
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char *name = NULL;
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/* Solaris2 ucbsigvechandler passes a pointer to a sigcontext
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as the third parameter. The offset to the saved pc is 12. */
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find_pc_partial_function (frame->pc, &name,
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(CORE_ADDR *)NULL,(CORE_ADDR *)NULL);
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if (name && STREQ (name, "ucbsigvechandler"))
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saved_pc_offset = 12;
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/* The sigcontext address is contained in register O2. */
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get_saved_register (buf, (int *)NULL, (CORE_ADDR *)NULL,
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frame, O0_REGNUM + 2, (enum lval_type *)NULL);
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sigcontext_addr = extract_address (buf, REGISTER_RAW_SIZE (O0_REGNUM));
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/* Don't cause a memory_error when accessing sigcontext in case the
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stack layout has changed or the stack is corrupt. */
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target_read_memory (sigcontext_addr + saved_pc_offset,
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scbuf, sizeof (scbuf));
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return extract_address (scbuf, sizeof (scbuf));
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}
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addr = (frame->bottom + FRAME_SAVED_I0 +
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REGISTER_RAW_SIZE (I7_REGNUM) * (I7_REGNUM - I0_REGNUM));
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read_memory (addr, buf, REGISTER_RAW_SIZE (I7_REGNUM));
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return PC_ADJUST (extract_address (buf, REGISTER_RAW_SIZE (I7_REGNUM)));
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}
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/*
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* Since an individual frame in the frame cache is defined by two
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* arguments (a frame pointer and a stack pointer), we need two
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* arguments to get info for an arbitrary stack frame. This routine
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* takes two arguments and makes the cached frames look as if these
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* two arguments defined a frame on the cache. This allows the rest
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* of info frame to extract the important arguments without
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* difficulty.
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*/
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FRAME
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setup_arbitrary_frame (argc, argv)
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int argc;
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FRAME_ADDR *argv;
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{
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FRAME fid;
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if (argc != 2)
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error ("Sparc frame specifications require two arguments: fp and sp");
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fid = create_new_frame (argv[0], 0);
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if (!fid)
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fatal ("internal: create_new_frame returned invalid frame id");
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fid->bottom = argv[1];
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fid->pc = FRAME_SAVED_PC (fid);
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return fid;
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}
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/* Given a pc value, skip it forward past the function prologue by
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disassembling instructions that appear to be a prologue.
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If FRAMELESS_P is set, we are only testing to see if the function
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is frameless. This allows a quicker answer.
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This routine should be more specific in its actions; making sure
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that it uses the same register in the initial prologue section. */
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CORE_ADDR
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skip_prologue (start_pc, frameless_p)
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CORE_ADDR start_pc;
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int frameless_p;
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{
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union
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{
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unsigned long int code;
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struct
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{
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unsigned int op:2;
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unsigned int rd:5;
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unsigned int op2:3;
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unsigned int imm22:22;
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} sethi;
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struct
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{
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unsigned int op:2;
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unsigned int rd:5;
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unsigned int op3:6;
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unsigned int rs1:5;
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unsigned int i:1;
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unsigned int simm13:13;
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} add;
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int i;
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} x;
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int dest = -1;
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CORE_ADDR pc = start_pc;
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x.i = read_memory_integer (pc, 4);
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/* Recognize the `sethi' insn and record its destination. */
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if (x.sethi.op == 0 && x.sethi.op2 == 4)
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{
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dest = x.sethi.rd;
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pc += 4;
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x.i = read_memory_integer (pc, 4);
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}
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/* Recognize an add immediate value to register to either %g1 or
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the destination register recorded above. Actually, this might
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well recognize several different arithmetic operations.
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It doesn't check that rs1 == rd because in theory "sub %g0, 5, %g1"
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followed by "save %sp, %g1, %sp" is a valid prologue (Not that
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I imagine any compiler really does that, however). */
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if (x.add.op == 2 && x.add.i && (x.add.rd == 1 || x.add.rd == dest))
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{
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pc += 4;
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x.i = read_memory_integer (pc, 4);
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}
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/* This recognizes any SAVE insn. But why do the XOR and then
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the compare? That's identical to comparing against 60 (as long
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as there isn't any sign extension). */
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if (x.add.op == 2 && (x.add.op3 ^ 32) == 28)
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{
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pc += 4;
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if (frameless_p) /* If the save is all we care about, */
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return pc; /* return before doing more work */
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x.i = read_memory_integer (pc, 4);
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}
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else
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{
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/* Without a save instruction, it's not a prologue. */
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return start_pc;
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}
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/* Now we need to recognize stores into the frame from the input
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registers. This recognizes all non alternate stores of input
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register, into a location offset from the frame pointer. */
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while (x.add.op == 3
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&& (x.add.op3 & 0x3c) == 4 /* Store, non-alternate. */
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&& (x.add.rd & 0x18) == 0x18 /* Input register. */
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&& x.add.i /* Immediate mode. */
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&& x.add.rs1 == 30 /* Off of frame pointer. */
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/* Into reserved stack space. */
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&& x.add.simm13 >= 0x44
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&& x.add.simm13 < 0x5b)
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{
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pc += 4;
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x.i = read_memory_integer (pc, 4);
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}
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return pc;
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}
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/* Check instruction at ADDR to see if it is an annulled branch.
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All other instructions will go to NPC or will trap.
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Set *TARGET if we find a canidate branch; set to zero if not. */
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branch_type
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isannulled (instruction, addr, target)
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long instruction;
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CORE_ADDR addr, *target;
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{
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branch_type val = not_branch;
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long int offset; /* Must be signed for sign-extend. */
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union
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{
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unsigned long int code;
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struct
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{
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unsigned int op:2;
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unsigned int a:1;
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unsigned int cond:4;
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unsigned int op2:3;
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unsigned int disp22:22;
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} b;
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} insn;
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*target = 0;
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insn.code = instruction;
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if (insn.b.op == 0
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&& (insn.b.op2 == 2 || insn.b.op2 == 6 || insn.b.op2 == 7))
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{
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if (insn.b.cond == 8)
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val = insn.b.a ? baa : ba;
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else
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val = insn.b.a ? bicca : bicc;
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offset = 4 * ((int) (insn.b.disp22 << 10) >> 10);
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*target = addr + offset;
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}
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return val;
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}
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/* sparc_frame_find_saved_regs ()
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Stores, into a struct frame_saved_regs,
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the addresses of the saved registers of frame described by FRAME_INFO.
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This includes special registers such as pc and fp saved in special
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ways in the stack frame. sp is even more special:
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the address we return for it IS the sp for the next frame.
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Note that on register window machines, we are currently making the
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assumption that window registers are being saved somewhere in the
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frame in which they are being used. If they are stored in an
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inferior frame, find_saved_register will break.
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On the Sun 4, the only time all registers are saved is when
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a dummy frame is involved. Otherwise, the only saved registers
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are the LOCAL and IN registers which are saved as a result
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of the "save/restore" opcodes. This condition is determined
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by address rather than by value.
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The "pc" is not stored in a frame on the SPARC. (What is stored
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is a return address minus 8.) sparc_pop_frame knows how to
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deal with that. Other routines might or might not.
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See tm-sparc.h (PUSH_FRAME and friends) for CRITICAL information
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about how this works. */
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void
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sparc_frame_find_saved_regs (fi, saved_regs_addr)
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struct frame_info *fi;
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struct frame_saved_regs *saved_regs_addr;
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{
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register int regnum;
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FRAME_ADDR frame = FRAME_FP(fi);
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FRAME fid = FRAME_INFO_ID (fi);
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if (!fid)
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fatal ("Bad frame info struct in FRAME_FIND_SAVED_REGS");
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memset (saved_regs_addr, 0, sizeof (*saved_regs_addr));
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if (fi->pc >= (fi->bottom ? fi->bottom :
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read_register (SP_REGNUM))
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&& fi->pc <= FRAME_FP(fi))
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{
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/* Dummy frame. All but the window regs are in there somewhere. */
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for (regnum = G1_REGNUM; regnum < G1_REGNUM+7; regnum++)
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saved_regs_addr->regs[regnum] =
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frame + (regnum - G0_REGNUM) * 4 - 0xa0;
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for (regnum = I0_REGNUM; regnum < I0_REGNUM+8; regnum++)
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saved_regs_addr->regs[regnum] =
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frame + (regnum - I0_REGNUM) * 4 - 0xc0;
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for (regnum = FP0_REGNUM; regnum < FP0_REGNUM + 32; regnum++)
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saved_regs_addr->regs[regnum] =
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frame + (regnum - FP0_REGNUM) * 4 - 0x80;
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for (regnum = Y_REGNUM; regnum < NUM_REGS; regnum++)
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saved_regs_addr->regs[regnum] =
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frame + (regnum - Y_REGNUM) * 4 - 0xe0;
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frame = fi->bottom ?
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fi->bottom : read_register (SP_REGNUM);
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}
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else
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{
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/* Normal frame. Just Local and In registers */
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frame = fi->bottom ?
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fi->bottom : read_register (SP_REGNUM);
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for (regnum = L0_REGNUM; regnum < L0_REGNUM+16; regnum++)
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saved_regs_addr->regs[regnum] =
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frame + (regnum - L0_REGNUM) * REGISTER_RAW_SIZE (L0_REGNUM);
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}
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if (fi->next)
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{
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/* Pull off either the next frame pointer or the stack pointer */
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FRAME_ADDR next_next_frame =
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(fi->next->bottom ?
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fi->next->bottom :
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read_register (SP_REGNUM));
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for (regnum = O0_REGNUM; regnum < O0_REGNUM+8; regnum++)
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saved_regs_addr->regs[regnum] =
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next_next_frame + regnum * REGISTER_RAW_SIZE (O0_REGNUM);
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}
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/* Otherwise, whatever we would get from ptrace(GETREGS) is accurate */
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saved_regs_addr->regs[SP_REGNUM] = FRAME_FP (fi);
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}
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/* Push an empty stack frame, and record in it the current PC, regs, etc.
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We save the non-windowed registers and the ins. The locals and outs
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are new; they don't need to be saved. The i's and l's of
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the last frame were already saved on the stack. */
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/* Definitely see tm-sparc.h for more doc of the frame format here. */
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void
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sparc_push_dummy_frame ()
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{
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CORE_ADDR sp, old_sp;
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char register_temp[0x140];
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old_sp = sp = read_register (SP_REGNUM);
|
||
|
||
/* Y, PS, WIM, TBR, PC, NPC, FPS, CPS regs */
|
||
read_register_bytes (REGISTER_BYTE (Y_REGNUM), ®ister_temp[0],
|
||
REGISTER_RAW_SIZE (Y_REGNUM) * 8);
|
||
|
||
read_register_bytes (REGISTER_BYTE (O0_REGNUM), ®ister_temp[8 * 4],
|
||
REGISTER_RAW_SIZE (O0_REGNUM) * 8);
|
||
|
||
read_register_bytes (REGISTER_BYTE (G0_REGNUM), ®ister_temp[16 * 4],
|
||
REGISTER_RAW_SIZE (G0_REGNUM) * 8);
|
||
|
||
read_register_bytes (REGISTER_BYTE (FP0_REGNUM), ®ister_temp[24 * 4],
|
||
REGISTER_RAW_SIZE (FP0_REGNUM) * 32);
|
||
|
||
sp -= 0x140;
|
||
|
||
write_register (SP_REGNUM, sp);
|
||
|
||
write_memory (sp + 0x60, ®ister_temp[0], (8 + 8 + 8 + 32) * 4);
|
||
|
||
write_register (FP_REGNUM, old_sp);
|
||
|
||
/* Set return address register for the call dummy to the current PC. */
|
||
write_register (I7_REGNUM, read_pc() - 8);
|
||
}
|
||
|
||
/* Discard from the stack the innermost frame, restoring all saved registers.
|
||
|
||
Note that the values stored in fsr by get_frame_saved_regs are *in
|
||
the context of the called frame*. What this means is that the i
|
||
regs of fsr must be restored into the o regs of the (calling) frame that
|
||
we pop into. We don't care about the output regs of the calling frame,
|
||
since unless it's a dummy frame, it won't have any output regs in it.
|
||
|
||
We never have to bother with %l (local) regs, since the called routine's
|
||
locals get tossed, and the calling routine's locals are already saved
|
||
on its stack. */
|
||
|
||
/* Definitely see tm-sparc.h for more doc of the frame format here. */
|
||
|
||
void
|
||
sparc_pop_frame ()
|
||
{
|
||
register FRAME frame = get_current_frame ();
|
||
register CORE_ADDR pc;
|
||
struct frame_saved_regs fsr;
|
||
struct frame_info *fi;
|
||
char raw_buffer[REGISTER_BYTES];
|
||
|
||
fi = get_frame_info (frame);
|
||
get_frame_saved_regs (fi, &fsr);
|
||
if (fsr.regs[FP0_REGNUM])
|
||
{
|
||
read_memory (fsr.regs[FP0_REGNUM], raw_buffer, 32 * 4);
|
||
write_register_bytes (REGISTER_BYTE (FP0_REGNUM), raw_buffer, 32 * 4);
|
||
}
|
||
if (fsr.regs[FPS_REGNUM])
|
||
{
|
||
read_memory (fsr.regs[FPS_REGNUM], raw_buffer, 4);
|
||
write_register_bytes (REGISTER_BYTE (FPS_REGNUM), raw_buffer, 4);
|
||
}
|
||
if (fsr.regs[CPS_REGNUM])
|
||
{
|
||
read_memory (fsr.regs[CPS_REGNUM], raw_buffer, 4);
|
||
write_register_bytes (REGISTER_BYTE (CPS_REGNUM), raw_buffer, 4);
|
||
}
|
||
if (fsr.regs[G1_REGNUM])
|
||
{
|
||
read_memory (fsr.regs[G1_REGNUM], raw_buffer, 7 * 4);
|
||
write_register_bytes (REGISTER_BYTE (G1_REGNUM), raw_buffer, 7 * 4);
|
||
}
|
||
if (fsr.regs[I0_REGNUM])
|
||
{
|
||
CORE_ADDR sp;
|
||
|
||
char reg_temp[REGISTER_BYTES];
|
||
|
||
read_memory (fsr.regs[I0_REGNUM], raw_buffer, 8 * 4);
|
||
|
||
/* Get the ins and locals which we are about to restore. Just
|
||
moving the stack pointer is all that is really needed, except
|
||
store_inferior_registers is then going to write the ins and
|
||
locals from the registers array, so we need to muck with the
|
||
registers array. */
|
||
sp = fsr.regs[SP_REGNUM];
|
||
read_memory (sp, reg_temp, REGISTER_RAW_SIZE (L0_REGNUM) * 16);
|
||
|
||
/* Restore the out registers.
|
||
Among other things this writes the new stack pointer. */
|
||
write_register_bytes (REGISTER_BYTE (O0_REGNUM), raw_buffer,
|
||
REGISTER_RAW_SIZE (O0_REGNUM) * 8);
|
||
|
||
write_register_bytes (REGISTER_BYTE (L0_REGNUM), reg_temp,
|
||
REGISTER_RAW_SIZE (L0_REGNUM) * 16);
|
||
}
|
||
if (fsr.regs[PS_REGNUM])
|
||
write_register (PS_REGNUM, read_memory_integer (fsr.regs[PS_REGNUM], 4));
|
||
if (fsr.regs[Y_REGNUM])
|
||
write_register (Y_REGNUM, read_memory_integer (fsr.regs[Y_REGNUM], 4));
|
||
if (fsr.regs[PC_REGNUM])
|
||
{
|
||
/* Explicitly specified PC (and maybe NPC) -- just restore them. */
|
||
write_register (PC_REGNUM, read_memory_integer (fsr.regs[PC_REGNUM], 4));
|
||
if (fsr.regs[NPC_REGNUM])
|
||
write_register (NPC_REGNUM,
|
||
read_memory_integer (fsr.regs[NPC_REGNUM], 4));
|
||
}
|
||
else if (fsr.regs[I7_REGNUM])
|
||
{
|
||
/* Return address in %i7 -- adjust it, then restore PC and NPC from it */
|
||
pc = PC_ADJUST ((CORE_ADDR) read_memory_integer (fsr.regs[I7_REGNUM], 4));
|
||
write_register (PC_REGNUM, pc);
|
||
write_register (NPC_REGNUM, pc + 4);
|
||
}
|
||
flush_cached_frames ();
|
||
}
|
||
|
||
/* On the Sun 4 under SunOS, the compile will leave a fake insn which
|
||
encodes the structure size being returned. If we detect such
|
||
a fake insn, step past it. */
|
||
|
||
CORE_ADDR
|
||
sparc_pc_adjust(pc)
|
||
CORE_ADDR pc;
|
||
{
|
||
unsigned long insn;
|
||
char buf[4];
|
||
int err;
|
||
|
||
err = target_read_memory (pc + 8, buf, sizeof(long));
|
||
insn = extract_unsigned_integer (buf, 4);
|
||
if ((err == 0) && (insn & 0xfffffe00) == 0)
|
||
return pc+12;
|
||
else
|
||
return pc+8;
|
||
}
|
||
|
||
#ifdef USE_PROC_FS /* Target dependent support for /proc */
|
||
|
||
/* The /proc interface divides the target machine's register set up into
|
||
two different sets, the general register set (gregset) and the floating
|
||
point register set (fpregset). For each set, there is an ioctl to get
|
||
the current register set and another ioctl to set the current values.
|
||
|
||
The actual structure passed through the ioctl interface is, of course,
|
||
naturally machine dependent, and is different for each set of registers.
|
||
For the sparc for example, the general register set is typically defined
|
||
by:
|
||
|
||
typedef int gregset_t[38];
|
||
|
||
#define R_G0 0
|
||
...
|
||
#define R_TBR 37
|
||
|
||
and the floating point set by:
|
||
|
||
typedef struct prfpregset {
|
||
union {
|
||
u_long pr_regs[32];
|
||
double pr_dregs[16];
|
||
} pr_fr;
|
||
void * pr_filler;
|
||
u_long pr_fsr;
|
||
u_char pr_qcnt;
|
||
u_char pr_q_entrysize;
|
||
u_char pr_en;
|
||
u_long pr_q[64];
|
||
} prfpregset_t;
|
||
|
||
These routines provide the packing and unpacking of gregset_t and
|
||
fpregset_t formatted data.
|
||
|
||
*/
|
||
|
||
|
||
/* Given a pointer to a general register set in /proc format (gregset_t *),
|
||
unpack the register contents and supply them as gdb's idea of the current
|
||
register values. */
|
||
|
||
void
|
||
supply_gregset (gregsetp)
|
||
prgregset_t *gregsetp;
|
||
{
|
||
register int regi;
|
||
register prgreg_t *regp = (prgreg_t *) gregsetp;
|
||
|
||
/* GDB register numbers for Gn, On, Ln, In all match /proc reg numbers. */
|
||
for (regi = G0_REGNUM ; regi <= I7_REGNUM ; regi++)
|
||
{
|
||
supply_register (regi, (char *) (regp + regi));
|
||
}
|
||
|
||
/* These require a bit more care. */
|
||
supply_register (PS_REGNUM, (char *) (regp + R_PS));
|
||
supply_register (PC_REGNUM, (char *) (regp + R_PC));
|
||
supply_register (NPC_REGNUM,(char *) (regp + R_nPC));
|
||
supply_register (Y_REGNUM, (char *) (regp + R_Y));
|
||
}
|
||
|
||
void
|
||
fill_gregset (gregsetp, regno)
|
||
prgregset_t *gregsetp;
|
||
int regno;
|
||
{
|
||
int regi;
|
||
register prgreg_t *regp = (prgreg_t *) gregsetp;
|
||
extern char registers[];
|
||
|
||
for (regi = 0 ; regi <= R_I7 ; regi++)
|
||
{
|
||
if ((regno == -1) || (regno == regi))
|
||
{
|
||
*(regp + regi) = *(int *) ®isters[REGISTER_BYTE (regi)];
|
||
}
|
||
}
|
||
if ((regno == -1) || (regno == PS_REGNUM))
|
||
{
|
||
*(regp + R_PS) = *(int *) ®isters[REGISTER_BYTE (PS_REGNUM)];
|
||
}
|
||
if ((regno == -1) || (regno == PC_REGNUM))
|
||
{
|
||
*(regp + R_PC) = *(int *) ®isters[REGISTER_BYTE (PC_REGNUM)];
|
||
}
|
||
if ((regno == -1) || (regno == NPC_REGNUM))
|
||
{
|
||
*(regp + R_nPC) = *(int *) ®isters[REGISTER_BYTE (NPC_REGNUM)];
|
||
}
|
||
if ((regno == -1) || (regno == Y_REGNUM))
|
||
{
|
||
*(regp + R_Y) = *(int *) ®isters[REGISTER_BYTE (Y_REGNUM)];
|
||
}
|
||
}
|
||
|
||
#if defined (FP0_REGNUM)
|
||
|
||
/* Given a pointer to a floating point register set in /proc format
|
||
(fpregset_t *), unpack the register contents and supply them as gdb's
|
||
idea of the current floating point register values. */
|
||
|
||
void
|
||
supply_fpregset (fpregsetp)
|
||
prfpregset_t *fpregsetp;
|
||
{
|
||
register int regi;
|
||
char *from;
|
||
|
||
for (regi = FP0_REGNUM ; regi < FP0_REGNUM+32 ; regi++)
|
||
{
|
||
from = (char *) &fpregsetp->pr_fr.pr_regs[regi-FP0_REGNUM];
|
||
supply_register (regi, from);
|
||
}
|
||
supply_register (FPS_REGNUM, (char *) &(fpregsetp->pr_fsr));
|
||
}
|
||
|
||
/* Given a pointer to a floating point register set in /proc format
|
||
(fpregset_t *), update the register specified by REGNO from gdb's idea
|
||
of the current floating point register set. If REGNO is -1, update
|
||
them all. */
|
||
|
||
void
|
||
fill_fpregset (fpregsetp, regno)
|
||
prfpregset_t *fpregsetp;
|
||
int regno;
|
||
{
|
||
int regi;
|
||
char *to;
|
||
char *from;
|
||
extern char registers[];
|
||
|
||
for (regi = FP0_REGNUM ; regi < FP0_REGNUM+32 ; regi++)
|
||
{
|
||
if ((regno == -1) || (regno == regi))
|
||
{
|
||
from = (char *) ®isters[REGISTER_BYTE (regi)];
|
||
to = (char *) &fpregsetp->pr_fr.pr_regs[regi-FP0_REGNUM];
|
||
memcpy (to, from, REGISTER_RAW_SIZE (regi));
|
||
}
|
||
}
|
||
if ((regno == -1) || (regno == FPS_REGNUM))
|
||
{
|
||
fpregsetp->pr_fsr = *(int *) ®isters[REGISTER_BYTE (FPS_REGNUM)];
|
||
}
|
||
}
|
||
|
||
#endif /* defined (FP0_REGNUM) */
|
||
|
||
#endif /* USE_PROC_FS */
|
||
|
||
|
||
#ifdef GET_LONGJMP_TARGET
|
||
|
||
/* Figure out where the longjmp will land. We expect that we have just entered
|
||
longjmp and haven't yet setup the stack frame, so the args are still in the
|
||
output regs. %o0 (O0_REGNUM) points at the jmp_buf structure from which we
|
||
extract the pc (JB_PC) that we will land at. The pc is copied into ADDR.
|
||
This routine returns true on success */
|
||
|
||
int
|
||
get_longjmp_target(pc)
|
||
CORE_ADDR *pc;
|
||
{
|
||
CORE_ADDR jb_addr;
|
||
#define LONGJMP_TARGET_SIZE 4
|
||
char buf[LONGJMP_TARGET_SIZE];
|
||
|
||
jb_addr = read_register(O0_REGNUM);
|
||
|
||
if (target_read_memory(jb_addr + JB_PC * JB_ELEMENT_SIZE, buf,
|
||
LONGJMP_TARGET_SIZE))
|
||
return 0;
|
||
|
||
*pc = extract_address (buf, LONGJMP_TARGET_SIZE);
|
||
|
||
return 1;
|
||
}
|
||
#endif /* GET_LONGJMP_TARGET */
|