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https://github.com/darlinghq/darling-gdb.git
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3288 lines
95 KiB
C
3288 lines
95 KiB
C
/* CPU data for sh.
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THIS FILE IS MACHINE GENERATED WITH CGEN.
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Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
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This file is part of the GNU Binutils and/or GDB, the GNU debugger.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License along
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with this program; if not, write to the Free Software Foundation, Inc.,
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59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#include "sysdep.h"
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#include <ctype.h>
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#include <stdio.h>
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#include <stdarg.h>
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#include "ansidecl.h"
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#include "bfd.h"
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#include "symcat.h"
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#include "sh-desc.h"
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#include "sh-opc.h"
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#include "opintl.h"
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#include "libiberty.h"
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/* Attributes. */
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static const CGEN_ATTR_ENTRY bool_attr[] =
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{
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{ "#f", 0 },
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{ "#t", 1 },
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{ 0, 0 }
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};
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static const CGEN_ATTR_ENTRY MACH_attr[] =
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{
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{ "base", MACH_BASE },
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{ "sh2", MACH_SH2 },
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{ "sh3", MACH_SH3 },
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{ "sh3e", MACH_SH3E },
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{ "sh4", MACH_SH4 },
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{ "sh5", MACH_SH5 },
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{ "max", MACH_MAX },
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{ 0, 0 }
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};
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static const CGEN_ATTR_ENTRY ISA_attr[] =
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{
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{ "compact", ISA_COMPACT },
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{ "media", ISA_MEDIA },
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{ "max", ISA_MAX },
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{ 0, 0 }
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};
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const CGEN_ATTR_TABLE sh_cgen_ifield_attr_table[] =
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{
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{ "MACH", & MACH_attr[0], & MACH_attr[0] },
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{ "ISA", & ISA_attr[0], & ISA_attr[0] },
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{ "VIRTUAL", &bool_attr[0], &bool_attr[0] },
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{ "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
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{ "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
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{ "RESERVED", &bool_attr[0], &bool_attr[0] },
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{ "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
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{ "SIGNED", &bool_attr[0], &bool_attr[0] },
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{ 0, 0, 0 }
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};
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const CGEN_ATTR_TABLE sh_cgen_hardware_attr_table[] =
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{
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{ "MACH", & MACH_attr[0], & MACH_attr[0] },
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{ "VIRTUAL", &bool_attr[0], &bool_attr[0] },
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{ "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
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{ "PC", &bool_attr[0], &bool_attr[0] },
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{ "PROFILE", &bool_attr[0], &bool_attr[0] },
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{ 0, 0, 0 }
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};
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const CGEN_ATTR_TABLE sh_cgen_operand_attr_table[] =
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{
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{ "MACH", & MACH_attr[0], & MACH_attr[0] },
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{ "ISA", & ISA_attr[0], & ISA_attr[0] },
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{ "VIRTUAL", &bool_attr[0], &bool_attr[0] },
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{ "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
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{ "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
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{ "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
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{ "SIGNED", &bool_attr[0], &bool_attr[0] },
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{ "NEGATIVE", &bool_attr[0], &bool_attr[0] },
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{ "RELAX", &bool_attr[0], &bool_attr[0] },
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{ "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
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{ 0, 0, 0 }
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};
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const CGEN_ATTR_TABLE sh_cgen_insn_attr_table[] =
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{
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{ "MACH", & MACH_attr[0], & MACH_attr[0] },
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{ "ISA", & ISA_attr[0], & ISA_attr[0] },
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{ "ALIAS", &bool_attr[0], &bool_attr[0] },
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{ "VIRTUAL", &bool_attr[0], &bool_attr[0] },
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{ "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
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{ "COND-CTI", &bool_attr[0], &bool_attr[0] },
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{ "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
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{ "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
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{ "RELAXABLE", &bool_attr[0], &bool_attr[0] },
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{ "RELAX", &bool_attr[0], &bool_attr[0] },
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{ "NO-DIS", &bool_attr[0], &bool_attr[0] },
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{ "PBB", &bool_attr[0], &bool_attr[0] },
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{ "ILLSLOT", &bool_attr[0], &bool_attr[0] },
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{ "FP-INSN", &bool_attr[0], &bool_attr[0] },
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{ 0, 0, 0 }
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};
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/* Instruction set variants. */
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static const CGEN_ISA sh_cgen_isa_table[] = {
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{ "media", 32, 32, 32, 32 },
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{ "compact", 16, 16, 16, 16 },
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{ 0, 0, 0, 0, 0 }
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};
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/* Machine variants. */
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static const CGEN_MACH sh_cgen_mach_table[] = {
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{ "sh2", "sh2", MACH_SH2 },
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{ "sh3", "sh3", MACH_SH3 },
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{ "sh3e", "sh3e", MACH_SH3E },
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{ "sh4", "sh4", MACH_SH4 },
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{ "sh5", "sh5", MACH_SH5 },
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{ 0, 0, 0 }
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};
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static CGEN_KEYWORD_ENTRY sh_cgen_opval_frc_names_entries[] =
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{
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{ "fr0", 0, {0, {0}}, 0, 0 },
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{ "fr1", 1, {0, {0}}, 0, 0 },
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{ "fr2", 2, {0, {0}}, 0, 0 },
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{ "fr3", 3, {0, {0}}, 0, 0 },
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{ "fr4", 4, {0, {0}}, 0, 0 },
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{ "fr5", 5, {0, {0}}, 0, 0 },
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{ "fr6", 6, {0, {0}}, 0, 0 },
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{ "fr7", 7, {0, {0}}, 0, 0 },
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{ "fr8", 8, {0, {0}}, 0, 0 },
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{ "fr9", 9, {0, {0}}, 0, 0 },
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{ "fr10", 10, {0, {0}}, 0, 0 },
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{ "fr11", 11, {0, {0}}, 0, 0 },
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{ "fr12", 12, {0, {0}}, 0, 0 },
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{ "fr13", 13, {0, {0}}, 0, 0 },
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{ "fr14", 14, {0, {0}}, 0, 0 },
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{ "fr15", 15, {0, {0}}, 0, 0 }
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};
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CGEN_KEYWORD sh_cgen_opval_frc_names =
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{
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& sh_cgen_opval_frc_names_entries[0],
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16,
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0, 0, 0, 0
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};
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static CGEN_KEYWORD_ENTRY sh_cgen_opval_drc_names_entries[] =
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{
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{ "dr0", 0, {0, {0}}, 0, 0 },
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{ "dr2", 2, {0, {0}}, 0, 0 },
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{ "dr4", 4, {0, {0}}, 0, 0 },
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{ "dr6", 6, {0, {0}}, 0, 0 },
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{ "dr8", 8, {0, {0}}, 0, 0 },
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{ "dr10", 10, {0, {0}}, 0, 0 },
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{ "dr12", 12, {0, {0}}, 0, 0 },
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{ "dr14", 14, {0, {0}}, 0, 0 }
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};
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CGEN_KEYWORD sh_cgen_opval_drc_names =
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{
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& sh_cgen_opval_drc_names_entries[0],
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8,
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0, 0, 0, 0
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};
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static CGEN_KEYWORD_ENTRY sh_cgen_opval_xf_names_entries[] =
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{
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{ "xf0", 0, {0, {0}}, 0, 0 },
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{ "xf1", 1, {0, {0}}, 0, 0 },
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{ "xf2", 2, {0, {0}}, 0, 0 },
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{ "xf3", 3, {0, {0}}, 0, 0 },
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{ "xf4", 4, {0, {0}}, 0, 0 },
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{ "xf5", 5, {0, {0}}, 0, 0 },
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{ "xf6", 6, {0, {0}}, 0, 0 },
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{ "xf7", 7, {0, {0}}, 0, 0 },
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{ "xf8", 8, {0, {0}}, 0, 0 },
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{ "xf9", 9, {0, {0}}, 0, 0 },
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{ "xf10", 10, {0, {0}}, 0, 0 },
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{ "xf11", 11, {0, {0}}, 0, 0 },
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{ "xf12", 12, {0, {0}}, 0, 0 },
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{ "xf13", 13, {0, {0}}, 0, 0 },
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{ "xf14", 14, {0, {0}}, 0, 0 },
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{ "xf15", 15, {0, {0}}, 0, 0 }
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};
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CGEN_KEYWORD sh_cgen_opval_xf_names =
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{
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& sh_cgen_opval_xf_names_entries[0],
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16,
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0, 0, 0, 0
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};
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static CGEN_KEYWORD_ENTRY sh_cgen_opval_h_gr_entries[] =
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{
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{ "r0", 0, {0, {0}}, 0, 0 },
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{ "r1", 1, {0, {0}}, 0, 0 },
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{ "r2", 2, {0, {0}}, 0, 0 },
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{ "r3", 3, {0, {0}}, 0, 0 },
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{ "r4", 4, {0, {0}}, 0, 0 },
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{ "r5", 5, {0, {0}}, 0, 0 },
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{ "r6", 6, {0, {0}}, 0, 0 },
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{ "r7", 7, {0, {0}}, 0, 0 },
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{ "r8", 8, {0, {0}}, 0, 0 },
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{ "r9", 9, {0, {0}}, 0, 0 },
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{ "r10", 10, {0, {0}}, 0, 0 },
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{ "r11", 11, {0, {0}}, 0, 0 },
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{ "r12", 12, {0, {0}}, 0, 0 },
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{ "r13", 13, {0, {0}}, 0, 0 },
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{ "r14", 14, {0, {0}}, 0, 0 },
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{ "r15", 15, {0, {0}}, 0, 0 },
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{ "r16", 16, {0, {0}}, 0, 0 },
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{ "r17", 17, {0, {0}}, 0, 0 },
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{ "r18", 18, {0, {0}}, 0, 0 },
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{ "r19", 19, {0, {0}}, 0, 0 },
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{ "r20", 20, {0, {0}}, 0, 0 },
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{ "r21", 21, {0, {0}}, 0, 0 },
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{ "r22", 22, {0, {0}}, 0, 0 },
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{ "r23", 23, {0, {0}}, 0, 0 },
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{ "r24", 24, {0, {0}}, 0, 0 },
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{ "r25", 25, {0, {0}}, 0, 0 },
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{ "r26", 26, {0, {0}}, 0, 0 },
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{ "r27", 27, {0, {0}}, 0, 0 },
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{ "r28", 28, {0, {0}}, 0, 0 },
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{ "r29", 29, {0, {0}}, 0, 0 },
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{ "r30", 30, {0, {0}}, 0, 0 },
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{ "r31", 31, {0, {0}}, 0, 0 },
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{ "r32", 32, {0, {0}}, 0, 0 },
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{ "r33", 33, {0, {0}}, 0, 0 },
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{ "r34", 34, {0, {0}}, 0, 0 },
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{ "r35", 35, {0, {0}}, 0, 0 },
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{ "r36", 36, {0, {0}}, 0, 0 },
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{ "r37", 37, {0, {0}}, 0, 0 },
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{ "r38", 38, {0, {0}}, 0, 0 },
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{ "r39", 39, {0, {0}}, 0, 0 },
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{ "r40", 40, {0, {0}}, 0, 0 },
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{ "r41", 41, {0, {0}}, 0, 0 },
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{ "r42", 42, {0, {0}}, 0, 0 },
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{ "r43", 43, {0, {0}}, 0, 0 },
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{ "r44", 44, {0, {0}}, 0, 0 },
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{ "r45", 45, {0, {0}}, 0, 0 },
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{ "r46", 46, {0, {0}}, 0, 0 },
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{ "r47", 47, {0, {0}}, 0, 0 },
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{ "r48", 48, {0, {0}}, 0, 0 },
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{ "r49", 49, {0, {0}}, 0, 0 },
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{ "r50", 50, {0, {0}}, 0, 0 },
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{ "r51", 51, {0, {0}}, 0, 0 },
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{ "r52", 52, {0, {0}}, 0, 0 },
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{ "r53", 53, {0, {0}}, 0, 0 },
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{ "r54", 54, {0, {0}}, 0, 0 },
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{ "r55", 55, {0, {0}}, 0, 0 },
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{ "r56", 56, {0, {0}}, 0, 0 },
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{ "r57", 57, {0, {0}}, 0, 0 },
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{ "r58", 58, {0, {0}}, 0, 0 },
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{ "r59", 59, {0, {0}}, 0, 0 },
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{ "r60", 60, {0, {0}}, 0, 0 },
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{ "r61", 61, {0, {0}}, 0, 0 },
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{ "r62", 62, {0, {0}}, 0, 0 },
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{ "r63", 63, {0, {0}}, 0, 0 }
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};
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CGEN_KEYWORD sh_cgen_opval_h_gr =
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{
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& sh_cgen_opval_h_gr_entries[0],
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64,
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0, 0, 0, 0
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};
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static CGEN_KEYWORD_ENTRY sh_cgen_opval_h_grc_entries[] =
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{
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{ "r0", 0, {0, {0}}, 0, 0 },
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{ "r1", 1, {0, {0}}, 0, 0 },
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{ "r2", 2, {0, {0}}, 0, 0 },
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{ "r3", 3, {0, {0}}, 0, 0 },
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{ "r4", 4, {0, {0}}, 0, 0 },
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{ "r5", 5, {0, {0}}, 0, 0 },
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{ "r6", 6, {0, {0}}, 0, 0 },
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{ "r7", 7, {0, {0}}, 0, 0 },
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{ "r8", 8, {0, {0}}, 0, 0 },
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{ "r9", 9, {0, {0}}, 0, 0 },
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{ "r10", 10, {0, {0}}, 0, 0 },
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{ "r11", 11, {0, {0}}, 0, 0 },
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{ "r12", 12, {0, {0}}, 0, 0 },
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{ "r13", 13, {0, {0}}, 0, 0 },
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{ "r14", 14, {0, {0}}, 0, 0 },
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{ "r15", 15, {0, {0}}, 0, 0 }
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};
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CGEN_KEYWORD sh_cgen_opval_h_grc =
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{
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& sh_cgen_opval_h_grc_entries[0],
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16,
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0, 0, 0, 0
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};
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static CGEN_KEYWORD_ENTRY sh_cgen_opval_h_cr_entries[] =
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{
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{ "cr0", 0, {0, {0}}, 0, 0 },
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{ "cr1", 1, {0, {0}}, 0, 0 },
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{ "cr2", 2, {0, {0}}, 0, 0 },
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{ "cr3", 3, {0, {0}}, 0, 0 },
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{ "cr4", 4, {0, {0}}, 0, 0 },
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{ "cr5", 5, {0, {0}}, 0, 0 },
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{ "cr6", 6, {0, {0}}, 0, 0 },
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{ "cr7", 7, {0, {0}}, 0, 0 },
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{ "cr8", 8, {0, {0}}, 0, 0 },
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{ "cr9", 9, {0, {0}}, 0, 0 },
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{ "cr10", 10, {0, {0}}, 0, 0 },
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{ "cr11", 11, {0, {0}}, 0, 0 },
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{ "cr12", 12, {0, {0}}, 0, 0 },
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{ "cr13", 13, {0, {0}}, 0, 0 },
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{ "cr14", 14, {0, {0}}, 0, 0 },
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{ "cr15", 15, {0, {0}}, 0, 0 },
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{ "cr16", 16, {0, {0}}, 0, 0 },
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{ "cr17", 17, {0, {0}}, 0, 0 },
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{ "cr18", 18, {0, {0}}, 0, 0 },
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{ "cr19", 19, {0, {0}}, 0, 0 },
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|
{ "cr20", 20, {0, {0}}, 0, 0 },
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|
{ "cr21", 21, {0, {0}}, 0, 0 },
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|
{ "cr22", 22, {0, {0}}, 0, 0 },
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|
{ "cr23", 23, {0, {0}}, 0, 0 },
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|
{ "cr24", 24, {0, {0}}, 0, 0 },
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|
{ "cr25", 25, {0, {0}}, 0, 0 },
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|
{ "cr26", 26, {0, {0}}, 0, 0 },
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|
{ "cr27", 27, {0, {0}}, 0, 0 },
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|
{ "cr28", 28, {0, {0}}, 0, 0 },
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|
{ "cr29", 29, {0, {0}}, 0, 0 },
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|
{ "cr30", 30, {0, {0}}, 0, 0 },
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|
{ "cr31", 31, {0, {0}}, 0, 0 },
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|
{ "cr32", 32, {0, {0}}, 0, 0 },
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{ "cr33", 33, {0, {0}}, 0, 0 },
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|
{ "cr34", 34, {0, {0}}, 0, 0 },
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{ "cr35", 35, {0, {0}}, 0, 0 },
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{ "cr36", 36, {0, {0}}, 0, 0 },
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{ "cr37", 37, {0, {0}}, 0, 0 },
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|
{ "cr38", 38, {0, {0}}, 0, 0 },
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|
{ "cr39", 39, {0, {0}}, 0, 0 },
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{ "cr40", 40, {0, {0}}, 0, 0 },
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{ "cr41", 41, {0, {0}}, 0, 0 },
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{ "cr42", 42, {0, {0}}, 0, 0 },
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{ "cr43", 43, {0, {0}}, 0, 0 },
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|
{ "cr44", 44, {0, {0}}, 0, 0 },
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{ "cr45", 45, {0, {0}}, 0, 0 },
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{ "cr46", 46, {0, {0}}, 0, 0 },
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{ "cr47", 47, {0, {0}}, 0, 0 },
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{ "cr48", 48, {0, {0}}, 0, 0 },
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{ "cr49", 49, {0, {0}}, 0, 0 },
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{ "cr50", 50, {0, {0}}, 0, 0 },
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{ "cr51", 51, {0, {0}}, 0, 0 },
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{ "cr52", 52, {0, {0}}, 0, 0 },
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{ "cr53", 53, {0, {0}}, 0, 0 },
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|
{ "cr54", 54, {0, {0}}, 0, 0 },
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{ "cr55", 55, {0, {0}}, 0, 0 },
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{ "cr56", 56, {0, {0}}, 0, 0 },
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|
{ "cr57", 57, {0, {0}}, 0, 0 },
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|
{ "cr58", 58, {0, {0}}, 0, 0 },
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|
{ "cr59", 59, {0, {0}}, 0, 0 },
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|
{ "cr60", 60, {0, {0}}, 0, 0 },
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|
{ "cr61", 61, {0, {0}}, 0, 0 },
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|
{ "cr62", 62, {0, {0}}, 0, 0 },
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{ "cr63", 63, {0, {0}}, 0, 0 }
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};
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CGEN_KEYWORD sh_cgen_opval_h_cr =
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{
|
|
& sh_cgen_opval_h_cr_entries[0],
|
|
64,
|
|
0, 0, 0, 0
|
|
};
|
|
|
|
static CGEN_KEYWORD_ENTRY sh_cgen_opval_h_fr_entries[] =
|
|
{
|
|
{ "fr0", 0, {0, {0}}, 0, 0 },
|
|
{ "fr1", 1, {0, {0}}, 0, 0 },
|
|
{ "fr2", 2, {0, {0}}, 0, 0 },
|
|
{ "fr3", 3, {0, {0}}, 0, 0 },
|
|
{ "fr4", 4, {0, {0}}, 0, 0 },
|
|
{ "fr5", 5, {0, {0}}, 0, 0 },
|
|
{ "fr6", 6, {0, {0}}, 0, 0 },
|
|
{ "fr7", 7, {0, {0}}, 0, 0 },
|
|
{ "fr8", 8, {0, {0}}, 0, 0 },
|
|
{ "fr9", 9, {0, {0}}, 0, 0 },
|
|
{ "fr10", 10, {0, {0}}, 0, 0 },
|
|
{ "fr11", 11, {0, {0}}, 0, 0 },
|
|
{ "fr12", 12, {0, {0}}, 0, 0 },
|
|
{ "fr13", 13, {0, {0}}, 0, 0 },
|
|
{ "fr14", 14, {0, {0}}, 0, 0 },
|
|
{ "fr15", 15, {0, {0}}, 0, 0 },
|
|
{ "fr16", 16, {0, {0}}, 0, 0 },
|
|
{ "fr17", 17, {0, {0}}, 0, 0 },
|
|
{ "fr18", 18, {0, {0}}, 0, 0 },
|
|
{ "fr19", 19, {0, {0}}, 0, 0 },
|
|
{ "fr20", 20, {0, {0}}, 0, 0 },
|
|
{ "fr21", 21, {0, {0}}, 0, 0 },
|
|
{ "fr22", 22, {0, {0}}, 0, 0 },
|
|
{ "fr23", 23, {0, {0}}, 0, 0 },
|
|
{ "fr24", 24, {0, {0}}, 0, 0 },
|
|
{ "fr25", 25, {0, {0}}, 0, 0 },
|
|
{ "fr26", 26, {0, {0}}, 0, 0 },
|
|
{ "fr27", 27, {0, {0}}, 0, 0 },
|
|
{ "fr28", 28, {0, {0}}, 0, 0 },
|
|
{ "fr29", 29, {0, {0}}, 0, 0 },
|
|
{ "fr30", 30, {0, {0}}, 0, 0 },
|
|
{ "fr31", 31, {0, {0}}, 0, 0 },
|
|
{ "fr32", 32, {0, {0}}, 0, 0 },
|
|
{ "fr33", 33, {0, {0}}, 0, 0 },
|
|
{ "fr34", 34, {0, {0}}, 0, 0 },
|
|
{ "fr35", 35, {0, {0}}, 0, 0 },
|
|
{ "fr36", 36, {0, {0}}, 0, 0 },
|
|
{ "fr37", 37, {0, {0}}, 0, 0 },
|
|
{ "fr38", 38, {0, {0}}, 0, 0 },
|
|
{ "fr39", 39, {0, {0}}, 0, 0 },
|
|
{ "fr40", 40, {0, {0}}, 0, 0 },
|
|
{ "fr41", 41, {0, {0}}, 0, 0 },
|
|
{ "fr42", 42, {0, {0}}, 0, 0 },
|
|
{ "fr43", 43, {0, {0}}, 0, 0 },
|
|
{ "fr44", 44, {0, {0}}, 0, 0 },
|
|
{ "fr45", 45, {0, {0}}, 0, 0 },
|
|
{ "fr46", 46, {0, {0}}, 0, 0 },
|
|
{ "fr47", 47, {0, {0}}, 0, 0 },
|
|
{ "fr48", 48, {0, {0}}, 0, 0 },
|
|
{ "fr49", 49, {0, {0}}, 0, 0 },
|
|
{ "fr50", 50, {0, {0}}, 0, 0 },
|
|
{ "fr51", 51, {0, {0}}, 0, 0 },
|
|
{ "fr52", 52, {0, {0}}, 0, 0 },
|
|
{ "fr53", 53, {0, {0}}, 0, 0 },
|
|
{ "fr54", 54, {0, {0}}, 0, 0 },
|
|
{ "fr55", 55, {0, {0}}, 0, 0 },
|
|
{ "fr56", 56, {0, {0}}, 0, 0 },
|
|
{ "fr57", 57, {0, {0}}, 0, 0 },
|
|
{ "fr58", 58, {0, {0}}, 0, 0 },
|
|
{ "fr59", 59, {0, {0}}, 0, 0 },
|
|
{ "fr60", 60, {0, {0}}, 0, 0 },
|
|
{ "fr61", 61, {0, {0}}, 0, 0 },
|
|
{ "fr62", 62, {0, {0}}, 0, 0 },
|
|
{ "fr63", 63, {0, {0}}, 0, 0 }
|
|
};
|
|
|
|
CGEN_KEYWORD sh_cgen_opval_h_fr =
|
|
{
|
|
& sh_cgen_opval_h_fr_entries[0],
|
|
64,
|
|
0, 0, 0, 0
|
|
};
|
|
|
|
static CGEN_KEYWORD_ENTRY sh_cgen_opval_h_fp_entries[] =
|
|
{
|
|
{ "fp0", 0, {0, {0}}, 0, 0 },
|
|
{ "fp1", 1, {0, {0}}, 0, 0 },
|
|
{ "fp2", 2, {0, {0}}, 0, 0 },
|
|
{ "fp3", 3, {0, {0}}, 0, 0 },
|
|
{ "fp4", 4, {0, {0}}, 0, 0 },
|
|
{ "fp5", 5, {0, {0}}, 0, 0 },
|
|
{ "fp6", 6, {0, {0}}, 0, 0 },
|
|
{ "fp7", 7, {0, {0}}, 0, 0 },
|
|
{ "fp8", 8, {0, {0}}, 0, 0 },
|
|
{ "fp9", 9, {0, {0}}, 0, 0 },
|
|
{ "fp10", 10, {0, {0}}, 0, 0 },
|
|
{ "fp11", 11, {0, {0}}, 0, 0 },
|
|
{ "fp12", 12, {0, {0}}, 0, 0 },
|
|
{ "fp13", 13, {0, {0}}, 0, 0 },
|
|
{ "fp14", 14, {0, {0}}, 0, 0 },
|
|
{ "fp15", 15, {0, {0}}, 0, 0 },
|
|
{ "fp16", 16, {0, {0}}, 0, 0 },
|
|
{ "fp17", 17, {0, {0}}, 0, 0 },
|
|
{ "fp18", 18, {0, {0}}, 0, 0 },
|
|
{ "fp19", 19, {0, {0}}, 0, 0 },
|
|
{ "fp20", 20, {0, {0}}, 0, 0 },
|
|
{ "fp21", 21, {0, {0}}, 0, 0 },
|
|
{ "fp22", 22, {0, {0}}, 0, 0 },
|
|
{ "fp23", 23, {0, {0}}, 0, 0 },
|
|
{ "fp24", 24, {0, {0}}, 0, 0 },
|
|
{ "fp25", 25, {0, {0}}, 0, 0 },
|
|
{ "fp26", 26, {0, {0}}, 0, 0 },
|
|
{ "fp27", 27, {0, {0}}, 0, 0 },
|
|
{ "fp28", 28, {0, {0}}, 0, 0 },
|
|
{ "fp29", 29, {0, {0}}, 0, 0 },
|
|
{ "fp30", 30, {0, {0}}, 0, 0 },
|
|
{ "fp31", 31, {0, {0}}, 0, 0 }
|
|
};
|
|
|
|
CGEN_KEYWORD sh_cgen_opval_h_fp =
|
|
{
|
|
& sh_cgen_opval_h_fp_entries[0],
|
|
32,
|
|
0, 0, 0, 0
|
|
};
|
|
|
|
static CGEN_KEYWORD_ENTRY sh_cgen_opval_h_fv_entries[] =
|
|
{
|
|
{ "fv0", 0, {0, {0}}, 0, 0 },
|
|
{ "fv1", 1, {0, {0}}, 0, 0 },
|
|
{ "fv2", 2, {0, {0}}, 0, 0 },
|
|
{ "fv3", 3, {0, {0}}, 0, 0 },
|
|
{ "fv4", 4, {0, {0}}, 0, 0 },
|
|
{ "fv5", 5, {0, {0}}, 0, 0 },
|
|
{ "fv6", 6, {0, {0}}, 0, 0 },
|
|
{ "fv7", 7, {0, {0}}, 0, 0 },
|
|
{ "fv8", 8, {0, {0}}, 0, 0 },
|
|
{ "fv9", 9, {0, {0}}, 0, 0 },
|
|
{ "fv10", 10, {0, {0}}, 0, 0 },
|
|
{ "fv11", 11, {0, {0}}, 0, 0 },
|
|
{ "fv12", 12, {0, {0}}, 0, 0 },
|
|
{ "fv13", 13, {0, {0}}, 0, 0 },
|
|
{ "fv14", 14, {0, {0}}, 0, 0 },
|
|
{ "fv15", 15, {0, {0}}, 0, 0 }
|
|
};
|
|
|
|
CGEN_KEYWORD sh_cgen_opval_h_fv =
|
|
{
|
|
& sh_cgen_opval_h_fv_entries[0],
|
|
16,
|
|
0, 0, 0, 0
|
|
};
|
|
|
|
static CGEN_KEYWORD_ENTRY sh_cgen_opval_h_fmtx_entries[] =
|
|
{
|
|
{ "mtrx0", 0, {0, {0}}, 0, 0 },
|
|
{ "mtrx1", 1, {0, {0}}, 0, 0 },
|
|
{ "mtrx2", 2, {0, {0}}, 0, 0 },
|
|
{ "mtrx3", 3, {0, {0}}, 0, 0 }
|
|
};
|
|
|
|
CGEN_KEYWORD sh_cgen_opval_h_fmtx =
|
|
{
|
|
& sh_cgen_opval_h_fmtx_entries[0],
|
|
4,
|
|
0, 0, 0, 0
|
|
};
|
|
|
|
static CGEN_KEYWORD_ENTRY sh_cgen_opval_h_dr_entries[] =
|
|
{
|
|
{ "dr0", 0, {0, {0}}, 0, 0 },
|
|
{ "dr1", 1, {0, {0}}, 0, 0 },
|
|
{ "dr2", 2, {0, {0}}, 0, 0 },
|
|
{ "dr3", 3, {0, {0}}, 0, 0 },
|
|
{ "dr4", 4, {0, {0}}, 0, 0 },
|
|
{ "dr5", 5, {0, {0}}, 0, 0 },
|
|
{ "dr6", 6, {0, {0}}, 0, 0 },
|
|
{ "dr7", 7, {0, {0}}, 0, 0 },
|
|
{ "dr8", 8, {0, {0}}, 0, 0 },
|
|
{ "dr9", 9, {0, {0}}, 0, 0 },
|
|
{ "dr10", 10, {0, {0}}, 0, 0 },
|
|
{ "dr11", 11, {0, {0}}, 0, 0 },
|
|
{ "dr12", 12, {0, {0}}, 0, 0 },
|
|
{ "dr13", 13, {0, {0}}, 0, 0 },
|
|
{ "dr14", 14, {0, {0}}, 0, 0 },
|
|
{ "dr15", 15, {0, {0}}, 0, 0 },
|
|
{ "dr16", 16, {0, {0}}, 0, 0 },
|
|
{ "dr17", 17, {0, {0}}, 0, 0 },
|
|
{ "dr18", 18, {0, {0}}, 0, 0 },
|
|
{ "dr19", 19, {0, {0}}, 0, 0 },
|
|
{ "dr20", 20, {0, {0}}, 0, 0 },
|
|
{ "dr21", 21, {0, {0}}, 0, 0 },
|
|
{ "dr22", 22, {0, {0}}, 0, 0 },
|
|
{ "dr23", 23, {0, {0}}, 0, 0 },
|
|
{ "dr24", 24, {0, {0}}, 0, 0 },
|
|
{ "dr25", 25, {0, {0}}, 0, 0 },
|
|
{ "dr26", 26, {0, {0}}, 0, 0 },
|
|
{ "dr27", 27, {0, {0}}, 0, 0 },
|
|
{ "dr28", 28, {0, {0}}, 0, 0 },
|
|
{ "dr29", 29, {0, {0}}, 0, 0 },
|
|
{ "dr30", 30, {0, {0}}, 0, 0 },
|
|
{ "dr31", 31, {0, {0}}, 0, 0 },
|
|
{ "dr32", 32, {0, {0}}, 0, 0 },
|
|
{ "dr33", 33, {0, {0}}, 0, 0 },
|
|
{ "dr34", 34, {0, {0}}, 0, 0 },
|
|
{ "dr35", 35, {0, {0}}, 0, 0 },
|
|
{ "dr36", 36, {0, {0}}, 0, 0 },
|
|
{ "dr37", 37, {0, {0}}, 0, 0 },
|
|
{ "dr38", 38, {0, {0}}, 0, 0 },
|
|
{ "dr39", 39, {0, {0}}, 0, 0 },
|
|
{ "dr40", 40, {0, {0}}, 0, 0 },
|
|
{ "dr41", 41, {0, {0}}, 0, 0 },
|
|
{ "dr42", 42, {0, {0}}, 0, 0 },
|
|
{ "dr43", 43, {0, {0}}, 0, 0 },
|
|
{ "dr44", 44, {0, {0}}, 0, 0 },
|
|
{ "dr45", 45, {0, {0}}, 0, 0 },
|
|
{ "dr46", 46, {0, {0}}, 0, 0 },
|
|
{ "dr47", 47, {0, {0}}, 0, 0 },
|
|
{ "dr48", 48, {0, {0}}, 0, 0 },
|
|
{ "dr49", 49, {0, {0}}, 0, 0 },
|
|
{ "dr50", 50, {0, {0}}, 0, 0 },
|
|
{ "dr51", 51, {0, {0}}, 0, 0 },
|
|
{ "dr52", 52, {0, {0}}, 0, 0 },
|
|
{ "dr53", 53, {0, {0}}, 0, 0 },
|
|
{ "dr54", 54, {0, {0}}, 0, 0 },
|
|
{ "dr55", 55, {0, {0}}, 0, 0 },
|
|
{ "dr56", 56, {0, {0}}, 0, 0 },
|
|
{ "dr57", 57, {0, {0}}, 0, 0 },
|
|
{ "dr58", 58, {0, {0}}, 0, 0 },
|
|
{ "dr59", 59, {0, {0}}, 0, 0 },
|
|
{ "dr60", 60, {0, {0}}, 0, 0 },
|
|
{ "dr61", 61, {0, {0}}, 0, 0 },
|
|
{ "dr62", 62, {0, {0}}, 0, 0 },
|
|
{ "dr63", 63, {0, {0}}, 0, 0 }
|
|
};
|
|
|
|
CGEN_KEYWORD sh_cgen_opval_h_dr =
|
|
{
|
|
& sh_cgen_opval_h_dr_entries[0],
|
|
64,
|
|
0, 0, 0, 0
|
|
};
|
|
|
|
static CGEN_KEYWORD_ENTRY sh_cgen_opval_h_tr_entries[] =
|
|
{
|
|
{ "tr0", 0, {0, {0}}, 0, 0 },
|
|
{ "tr1", 1, {0, {0}}, 0, 0 },
|
|
{ "tr2", 2, {0, {0}}, 0, 0 },
|
|
{ "tr3", 3, {0, {0}}, 0, 0 },
|
|
{ "tr4", 4, {0, {0}}, 0, 0 },
|
|
{ "tr5", 5, {0, {0}}, 0, 0 },
|
|
{ "tr6", 6, {0, {0}}, 0, 0 },
|
|
{ "tr7", 7, {0, {0}}, 0, 0 }
|
|
};
|
|
|
|
CGEN_KEYWORD sh_cgen_opval_h_tr =
|
|
{
|
|
& sh_cgen_opval_h_tr_entries[0],
|
|
8,
|
|
0, 0, 0, 0
|
|
};
|
|
|
|
static CGEN_KEYWORD_ENTRY sh_cgen_opval_h_fvc_entries[] =
|
|
{
|
|
{ "fv0", 0, {0, {0}}, 0, 0 },
|
|
{ "fv4", 4, {0, {0}}, 0, 0 },
|
|
{ "fv8", 8, {0, {0}}, 0, 0 },
|
|
{ "fv12", 12, {0, {0}}, 0, 0 }
|
|
};
|
|
|
|
CGEN_KEYWORD sh_cgen_opval_h_fvc =
|
|
{
|
|
& sh_cgen_opval_h_fvc_entries[0],
|
|
4,
|
|
0, 0, 0, 0
|
|
};
|
|
|
|
|
|
/* The hardware table. */
|
|
|
|
#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
|
|
#define A(a) (1 << CGEN_HW_##a)
|
|
#else
|
|
#define A(a) (1 << CGEN_HW_/**/a)
|
|
#endif
|
|
|
|
const CGEN_HW_ENTRY sh_cgen_hw_table[] =
|
|
{
|
|
{ "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
|
|
{ "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
|
|
{ "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
|
|
{ "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
|
|
{ "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
|
|
{ "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PC), { (1<<MACH_BASE) } } },
|
|
{ "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & sh_cgen_opval_h_gr, { 0, { (1<<MACH_BASE) } } },
|
|
{ "h-grc", HW_H_GRC, CGEN_ASM_KEYWORD, (PTR) & sh_cgen_opval_h_grc, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
|
|
{ "h-cr", HW_H_CR, CGEN_ASM_KEYWORD, (PTR) & sh_cgen_opval_h_cr, { 0, { (1<<MACH_BASE) } } },
|
|
{ "h-sr", HW_H_SR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
|
|
{ "h-fpscr", HW_H_FPSCR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
|
|
{ "h-frbit", HW_H_FRBIT, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
|
|
{ "h-szbit", HW_H_SZBIT, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
|
|
{ "h-prbit", HW_H_PRBIT, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
|
|
{ "h-sbit", HW_H_SBIT, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
|
|
{ "h-mbit", HW_H_MBIT, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
|
|
{ "h-qbit", HW_H_QBIT, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
|
|
{ "h-fr", HW_H_FR, CGEN_ASM_KEYWORD, (PTR) & sh_cgen_opval_h_fr, { 0, { (1<<MACH_BASE) } } },
|
|
{ "h-fp", HW_H_FP, CGEN_ASM_KEYWORD, (PTR) & sh_cgen_opval_h_fp, { 0, { (1<<MACH_BASE) } } },
|
|
{ "h-fv", HW_H_FV, CGEN_ASM_KEYWORD, (PTR) & sh_cgen_opval_h_fv, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
|
|
{ "h-fmtx", HW_H_FMTX, CGEN_ASM_KEYWORD, (PTR) & sh_cgen_opval_h_fmtx, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
|
|
{ "h-dr", HW_H_DR, CGEN_ASM_KEYWORD, (PTR) & sh_cgen_opval_h_dr, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
|
|
{ "h-tr", HW_H_TR, CGEN_ASM_KEYWORD, (PTR) & sh_cgen_opval_h_tr, { 0, { (1<<MACH_BASE) } } },
|
|
{ "h-endian", HW_H_ENDIAN, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
|
|
{ "h-ism", HW_H_ISM, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
|
|
{ "h-frc", HW_H_FRC, CGEN_ASM_KEYWORD, (PTR) & sh_cgen_opval_frc_names, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
|
|
{ "h-drc", HW_H_DRC, CGEN_ASM_KEYWORD, (PTR) & sh_cgen_opval_drc_names, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
|
|
{ "h-xf", HW_H_XF, CGEN_ASM_KEYWORD, (PTR) & sh_cgen_opval_xf_names, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
|
|
{ "h-xd", HW_H_XD, CGEN_ASM_KEYWORD, (PTR) & sh_cgen_opval_frc_names, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
|
|
{ "h-fvc", HW_H_FVC, CGEN_ASM_KEYWORD, (PTR) & sh_cgen_opval_h_fvc, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
|
|
{ "h-fpccr", HW_H_FPCCR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
|
|
{ "h-gbr", HW_H_GBR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
|
|
{ "h-pr", HW_H_PR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
|
|
{ "h-macl", HW_H_MACL, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
|
|
{ "h-mach", HW_H_MACH, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
|
|
{ "h-tbit", HW_H_TBIT, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
|
|
{ 0, 0, CGEN_ASM_NONE, 0, {0, {0}} }
|
|
};
|
|
|
|
#undef A
|
|
|
|
|
|
/* The instruction field table. */
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#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
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#define A(a) (1 << CGEN_IFLD_##a)
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#else
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#define A(a) (1 << CGEN_IFLD_/**/a)
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#endif
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const CGEN_IFLD sh_cgen_ifld_table[] =
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{
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{ SH_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
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{ SH_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
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{ SH_F_OP4, "f-op4", 0, 16, 15, 4, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
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{ SH_F_OP8, "f-op8", 0, 16, 15, 8, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
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{ SH_F_OP16, "f-op16", 0, 16, 15, 16, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
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{ SH_F_SUB4, "f-sub4", 0, 16, 3, 4, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
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{ SH_F_SUB8, "f-sub8", 0, 16, 7, 8, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
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{ SH_F_SUB10, "f-sub10", 0, 16, 9, 10, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
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{ SH_F_RN, "f-rn", 0, 16, 11, 4, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
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{ SH_F_RM, "f-rm", 0, 16, 7, 4, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
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{ SH_F_8_1, "f-8-1", 0, 16, 8, 1, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
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{ SH_F_DISP8, "f-disp8", 0, 16, 7, 8, { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
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{ SH_F_DISP12, "f-disp12", 0, 16, 11, 12, { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
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{ SH_F_IMM8, "f-imm8", 0, 16, 7, 8, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
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{ SH_F_IMM4, "f-imm4", 0, 16, 3, 4, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
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{ SH_F_IMM4X2, "f-imm4x2", 0, 16, 3, 4, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
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{ SH_F_IMM4X4, "f-imm4x4", 0, 16, 3, 4, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
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{ SH_F_IMM8X2, "f-imm8x2", 0, 16, 7, 8, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
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{ SH_F_IMM8X4, "f-imm8x4", 0, 16, 7, 8, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
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{ SH_F_DN, "f-dn", 0, 16, 11, 3, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
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{ SH_F_DM, "f-dm", 0, 16, 7, 3, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
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{ SH_F_VN, "f-vn", 0, 16, 11, 2, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
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{ SH_F_VM, "f-vm", 0, 16, 9, 2, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
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{ SH_F_XN, "f-xn", 0, 16, 11, 3, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
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{ SH_F_XM, "f-xm", 0, 16, 7, 3, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
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{ SH_F_OP, "f-op", 0, 32, 31, 6, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
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{ SH_F_EXT, "f-ext", 0, 32, 19, 4, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
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{ SH_F_RSVD, "f-rsvd", 0, 32, 3, 4, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
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{ SH_F_LEFT, "f-left", 0, 32, 25, 6, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
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{ SH_F_RIGHT, "f-right", 0, 32, 15, 6, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
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{ SH_F_DEST, "f-dest", 0, 32, 9, 6, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
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{ SH_F_TRA, "f-tra", 0, 32, 6, 3, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
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{ SH_F_TRB, "f-trb", 0, 32, 22, 3, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
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{ SH_F_LIKELY, "f-likely", 0, 32, 9, 1, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
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{ SH_F_25, "f-25", 0, 32, 25, 3, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
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{ SH_F_8_2, "f-8-2", 0, 32, 8, 2, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
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{ SH_F_IMM6, "f-imm6", 0, 32, 15, 6, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
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{ SH_F_IMM10, "f-imm10", 0, 32, 19, 10, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
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{ SH_F_IMM16, "f-imm16", 0, 32, 25, 16, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
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{ SH_F_UIMM6, "f-uimm6", 0, 32, 15, 6, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
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{ SH_F_UIMM16, "f-uimm16", 0, 32, 25, 16, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
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{ SH_F_DISP6, "f-disp6", 0, 32, 15, 6, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
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{ SH_F_DISP6X32, "f-disp6x32", 0, 32, 15, 6, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
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{ SH_F_DISP10, "f-disp10", 0, 32, 19, 10, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
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{ SH_F_DISP10X8, "f-disp10x8", 0, 32, 19, 10, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
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{ SH_F_DISP10X4, "f-disp10x4", 0, 32, 19, 10, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
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{ SH_F_DISP10X2, "f-disp10x2", 0, 32, 19, 10, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
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{ SH_F_DISP16, "f-disp16", 0, 32, 25, 16, { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
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{ 0, 0, 0, 0, 0, 0, {0, {0}} }
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};
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#undef A
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/* The operand table. */
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#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
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#define A(a) (1 << CGEN_OPERAND_##a)
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#else
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#define A(a) (1 << CGEN_OPERAND_/**/a)
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#endif
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#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
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#define OPERAND(op) SH_OPERAND_##op
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#else
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#define OPERAND(op) SH_OPERAND_/**/op
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#endif
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const CGEN_OPERAND sh_cgen_operand_table[] =
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{
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/* pc: program counter */
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{ "pc", SH_OPERAND_PC, HW_H_PC, 0, 0,
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{ 0|A(SEM_ONLY), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
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/* endian: Endian mode */
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{ "endian", SH_OPERAND_ENDIAN, HW_H_ENDIAN, 0, 0,
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{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT)|(1<<ISA_MEDIA) } } },
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/* ism: Instruction set mode */
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{ "ism", SH_OPERAND_ISM, HW_H_ISM, 0, 0,
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{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT)|(1<<ISA_MEDIA) } } },
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/* rm: Left general purpose register */
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{ "rm", SH_OPERAND_RM, HW_H_GRC, 7, 4,
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{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
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/* rn: Right general purpose register */
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{ "rn", SH_OPERAND_RN, HW_H_GRC, 11, 4,
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{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
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/* r0: Register 0 */
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{ "r0", SH_OPERAND_R0, HW_H_GRC, 0, 0,
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{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
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/* frn: Single precision register */
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{ "frn", SH_OPERAND_FRN, HW_H_FRC, 11, 4,
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{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
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/* frm: Single precision register */
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{ "frm", SH_OPERAND_FRM, HW_H_FRC, 7, 4,
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{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
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/* fvn: Left floating point vector */
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{ "fvn", SH_OPERAND_FVN, HW_H_FVC, 11, 2,
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{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
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/* fvm: Right floating point vector */
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{ "fvm", SH_OPERAND_FVM, HW_H_FVC, 9, 2,
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{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
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/* drn: Left double precision register */
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{ "drn", SH_OPERAND_DRN, HW_H_DRC, 11, 3,
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{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
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/* drm: Right double precision register */
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{ "drm", SH_OPERAND_DRM, HW_H_DRC, 7, 3,
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{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
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/* imm4: Immediate value (4 bits) */
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{ "imm4", SH_OPERAND_IMM4, HW_H_SINT, 3, 4,
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{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
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/* imm8: Immediate value (8 bits) */
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{ "imm8", SH_OPERAND_IMM8, HW_H_SINT, 7, 8,
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{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
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/* uimm8: Immediate value (8 bits unsigned) */
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{ "uimm8", SH_OPERAND_UIMM8, HW_H_UINT, 7, 8,
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{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
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/* imm4x2: Immediate value (4 bits, 2x scale) */
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{ "imm4x2", SH_OPERAND_IMM4X2, HW_H_UINT, 3, 4,
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{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
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/* imm4x4: Immediate value (4 bits, 4x scale) */
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{ "imm4x4", SH_OPERAND_IMM4X4, HW_H_UINT, 3, 4,
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{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
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/* imm8x2: Immediate value (8 bits, 2x scale) */
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{ "imm8x2", SH_OPERAND_IMM8X2, HW_H_UINT, 7, 8,
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{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
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/* imm8x4: Immediate value (8 bits, 4x scale) */
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{ "imm8x4", SH_OPERAND_IMM8X4, HW_H_UINT, 7, 8,
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{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
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/* disp8: Displacement (8 bits) */
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{ "disp8", SH_OPERAND_DISP8, HW_H_IADDR, 7, 8,
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{ 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
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/* disp12: Displacement (12 bits) */
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{ "disp12", SH_OPERAND_DISP12, HW_H_IADDR, 11, 12,
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{ 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
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/* rm64: Register m (64 bits) */
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{ "rm64", SH_OPERAND_RM64, HW_H_GR, 7, 4,
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{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
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/* rn64: Register n (64 bits) */
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{ "rn64", SH_OPERAND_RN64, HW_H_GR, 11, 4,
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{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
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/* gbr: Global base register */
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{ "gbr", SH_OPERAND_GBR, HW_H_GBR, 0, 0,
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{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
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/* pr: Procedure link register */
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{ "pr", SH_OPERAND_PR, HW_H_PR, 0, 0,
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{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
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/* fpscr: Floating point status/control register */
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{ "fpscr", SH_OPERAND_FPSCR, HW_H_FPCCR, 0, 0,
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{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
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/* tbit: Condition code flag */
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{ "tbit", SH_OPERAND_TBIT, HW_H_TBIT, 0, 0,
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{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
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/* sbit: Multiply-accumulate saturation flag */
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{ "sbit", SH_OPERAND_SBIT, HW_H_SBIT, 0, 0,
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{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
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/* mbit: Divide-step M flag */
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{ "mbit", SH_OPERAND_MBIT, HW_H_MBIT, 0, 0,
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{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
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/* qbit: Divide-step Q flag */
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{ "qbit", SH_OPERAND_QBIT, HW_H_QBIT, 0, 0,
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{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
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/* fpul: Floating point ??? */
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{ "fpul", SH_OPERAND_FPUL, HW_H_FR, 0, 0,
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{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
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/* frbit: Floating point register bank bit */
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{ "frbit", SH_OPERAND_FRBIT, HW_H_FRBIT, 0, 0,
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{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
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/* szbit: Floating point transfer size bit */
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{ "szbit", SH_OPERAND_SZBIT, HW_H_SZBIT, 0, 0,
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{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
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/* prbit: Floating point precision bit */
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{ "prbit", SH_OPERAND_PRBIT, HW_H_PRBIT, 0, 0,
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{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
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/* macl: Multiply-accumulate low register */
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{ "macl", SH_OPERAND_MACL, HW_H_MACL, 0, 0,
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{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
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/* mach: Multiply-accumulate high register */
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{ "mach", SH_OPERAND_MACH, HW_H_MACH, 0, 0,
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{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
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/* fsdm: bar */
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{ "fsdm", SH_OPERAND_FSDM, HW_H_FRC, 7, 4,
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{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
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/* fsdn: bar */
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{ "fsdn", SH_OPERAND_FSDN, HW_H_FRC, 11, 4,
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{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
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/* rm: Left general purpose reg */
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{ "rm", SH_OPERAND_RM, HW_H_GR, 25, 6,
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{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
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/* rn: Right general purpose reg */
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{ "rn", SH_OPERAND_RN, HW_H_GR, 15, 6,
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{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
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/* rd: Destination general purpose reg */
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{ "rd", SH_OPERAND_RD, HW_H_GR, 9, 6,
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{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
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/* frg: Left single precision register */
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{ "frg", SH_OPERAND_FRG, HW_H_FR, 25, 6,
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{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
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/* frh: Right single precision register */
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{ "frh", SH_OPERAND_FRH, HW_H_FR, 15, 6,
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{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
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/* frf: Destination single precision reg */
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{ "frf", SH_OPERAND_FRF, HW_H_FR, 9, 6,
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{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
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/* frgh: Single precision register pair */
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{ "frgh", SH_OPERAND_FRGH, HW_H_FR, 15, 12,
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{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
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/* fpf: Pair of single precision registers */
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{ "fpf", SH_OPERAND_FPF, HW_H_FP, 9, 6,
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{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
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/* fvg: Left single precision vector */
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{ "fvg", SH_OPERAND_FVG, HW_H_FV, 25, 6,
|
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{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
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/* fvh: Right single precision vector */
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{ "fvh", SH_OPERAND_FVH, HW_H_FV, 15, 6,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
|
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/* fvf: Destination single precision vector */
|
|
{ "fvf", SH_OPERAND_FVF, HW_H_FV, 9, 6,
|
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{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
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/* mtrxg: Left single precision matrix */
|
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{ "mtrxg", SH_OPERAND_MTRXG, HW_H_FMTX, 25, 6,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
|
|
/* drg: Left double precision register */
|
|
{ "drg", SH_OPERAND_DRG, HW_H_DR, 25, 6,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
|
|
/* drh: Right double precision register */
|
|
{ "drh", SH_OPERAND_DRH, HW_H_DR, 15, 6,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
|
|
/* drf: Destination double precision reg */
|
|
{ "drf", SH_OPERAND_DRF, HW_H_DR, 9, 6,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
|
|
/* drgh: Double precision register pair */
|
|
{ "drgh", SH_OPERAND_DRGH, HW_H_DR, 15, 12,
|
|
{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
|
|
/* fpscr: Floating point status register */
|
|
{ "fpscr", SH_OPERAND_FPSCR, HW_H_FPSCR, 0, 0,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
|
|
/* crj: Control register j */
|
|
{ "crj", SH_OPERAND_CRJ, HW_H_CR, 9, 6,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
|
|
/* crk: Control register k */
|
|
{ "crk", SH_OPERAND_CRK, HW_H_CR, 25, 6,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
|
|
/* tra: Target register a */
|
|
{ "tra", SH_OPERAND_TRA, HW_H_TR, 6, 3,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
|
|
/* trb: Target register b */
|
|
{ "trb", SH_OPERAND_TRB, HW_H_TR, 22, 3,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
|
|
/* disp6: Displacement (6 bits) */
|
|
{ "disp6", SH_OPERAND_DISP6, HW_H_SINT, 15, 6,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
|
|
/* disp6x32: Displacement (6 bits, scale 32) */
|
|
{ "disp6x32", SH_OPERAND_DISP6X32, HW_H_SINT, 15, 6,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
|
|
/* disp10: Displacement (10 bits) */
|
|
{ "disp10", SH_OPERAND_DISP10, HW_H_SINT, 19, 10,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
|
|
/* disp10x2: Displacement (10 bits, scale 2) */
|
|
{ "disp10x2", SH_OPERAND_DISP10X2, HW_H_SINT, 19, 10,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
|
|
/* disp10x4: Displacement (10 bits, scale 4) */
|
|
{ "disp10x4", SH_OPERAND_DISP10X4, HW_H_SINT, 19, 10,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
|
|
/* disp10x8: Displacement (10 bits, scale 8) */
|
|
{ "disp10x8", SH_OPERAND_DISP10X8, HW_H_SINT, 19, 10,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
|
|
/* disp16: Displacement (16 bits) */
|
|
{ "disp16", SH_OPERAND_DISP16, HW_H_SINT, 25, 16,
|
|
{ 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
|
|
/* imm6: Immediate (6 bits) */
|
|
{ "imm6", SH_OPERAND_IMM6, HW_H_SINT, 15, 6,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
|
|
/* imm10: Immediate (10 bits) */
|
|
{ "imm10", SH_OPERAND_IMM10, HW_H_SINT, 19, 10,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
|
|
/* imm16: Immediate (16 bits) */
|
|
{ "imm16", SH_OPERAND_IMM16, HW_H_SINT, 25, 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
|
|
/* uimm6: Immediate (6 bits) */
|
|
{ "uimm6", SH_OPERAND_UIMM6, HW_H_UINT, 15, 6,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
|
|
/* uimm16: Unsigned immediate (16 bits) */
|
|
{ "uimm16", SH_OPERAND_UIMM16, HW_H_UINT, 25, 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
|
|
/* likely: Likely branch? */
|
|
{ "likely", SH_OPERAND_LIKELY, HW_H_UINT, 9, 1,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
|
|
{ 0, 0, 0, 0, 0, {0, {0}} }
|
|
};
|
|
|
|
#undef A
|
|
|
|
|
|
/* The instruction table. */
|
|
|
|
#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
|
|
#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
|
|
#define A(a) (1 << CGEN_INSN_##a)
|
|
#else
|
|
#define A(a) (1 << CGEN_INSN_/**/a)
|
|
#endif
|
|
|
|
static const CGEN_IBASE sh_cgen_insn_table[MAX_INSNS] =
|
|
{
|
|
/* Special null first entry.
|
|
A `num' value of zero is thus invalid.
|
|
Also, the special `invalid' insn resides here. */
|
|
{ 0, 0, 0, 0, {0, {0}} },
|
|
/* add $rm, $rn */
|
|
{
|
|
SH_INSN_ADD_COMPACT, "add-compact", "add", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* add #$imm8, $rn */
|
|
{
|
|
SH_INSN_ADDI_COMPACT, "addi-compact", "add", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* addc $rm, $rn */
|
|
{
|
|
SH_INSN_ADDC_COMPACT, "addc-compact", "addc", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* addv $rm, $rn */
|
|
{
|
|
SH_INSN_ADDV_COMPACT, "addv-compact", "addv", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* and $rm64, $rn64 */
|
|
{
|
|
SH_INSN_AND_COMPACT, "and-compact", "and", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* and #$uimm8, r0 */
|
|
{
|
|
SH_INSN_ANDI_COMPACT, "andi-compact", "and", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* and.b #$imm8, @(r0, gbr) */
|
|
{
|
|
SH_INSN_ANDB_COMPACT, "andb-compact", "and.b", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* bf $disp8 */
|
|
{
|
|
SH_INSN_BF_COMPACT, "bf-compact", "bf", 16,
|
|
{ 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* bf/s $disp8 */
|
|
{
|
|
SH_INSN_BFS_COMPACT, "bfs-compact", "bf/s", 16,
|
|
{ 0|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* bra $disp12 */
|
|
{
|
|
SH_INSN_BRA_COMPACT, "bra-compact", "bra", 16,
|
|
{ 0|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* braf $rn */
|
|
{
|
|
SH_INSN_BRAF_COMPACT, "braf-compact", "braf", 16,
|
|
{ 0|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* brk */
|
|
{
|
|
SH_INSN_BRK_COMPACT, "brk-compact", "brk", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* bsr $disp12 */
|
|
{
|
|
SH_INSN_BSR_COMPACT, "bsr-compact", "bsr", 16,
|
|
{ 0|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* bsrf $rn */
|
|
{
|
|
SH_INSN_BSRF_COMPACT, "bsrf-compact", "bsrf", 16,
|
|
{ 0|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* bt $disp8 */
|
|
{
|
|
SH_INSN_BT_COMPACT, "bt-compact", "bt", 16,
|
|
{ 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* bt/s $disp8 */
|
|
{
|
|
SH_INSN_BTS_COMPACT, "bts-compact", "bt/s", 16,
|
|
{ 0|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* clrmac */
|
|
{
|
|
SH_INSN_CLRMAC_COMPACT, "clrmac-compact", "clrmac", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* clrs */
|
|
{
|
|
SH_INSN_CLRS_COMPACT, "clrs-compact", "clrs", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* clrt */
|
|
{
|
|
SH_INSN_CLRT_COMPACT, "clrt-compact", "clrt", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* cmp/eq $rm, $rn */
|
|
{
|
|
SH_INSN_CMPEQ_COMPACT, "cmpeq-compact", "cmp/eq", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* cmp/eq #$imm8, r0 */
|
|
{
|
|
SH_INSN_CMPEQI_COMPACT, "cmpeqi-compact", "cmp/eq", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* cmp/ge $rm, $rn */
|
|
{
|
|
SH_INSN_CMPGE_COMPACT, "cmpge-compact", "cmp/ge", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* cmp/gt $rm, $rn */
|
|
{
|
|
SH_INSN_CMPGT_COMPACT, "cmpgt-compact", "cmp/gt", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* cmp/hi $rm, $rn */
|
|
{
|
|
SH_INSN_CMPHI_COMPACT, "cmphi-compact", "cmp/hi", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* cmp/hs $rm, $rn */
|
|
{
|
|
SH_INSN_CMPHS_COMPACT, "cmphs-compact", "cmp/hs", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* cmp/pl $rn */
|
|
{
|
|
SH_INSN_CMPPL_COMPACT, "cmppl-compact", "cmp/pl", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* cmp/pz $rn */
|
|
{
|
|
SH_INSN_CMPPZ_COMPACT, "cmppz-compact", "cmp/pz", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* cmp/str $rm, $rn */
|
|
{
|
|
SH_INSN_CMPSTR_COMPACT, "cmpstr-compact", "cmp/str", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* div0s $rm, $rn */
|
|
{
|
|
SH_INSN_DIV0S_COMPACT, "div0s-compact", "div0s", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* div0u */
|
|
{
|
|
SH_INSN_DIV0U_COMPACT, "div0u-compact", "div0u", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* div1 $rm, $rn */
|
|
{
|
|
SH_INSN_DIV1_COMPACT, "div1-compact", "div1", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* dmuls.l $rm, $rn */
|
|
{
|
|
SH_INSN_DMULSL_COMPACT, "dmulsl-compact", "dmuls.l", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* dmulu.l $rm, $rn */
|
|
{
|
|
SH_INSN_DMULUL_COMPACT, "dmulul-compact", "dmulu.l", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* dt $rn */
|
|
{
|
|
SH_INSN_DT_COMPACT, "dt-compact", "dt", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* exts.b $rm, $rn */
|
|
{
|
|
SH_INSN_EXTSB_COMPACT, "extsb-compact", "exts.b", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* exts.w $rm, $rn */
|
|
{
|
|
SH_INSN_EXTSW_COMPACT, "extsw-compact", "exts.w", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* extu.b $rm, $rn */
|
|
{
|
|
SH_INSN_EXTUB_COMPACT, "extub-compact", "extu.b", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* extu.w $rm, $rn */
|
|
{
|
|
SH_INSN_EXTUW_COMPACT, "extuw-compact", "extu.w", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* fabs $fsdn */
|
|
{
|
|
SH_INSN_FABS_COMPACT, "fabs-compact", "fabs", 16,
|
|
{ 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* fadd $fsdm, $fsdn */
|
|
{
|
|
SH_INSN_FADD_COMPACT, "fadd-compact", "fadd", 16,
|
|
{ 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* fcmp/eq $fsdm, $fsdn */
|
|
{
|
|
SH_INSN_FCMPEQ_COMPACT, "fcmpeq-compact", "fcmp/eq", 16,
|
|
{ 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* fcmp/gt $fsdm, $fsdn */
|
|
{
|
|
SH_INSN_FCMPGT_COMPACT, "fcmpgt-compact", "fcmp/gt", 16,
|
|
{ 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* fcnvds $drn, fpul */
|
|
{
|
|
SH_INSN_FCNVDS_COMPACT, "fcnvds-compact", "fcnvds", 16,
|
|
{ 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* fcnvsd fpul, $drn */
|
|
{
|
|
SH_INSN_FCNVSD_COMPACT, "fcnvsd-compact", "fcnvsd", 16,
|
|
{ 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* fdiv $fsdm, $fsdn */
|
|
{
|
|
SH_INSN_FDIV_COMPACT, "fdiv-compact", "fdiv", 16,
|
|
{ 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* fipr $fvm, $fvn */
|
|
{
|
|
SH_INSN_FIPR_COMPACT, "fipr-compact", "fipr", 16,
|
|
{ 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* flds $frn */
|
|
{
|
|
SH_INSN_FLDS_COMPACT, "flds-compact", "flds", 16,
|
|
{ 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* fldi0 $frn */
|
|
{
|
|
SH_INSN_FLDI0_COMPACT, "fldi0-compact", "fldi0", 16,
|
|
{ 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* fldi1 $frn */
|
|
{
|
|
SH_INSN_FLDI1_COMPACT, "fldi1-compact", "fldi1", 16,
|
|
{ 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* float fpul, $fsdn */
|
|
{
|
|
SH_INSN_FLOAT_COMPACT, "float-compact", "float", 16,
|
|
{ 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* fmac fr0, $frm, $frn */
|
|
{
|
|
SH_INSN_FMAC_COMPACT, "fmac-compact", "fmac", 16,
|
|
{ 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* fmov $frm, $frn */
|
|
{
|
|
SH_INSN_FMOV1_COMPACT, "fmov1-compact", "fmov", 16,
|
|
{ 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* fmov @$rm, $frn */
|
|
{
|
|
SH_INSN_FMOV2_COMPACT, "fmov2-compact", "fmov", 16,
|
|
{ 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* fmov @${rm}+, frn */
|
|
{
|
|
SH_INSN_FMOV3_COMPACT, "fmov3-compact", "fmov", 16,
|
|
{ 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* fmov @(r0, $rm), $frn */
|
|
{
|
|
SH_INSN_FMOV4_COMPACT, "fmov4-compact", "fmov", 16,
|
|
{ 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* fmov $frm, @$rn */
|
|
{
|
|
SH_INSN_FMOV5_COMPACT, "fmov5-compact", "fmov", 16,
|
|
{ 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* fmov $frm, @-$rn */
|
|
{
|
|
SH_INSN_FMOV6_COMPACT, "fmov6-compact", "fmov", 16,
|
|
{ 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* fmov $frm, @(r0, $rn) */
|
|
{
|
|
SH_INSN_FMOV7_COMPACT, "fmov7-compact", "fmov", 16,
|
|
{ 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* fmul $fsdm, $fsdn */
|
|
{
|
|
SH_INSN_FMUL_COMPACT, "fmul-compact", "fmul", 16,
|
|
{ 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* fneg $fsdn */
|
|
{
|
|
SH_INSN_FNEG_COMPACT, "fneg-compact", "fneg", 16,
|
|
{ 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* frchg */
|
|
{
|
|
SH_INSN_FRCHG_COMPACT, "frchg-compact", "frchg", 16,
|
|
{ 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* fschg */
|
|
{
|
|
SH_INSN_FSCHG_COMPACT, "fschg-compact", "fschg", 16,
|
|
{ 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* fsqrt $fsdn */
|
|
{
|
|
SH_INSN_FSQRT_COMPACT, "fsqrt-compact", "fsqrt", 16,
|
|
{ 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* fsts fpul, $frn */
|
|
{
|
|
SH_INSN_FSTS_COMPACT, "fsts-compact", "fsts", 16,
|
|
{ 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* fsub $fsdm, $fsdn */
|
|
{
|
|
SH_INSN_FSUB_COMPACT, "fsub-compact", "fsub", 16,
|
|
{ 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* ftrc $fsdn, fpul */
|
|
{
|
|
SH_INSN_FTRC_COMPACT, "ftrc-compact", "ftrc", 16,
|
|
{ 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* ftrv xmtrx, $fvn */
|
|
{
|
|
SH_INSN_FTRV_COMPACT, "ftrv-compact", "ftrv", 16,
|
|
{ 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* jmp @$rn */
|
|
{
|
|
SH_INSN_JMP_COMPACT, "jmp-compact", "jmp", 16,
|
|
{ 0|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* jsr @$rn */
|
|
{
|
|
SH_INSN_JSR_COMPACT, "jsr-compact", "jsr", 16,
|
|
{ 0|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* ldc $rn, gbr */
|
|
{
|
|
SH_INSN_LDC_COMPACT, "ldc-compact", "ldc", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* ldc.l @${rn}+, gbr */
|
|
{
|
|
SH_INSN_LDCL_COMPACT, "ldcl-compact", "ldc.l", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* lds $rn, fpscr */
|
|
{
|
|
SH_INSN_LDS_FPSCR_COMPACT, "lds-fpscr-compact", "lds", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* lds.l @${rn}+, fpscr */
|
|
{
|
|
SH_INSN_LDSL_FPSCR_COMPACT, "ldsl-fpscr-compact", "lds.l", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* lds $rn, fpul */
|
|
{
|
|
SH_INSN_LDS_FPUL_COMPACT, "lds-fpul-compact", "lds", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* lds.l @${rn}+, fpul */
|
|
{
|
|
SH_INSN_LDSL_FPUL_COMPACT, "ldsl-fpul-compact", "lds.l", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* lds $rn, mach */
|
|
{
|
|
SH_INSN_LDS_MACH_COMPACT, "lds-mach-compact", "lds", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* lds.l @${rn}+, mach */
|
|
{
|
|
SH_INSN_LDSL_MACH_COMPACT, "ldsl-mach-compact", "lds.l", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* lds $rn, macl */
|
|
{
|
|
SH_INSN_LDS_MACL_COMPACT, "lds-macl-compact", "lds", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* lds.l @${rn}+, macl */
|
|
{
|
|
SH_INSN_LDSL_MACL_COMPACT, "ldsl-macl-compact", "lds.l", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* lds $rn, pr */
|
|
{
|
|
SH_INSN_LDS_PR_COMPACT, "lds-pr-compact", "lds", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* lds.l @${rn}+, pr */
|
|
{
|
|
SH_INSN_LDSL_PR_COMPACT, "ldsl-pr-compact", "lds.l", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* mac.l @${rm}+, @${rn}+ */
|
|
{
|
|
SH_INSN_MACL_COMPACT, "macl-compact", "mac.l", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* mac.w @${rm}+, @${rn}+ */
|
|
{
|
|
SH_INSN_MACW_COMPACT, "macw-compact", "mac.w", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* mov $rm64, $rn64 */
|
|
{
|
|
SH_INSN_MOV_COMPACT, "mov-compact", "mov", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* mov #$imm8, $rn */
|
|
{
|
|
SH_INSN_MOVI_COMPACT, "movi-compact", "mov", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* mov.b $rm, @$rn */
|
|
{
|
|
SH_INSN_MOVB1_COMPACT, "movb1-compact", "mov.b", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* mov.b $rm, @-$rn */
|
|
{
|
|
SH_INSN_MOVB2_COMPACT, "movb2-compact", "mov.b", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* mov.b $rm, @(r0,$rn) */
|
|
{
|
|
SH_INSN_MOVB3_COMPACT, "movb3-compact", "mov.b", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* mov.b r0, @($imm8, gbr) */
|
|
{
|
|
SH_INSN_MOVB4_COMPACT, "movb4-compact", "mov.b", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* mov.b r0, @($imm4, $rm) */
|
|
{
|
|
SH_INSN_MOVB5_COMPACT, "movb5-compact", "mov.b", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* mov.b @$rm, $rn */
|
|
{
|
|
SH_INSN_MOVB6_COMPACT, "movb6-compact", "mov.b", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* mov.b @${rm}+, $rn */
|
|
{
|
|
SH_INSN_MOVB7_COMPACT, "movb7-compact", "mov.b", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* mov.b @(r0, $rm), $rn */
|
|
{
|
|
SH_INSN_MOVB8_COMPACT, "movb8-compact", "mov.b", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* mov.b @($imm8, gbr), r0 */
|
|
{
|
|
SH_INSN_MOVB9_COMPACT, "movb9-compact", "mov.b", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* mov.b @($imm4, $rm), r0 */
|
|
{
|
|
SH_INSN_MOVB10_COMPACT, "movb10-compact", "mov.b", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* mov.l $rm, @$rn */
|
|
{
|
|
SH_INSN_MOVL1_COMPACT, "movl1-compact", "mov.l", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* mov.l $rm, @-$rn */
|
|
{
|
|
SH_INSN_MOVL2_COMPACT, "movl2-compact", "mov.l", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* mov.l $rm, @(r0, $rn) */
|
|
{
|
|
SH_INSN_MOVL3_COMPACT, "movl3-compact", "mov.l", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* mov.l r0, @($imm8x4, gbr) */
|
|
{
|
|
SH_INSN_MOVL4_COMPACT, "movl4-compact", "mov.l", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* mov.l $rm, @($imm4x4, $rn) */
|
|
{
|
|
SH_INSN_MOVL5_COMPACT, "movl5-compact", "mov.l", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* mov.l @$rm, $rn */
|
|
{
|
|
SH_INSN_MOVL6_COMPACT, "movl6-compact", "mov.l", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* mov.l @${rm}+, $rn */
|
|
{
|
|
SH_INSN_MOVL7_COMPACT, "movl7-compact", "mov.l", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* mov.l @(r0, $rm), $rn */
|
|
{
|
|
SH_INSN_MOVL8_COMPACT, "movl8-compact", "mov.l", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* mov.l @($imm8x4, gbr), r0 */
|
|
{
|
|
SH_INSN_MOVL9_COMPACT, "movl9-compact", "mov.l", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* mov.l @($imm8x4, pc), $rn */
|
|
{
|
|
SH_INSN_MOVL10_COMPACT, "movl10-compact", "mov.l", 16,
|
|
{ 0|A(ILLSLOT), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* mov.l @($imm4x4, $rm), $rn */
|
|
{
|
|
SH_INSN_MOVL11_COMPACT, "movl11-compact", "mov.l", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* mov.w $rm, @$rn */
|
|
{
|
|
SH_INSN_MOVW1_COMPACT, "movw1-compact", "mov.w", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* mov.w $rm, @-$rn */
|
|
{
|
|
SH_INSN_MOVW2_COMPACT, "movw2-compact", "mov.w", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* mov.w $rm, @(r0, $rn) */
|
|
{
|
|
SH_INSN_MOVW3_COMPACT, "movw3-compact", "mov.w", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* mov.w r0, @($imm8x2, gbr) */
|
|
{
|
|
SH_INSN_MOVW4_COMPACT, "movw4-compact", "mov.w", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* mov.w r0, @($imm4x2, $rn) */
|
|
{
|
|
SH_INSN_MOVW5_COMPACT, "movw5-compact", "mov.w", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* mov.w @$rm, $rn */
|
|
{
|
|
SH_INSN_MOVW6_COMPACT, "movw6-compact", "mov.w", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* mov.w @${rm}+, $rn */
|
|
{
|
|
SH_INSN_MOVW7_COMPACT, "movw7-compact", "mov.w", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* mov.w @(r0, $rm), $rn */
|
|
{
|
|
SH_INSN_MOVW8_COMPACT, "movw8-compact", "mov.w", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* mov.w @($imm8x2, gbr), r0 */
|
|
{
|
|
SH_INSN_MOVW9_COMPACT, "movw9-compact", "mov.w", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* mov.w @($imm8x2, pc), $rn */
|
|
{
|
|
SH_INSN_MOVW10_COMPACT, "movw10-compact", "mov.w", 16,
|
|
{ 0|A(ILLSLOT), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* mov.w @($imm4x2, $rm), r0 */
|
|
{
|
|
SH_INSN_MOVW11_COMPACT, "movw11-compact", "mov.w", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* mova @($imm8x4, pc), r0 */
|
|
{
|
|
SH_INSN_MOVA_COMPACT, "mova-compact", "mova", 16,
|
|
{ 0|A(ILLSLOT), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* movca.l r0, @$rn */
|
|
{
|
|
SH_INSN_MOVCAL_COMPACT, "movcal-compact", "movca.l", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* movt $rn */
|
|
{
|
|
SH_INSN_MOVT_COMPACT, "movt-compact", "movt", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* mul.l $rm, $rn */
|
|
{
|
|
SH_INSN_MULL_COMPACT, "mull-compact", "mul.l", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* muls.w $rm, $rn */
|
|
{
|
|
SH_INSN_MULSW_COMPACT, "mulsw-compact", "muls.w", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* mulu.w $rm, $rn */
|
|
{
|
|
SH_INSN_MULUW_COMPACT, "muluw-compact", "mulu.w", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* neg $rm, $rn */
|
|
{
|
|
SH_INSN_NEG_COMPACT, "neg-compact", "neg", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* negc $rm, $rn */
|
|
{
|
|
SH_INSN_NEGC_COMPACT, "negc-compact", "negc", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* nop */
|
|
{
|
|
SH_INSN_NOP_COMPACT, "nop-compact", "nop", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* not $rm64, $rn64 */
|
|
{
|
|
SH_INSN_NOT_COMPACT, "not-compact", "not", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* ocbi @$rn */
|
|
{
|
|
SH_INSN_OCBI_COMPACT, "ocbi-compact", "ocbi", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* ocbp @$rn */
|
|
{
|
|
SH_INSN_OCBP_COMPACT, "ocbp-compact", "ocbp", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* ocbwb @$rn */
|
|
{
|
|
SH_INSN_OCBWB_COMPACT, "ocbwb-compact", "ocbwb", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* or $rm64, $rn64 */
|
|
{
|
|
SH_INSN_OR_COMPACT, "or-compact", "or", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* or #$uimm8, r0 */
|
|
{
|
|
SH_INSN_ORI_COMPACT, "ori-compact", "or", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* or.b #$imm8, @(r0, gbr) */
|
|
{
|
|
SH_INSN_ORB_COMPACT, "orb-compact", "or.b", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* pref @$rn */
|
|
{
|
|
SH_INSN_PREF_COMPACT, "pref-compact", "pref", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* rotcl $rn */
|
|
{
|
|
SH_INSN_ROTCL_COMPACT, "rotcl-compact", "rotcl", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* rotcr $rn */
|
|
{
|
|
SH_INSN_ROTCR_COMPACT, "rotcr-compact", "rotcr", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* rotl $rn */
|
|
{
|
|
SH_INSN_ROTL_COMPACT, "rotl-compact", "rotl", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* rotr $rn */
|
|
{
|
|
SH_INSN_ROTR_COMPACT, "rotr-compact", "rotr", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* rts */
|
|
{
|
|
SH_INSN_RTS_COMPACT, "rts-compact", "rts", 16,
|
|
{ 0|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* sets */
|
|
{
|
|
SH_INSN_SETS_COMPACT, "sets-compact", "sets", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* sett */
|
|
{
|
|
SH_INSN_SETT_COMPACT, "sett-compact", "sett", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* shad $rm, $rn */
|
|
{
|
|
SH_INSN_SHAD_COMPACT, "shad-compact", "shad", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* shal $rn */
|
|
{
|
|
SH_INSN_SHAL_COMPACT, "shal-compact", "shal", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* shar $rn */
|
|
{
|
|
SH_INSN_SHAR_COMPACT, "shar-compact", "shar", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* shld $rm, $rn */
|
|
{
|
|
SH_INSN_SHLD_COMPACT, "shld-compact", "shld", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* shll $rn */
|
|
{
|
|
SH_INSN_SHLL_COMPACT, "shll-compact", "shll", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* shll2 $rn */
|
|
{
|
|
SH_INSN_SHLL2_COMPACT, "shll2-compact", "shll2", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* shll8 $rn */
|
|
{
|
|
SH_INSN_SHLL8_COMPACT, "shll8-compact", "shll8", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* shll16 $rn */
|
|
{
|
|
SH_INSN_SHLL16_COMPACT, "shll16-compact", "shll16", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* shlr $rn */
|
|
{
|
|
SH_INSN_SHLR_COMPACT, "shlr-compact", "shlr", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* shlr2 $rn */
|
|
{
|
|
SH_INSN_SHLR2_COMPACT, "shlr2-compact", "shlr2", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* shlr8 $rn */
|
|
{
|
|
SH_INSN_SHLR8_COMPACT, "shlr8-compact", "shlr8", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* shlr16 $rn */
|
|
{
|
|
SH_INSN_SHLR16_COMPACT, "shlr16-compact", "shlr16", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* stc gbr, $rn */
|
|
{
|
|
SH_INSN_STC_GBR_COMPACT, "stc-gbr-compact", "stc", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* stc.l gbr, @-$rn */
|
|
{
|
|
SH_INSN_STCL_GBR_COMPACT, "stcl-gbr-compact", "stc.l", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* sts fpscr, $rn */
|
|
{
|
|
SH_INSN_STS_FPSCR_COMPACT, "sts-fpscr-compact", "sts", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* sts.l fpscr, @-$rn */
|
|
{
|
|
SH_INSN_STSL_FPSCR_COMPACT, "stsl-fpscr-compact", "sts.l", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* sts fpul, $rn */
|
|
{
|
|
SH_INSN_STS_FPUL_COMPACT, "sts-fpul-compact", "sts", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* sts.l fpul, @-$rn */
|
|
{
|
|
SH_INSN_STSL_FPUL_COMPACT, "stsl-fpul-compact", "sts.l", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* sts mach, $rn */
|
|
{
|
|
SH_INSN_STS_MACH_COMPACT, "sts-mach-compact", "sts", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* sts.l mach, @-$rn */
|
|
{
|
|
SH_INSN_STSL_MACH_COMPACT, "stsl-mach-compact", "sts.l", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* sts macl, $rn */
|
|
{
|
|
SH_INSN_STS_MACL_COMPACT, "sts-macl-compact", "sts", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* sts.l macl, @-$rn */
|
|
{
|
|
SH_INSN_STSL_MACL_COMPACT, "stsl-macl-compact", "sts.l", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* sts pr, $rn */
|
|
{
|
|
SH_INSN_STS_PR_COMPACT, "sts-pr-compact", "sts", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* sts.l pr, @-$rn */
|
|
{
|
|
SH_INSN_STSL_PR_COMPACT, "stsl-pr-compact", "sts.l", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* sub $rm, $rn */
|
|
{
|
|
SH_INSN_SUB_COMPACT, "sub-compact", "sub", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* subc $rm, $rn */
|
|
{
|
|
SH_INSN_SUBC_COMPACT, "subc-compact", "subc", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* subv $rm, $rn */
|
|
{
|
|
SH_INSN_SUBV_COMPACT, "subv-compact", "subv", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* swap.b $rm, $rn */
|
|
{
|
|
SH_INSN_SWAPB_COMPACT, "swapb-compact", "swap.b", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* swap.w $rm, $rn */
|
|
{
|
|
SH_INSN_SWAPW_COMPACT, "swapw-compact", "swap.w", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* tas.b @$rn */
|
|
{
|
|
SH_INSN_TASB_COMPACT, "tasb-compact", "tas.b", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* trapa #$uimm8 */
|
|
{
|
|
SH_INSN_TRAPA_COMPACT, "trapa-compact", "trapa", 16,
|
|
{ 0|A(ILLSLOT), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* tst $rm, $rn */
|
|
{
|
|
SH_INSN_TST_COMPACT, "tst-compact", "tst", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* tst #$uimm8, r0 */
|
|
{
|
|
SH_INSN_TSTI_COMPACT, "tsti-compact", "tst", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* tst.b #$imm8, @(r0, gbr) */
|
|
{
|
|
SH_INSN_TSTB_COMPACT, "tstb-compact", "tst.b", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* xor $rm64, $rn64 */
|
|
{
|
|
SH_INSN_XOR_COMPACT, "xor-compact", "xor", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* xor #$uimm8, r0 */
|
|
{
|
|
SH_INSN_XORI_COMPACT, "xori-compact", "xor", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* xor.b #$imm8, @(r0, gbr) */
|
|
{
|
|
SH_INSN_XORB_COMPACT, "xorb-compact", "xor.b", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* xtrct $rm, $rn */
|
|
{
|
|
SH_INSN_XTRCT_COMPACT, "xtrct-compact", "xtrct", 16,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
|
|
},
|
|
/* add $rm, $rn, $rd */
|
|
{
|
|
SH_INSN_ADD, "add", "add", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* add.l $rm, $rn, $rd */
|
|
{
|
|
SH_INSN_ADDL, "addl", "add.l", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* addi $rm, $disp10, $rd */
|
|
{
|
|
SH_INSN_ADDI, "addi", "addi", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* addi.l $rm, $disp10, $rd */
|
|
{
|
|
SH_INSN_ADDIL, "addil", "addi.l", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* addz.l $rm, $rn, $rd */
|
|
{
|
|
SH_INSN_ADDZL, "addzl", "addz.l", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* alloco $rm, $disp6x32 */
|
|
{
|
|
SH_INSN_ALLOCO, "alloco", "alloco", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* and $rm, $rn, $rd */
|
|
{
|
|
SH_INSN_AND, "and", "and", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* andc $rm, $rn, $rd */
|
|
{
|
|
SH_INSN_ANDC, "andc", "andc", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* andi $rm, $disp10, $rd */
|
|
{
|
|
SH_INSN_ANDI, "andi", "andi", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* beq$likely $rm, $rn, $tra */
|
|
{
|
|
SH_INSN_BEQ, "beq", "beq", 32,
|
|
{ 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* beqi$likely $rm, $imm6, $tra */
|
|
{
|
|
SH_INSN_BEQI, "beqi", "beqi", 32,
|
|
{ 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* bge$likely $rm, $rn, $tra */
|
|
{
|
|
SH_INSN_BGE, "bge", "bge", 32,
|
|
{ 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* bgeu$likely $rm, $rn, $tra */
|
|
{
|
|
SH_INSN_BGEU, "bgeu", "bgeu", 32,
|
|
{ 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* bgt$likely $rm, $rn, $tra */
|
|
{
|
|
SH_INSN_BGT, "bgt", "bgt", 32,
|
|
{ 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* bgtu$likely $rm, $rn, $tra */
|
|
{
|
|
SH_INSN_BGTU, "bgtu", "bgtu", 32,
|
|
{ 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* blink $trb, $rd */
|
|
{
|
|
SH_INSN_BLINK, "blink", "blink", 32,
|
|
{ 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* bne$likely $rm, $rn, $tra */
|
|
{
|
|
SH_INSN_BNE, "bne", "bne", 32,
|
|
{ 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* bnei$likely $rm, $imm6, $tra */
|
|
{
|
|
SH_INSN_BNEI, "bnei", "bnei", 32,
|
|
{ 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* brk */
|
|
{
|
|
SH_INSN_BRK, "brk", "brk", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* byterev $rm, $rd */
|
|
{
|
|
SH_INSN_BYTEREV, "byterev", "byterev", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* cmpeq $rm, $rn, $rd */
|
|
{
|
|
SH_INSN_CMPEQ, "cmpeq", "cmpeq", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* cmpgt $rm, $rn, $rd */
|
|
{
|
|
SH_INSN_CMPGT, "cmpgt", "cmpgt", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* cmpgtu $rm,$rn, $rd */
|
|
{
|
|
SH_INSN_CMPGTU, "cmpgtu", "cmpgtu", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* cmveq $rm, $rn, $rd */
|
|
{
|
|
SH_INSN_CMVEQ, "cmveq", "cmveq", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* cmvne $rm, $rn, $rd */
|
|
{
|
|
SH_INSN_CMVNE, "cmvne", "cmvne", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* fabs.d $drgh, $drf */
|
|
{
|
|
SH_INSN_FABSD, "fabsd", "fabs.d", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* fabs.s $frgh, $frf */
|
|
{
|
|
SH_INSN_FABSS, "fabss", "fabs.s", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* fadd.d $drg, $drh, $drf */
|
|
{
|
|
SH_INSN_FADDD, "faddd", "fadd.d", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* fadd.s $frg, $frh, $frf */
|
|
{
|
|
SH_INSN_FADDS, "fadds", "fadd.s", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* fcmpeq.d $drg, $drh, $rd */
|
|
{
|
|
SH_INSN_FCMPEQD, "fcmpeqd", "fcmpeq.d", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* fcmpeq.s $frg, $frh, $rd */
|
|
{
|
|
SH_INSN_FCMPEQS, "fcmpeqs", "fcmpeq.s", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* fcmpge.d $drg, $drh, $rd */
|
|
{
|
|
SH_INSN_FCMPGED, "fcmpged", "fcmpge.d", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* fcmpge.s $frg, $frh, $rd */
|
|
{
|
|
SH_INSN_FCMPGES, "fcmpges", "fcmpge.s", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* fcmpgt.d $drg, $drh, $rd */
|
|
{
|
|
SH_INSN_FCMPGTD, "fcmpgtd", "fcmpgt.d", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* fcmpgt.s $frg, $frh, $rd */
|
|
{
|
|
SH_INSN_FCMPGTS, "fcmpgts", "fcmpgt.s", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* fcmpun.d $drg, $drh, $rd */
|
|
{
|
|
SH_INSN_FCMPUND, "fcmpund", "fcmpun.d", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* fcmpun.s $frg, $frh, $rd */
|
|
{
|
|
SH_INSN_FCMPUNS, "fcmpuns", "fcmpun.s", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* fcnv.ds $drgh, $frf */
|
|
{
|
|
SH_INSN_FCNVDS, "fcnvds", "fcnv.ds", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* fcnv.sd $frgh, $drf */
|
|
{
|
|
SH_INSN_FCNVSD, "fcnvsd", "fcnv.sd", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* fdiv.d $drg, $drh, $drf */
|
|
{
|
|
SH_INSN_FDIVD, "fdivd", "fdiv.d", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* fdiv.s $frg, $frh, $frf */
|
|
{
|
|
SH_INSN_FDIVS, "fdivs", "fdiv.s", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* fgetscr $frf */
|
|
{
|
|
SH_INSN_FGETSCR, "fgetscr", "fgetscr", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* fipr.s $fvg, $fvh, $frf */
|
|
{
|
|
SH_INSN_FIPRS, "fiprs", "fipr.s", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* fld.d $rm, $disp10x8, $drf */
|
|
{
|
|
SH_INSN_FLDD, "fldd", "fld.d", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* fld.p $rm, $disp10x8, $fpf */
|
|
{
|
|
SH_INSN_FLDP, "fldp", "fld.p", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* fld.s $rm, $disp10x4, $frf */
|
|
{
|
|
SH_INSN_FLDS, "flds", "fld.s", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* fldx.d $rm, $rn, $drf */
|
|
{
|
|
SH_INSN_FLDXD, "fldxd", "fldx.d", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* fldx.p $rm, $rn, $fpf */
|
|
{
|
|
SH_INSN_FLDXP, "fldxp", "fldx.p", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* fldx.s $rm, $rn, $frf */
|
|
{
|
|
SH_INSN_FLDXS, "fldxs", "fldx.s", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* float.ld $frgh, $drf */
|
|
{
|
|
SH_INSN_FLOATLD, "floatld", "float.ld", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* float.ls $frgh, $frf */
|
|
{
|
|
SH_INSN_FLOATLS, "floatls", "float.ls", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* float.qd $drgh, $drf */
|
|
{
|
|
SH_INSN_FLOATQD, "floatqd", "float.qd", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* float.qs $drgh, $frf */
|
|
{
|
|
SH_INSN_FLOATQS, "floatqs", "float.qs", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* fmac.s $frg, $frh, $frf */
|
|
{
|
|
SH_INSN_FMACS, "fmacs", "fmac.s", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* fmov.d $drgh, $drf */
|
|
{
|
|
SH_INSN_FMOVD, "fmovd", "fmov.d", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* fmov.dq $drgh, $rd */
|
|
{
|
|
SH_INSN_FMOVDQ, "fmovdq", "fmov.dq", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* fmov.ls $rm, $frf */
|
|
{
|
|
SH_INSN_FMOVLS, "fmovls", "fmov.ls", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* fmov.qd $rm, $drf */
|
|
{
|
|
SH_INSN_FMOVQD, "fmovqd", "fmov.qd", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* fmov.s $frgh, $frf */
|
|
{
|
|
SH_INSN_FMOVS, "fmovs", "fmov.s", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* fmov.sl $frgh, $rd */
|
|
{
|
|
SH_INSN_FMOVSL, "fmovsl", "fmov.sl", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* fmul.d $drg, $drh, $drf */
|
|
{
|
|
SH_INSN_FMULD, "fmuld", "fmul.d", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* fmul.s $frg, $frh, $frf */
|
|
{
|
|
SH_INSN_FMULS, "fmuls", "fmul.s", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* fneg.d $drgh, $drf */
|
|
{
|
|
SH_INSN_FNEGD, "fnegd", "fneg.d", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* fneg.s $frgh, $frf */
|
|
{
|
|
SH_INSN_FNEGS, "fnegs", "fneg.s", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* fputscr $frgh */
|
|
{
|
|
SH_INSN_FPUTSCR, "fputscr", "fputscr", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* fsqrt.d $drgh, $drf */
|
|
{
|
|
SH_INSN_FSQRTD, "fsqrtd", "fsqrt.d", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* fsqrt.s $frgh, $frf */
|
|
{
|
|
SH_INSN_FSQRTS, "fsqrts", "fsqrt.s", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* fst.d $rm, $disp10x8, $drf */
|
|
{
|
|
SH_INSN_FSTD, "fstd", "fst.d", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* fst.p $rm, $disp10x8, $fpf */
|
|
{
|
|
SH_INSN_FSTP, "fstp", "fst.p", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* fst.s $rm, $disp10x4, $frf */
|
|
{
|
|
SH_INSN_FSTS, "fsts", "fst.s", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* fstx.d $rm, $rn, $drf */
|
|
{
|
|
SH_INSN_FSTXD, "fstxd", "fstx.d", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* fstx.p $rm, $rn, $fpf */
|
|
{
|
|
SH_INSN_FSTXP, "fstxp", "fstx.p", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* fstx.s $rm, $rn, $frf */
|
|
{
|
|
SH_INSN_FSTXS, "fstxs", "fstx.s", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* fsub.d $drg, $drh, $drf */
|
|
{
|
|
SH_INSN_FSUBD, "fsubd", "fsub.d", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* fsub.s $frg, $frh, $frf */
|
|
{
|
|
SH_INSN_FSUBS, "fsubs", "fsub.s", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* ftrc.dl $drgh, $frf */
|
|
{
|
|
SH_INSN_FTRCDL, "ftrcdl", "ftrc.dl", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* ftrc.sl $frgh, $frf */
|
|
{
|
|
SH_INSN_FTRCSL, "ftrcsl", "ftrc.sl", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* ftrc.dq $drgh, $drf */
|
|
{
|
|
SH_INSN_FTRCDQ, "ftrcdq", "ftrc.dq", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* ftrc.sq $frgh, $drf */
|
|
{
|
|
SH_INSN_FTRCSQ, "ftrcsq", "ftrc.sq", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* ftrv.s $mtrxg, $fvh, $fvf */
|
|
{
|
|
SH_INSN_FTRVS, "ftrvs", "ftrv.s", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* getcfg $rm, $disp6, $rd */
|
|
{
|
|
SH_INSN_GETCFG, "getcfg", "getcfg", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* getcon $crk, $rd */
|
|
{
|
|
SH_INSN_GETCON, "getcon", "getcon", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* gettr $trb, $rd */
|
|
{
|
|
SH_INSN_GETTR, "gettr", "gettr", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* icbi $rm, $disp6x32 */
|
|
{
|
|
SH_INSN_ICBI, "icbi", "icbi", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* ld.b $rm, $disp10, $rd */
|
|
{
|
|
SH_INSN_LDB, "ldb", "ld.b", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* ld.l $rm, $disp10x4, $rd */
|
|
{
|
|
SH_INSN_LDL, "ldl", "ld.l", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* ld.q $rm, $disp10x8, $rd */
|
|
{
|
|
SH_INSN_LDQ, "ldq", "ld.q", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* ld.ub $rm, $disp10, $rd */
|
|
{
|
|
SH_INSN_LDUB, "ldub", "ld.ub", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* ld.uw $rm, $disp10x2, $rd */
|
|
{
|
|
SH_INSN_LDUW, "lduw", "ld.uw", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* ld.w $rm, $disp10x2, $rd */
|
|
{
|
|
SH_INSN_LDW, "ldw", "ld.w", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* ldhi.l $rm, $disp6, $rd */
|
|
{
|
|
SH_INSN_LDHIL, "ldhil", "ldhi.l", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* ldhi.q $rm, $disp6, $rd */
|
|
{
|
|
SH_INSN_LDHIQ, "ldhiq", "ldhi.q", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* ldlo.l $rm, $disp6, $rd */
|
|
{
|
|
SH_INSN_LDLOL, "ldlol", "ldlo.l", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* ldlo.q $rm, $disp6, $rd */
|
|
{
|
|
SH_INSN_LDLOQ, "ldloq", "ldlo.q", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* ldx.b $rm, $rn, $rd */
|
|
{
|
|
SH_INSN_LDXB, "ldxb", "ldx.b", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* ldx.l $rm, $rn, $rd */
|
|
{
|
|
SH_INSN_LDXL, "ldxl", "ldx.l", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* ldx.q $rm, $rn, $rd */
|
|
{
|
|
SH_INSN_LDXQ, "ldxq", "ldx.q", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* ldx.ub $rm, $rn, $rd */
|
|
{
|
|
SH_INSN_LDXUB, "ldxub", "ldx.ub", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* ldx.uw $rm, $rn, $rd */
|
|
{
|
|
SH_INSN_LDXUW, "ldxuw", "ldx.uw", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* ldx.w $rm, $rn, $rd */
|
|
{
|
|
SH_INSN_LDXW, "ldxw", "ldx.w", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* mabs.l $rm, $rd */
|
|
{
|
|
SH_INSN_MABSL, "mabsl", "mabs.l", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* mabs.w $rm, $rd */
|
|
{
|
|
SH_INSN_MABSW, "mabsw", "mabs.w", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* madd.l $rm, $rn, $rd */
|
|
{
|
|
SH_INSN_MADDL, "maddl", "madd.l", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* madd.w $rm, $rn, $rd */
|
|
{
|
|
SH_INSN_MADDW, "maddw", "madd.w", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* madds.l $rm, $rn, $rd */
|
|
{
|
|
SH_INSN_MADDSL, "maddsl", "madds.l", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* madds.ub $rm, $rn, $rd */
|
|
{
|
|
SH_INSN_MADDSUB, "maddsub", "madds.ub", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* madds.w $rm, $rn, $rd */
|
|
{
|
|
SH_INSN_MADDSW, "maddsw", "madds.w", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* mcmpeq.b $rm, $rn, $rd */
|
|
{
|
|
SH_INSN_MCMPEQB, "mcmpeqb", "mcmpeq.b", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* mcmpeq.l $rm, $rn, $rd */
|
|
{
|
|
SH_INSN_MCMPEQL, "mcmpeql", "mcmpeq.l", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* mcmpeq.w $rm, $rn, $rd */
|
|
{
|
|
SH_INSN_MCMPEQW, "mcmpeqw", "mcmpeq.w", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* mcmpgt.l $rm, $rn, $rd */
|
|
{
|
|
SH_INSN_MCMPGTL, "mcmpgtl", "mcmpgt.l", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* mcmpgt.ub $rm, $rn, $rd */
|
|
{
|
|
SH_INSN_MCMPGTUB, "mcmpgtub", "mcmpgt.ub", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* mcmpgt.w $rm, $rn, $rd */
|
|
{
|
|
SH_INSN_MCMPGTW, "mcmpgtw", "mcmpgt.w", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* mcmv $rm, $rn, $rd */
|
|
{
|
|
SH_INSN_MCMV, "mcmv", "mcmv", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* mcnvs.lw $rm, $rn, $rd */
|
|
{
|
|
SH_INSN_MCNVSLW, "mcnvslw", "mcnvs.lw", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* mcnvs.wb $rm, $rn, $rd */
|
|
{
|
|
SH_INSN_MCNVSWB, "mcnvswb", "mcnvs.wb", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* mcnvs.wub $rm, $rn, $rd */
|
|
{
|
|
SH_INSN_MCNVSWUB, "mcnvswub", "mcnvs.wub", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* mextr1 $rm, $rn, $rd */
|
|
{
|
|
SH_INSN_MEXTR1, "mextr1", "mextr1", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* mextr2 $rm, $rn, $rd */
|
|
{
|
|
SH_INSN_MEXTR2, "mextr2", "mextr2", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* mextr3 $rm, $rn, $rd */
|
|
{
|
|
SH_INSN_MEXTR3, "mextr3", "mextr3", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* mextr4 $rm, $rn, $rd */
|
|
{
|
|
SH_INSN_MEXTR4, "mextr4", "mextr4", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* mextr5 $rm, $rn, $rd */
|
|
{
|
|
SH_INSN_MEXTR5, "mextr5", "mextr5", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* mextr6 $rm, $rn, $rd */
|
|
{
|
|
SH_INSN_MEXTR6, "mextr6", "mextr6", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* mextr7 $rm, $rn, $rd */
|
|
{
|
|
SH_INSN_MEXTR7, "mextr7", "mextr7", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* mmacfx.wl $rm, $rn, $rd */
|
|
{
|
|
SH_INSN_MMACFXWL, "mmacfxwl", "mmacfx.wl", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* mmacnfx.wl $rm, $rn, $rd */
|
|
{
|
|
SH_INSN_MMACNFX_WL, "mmacnfx.wl", "mmacnfx.wl", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* mmul.l $rm, $rn, $rd */
|
|
{
|
|
SH_INSN_MMULL, "mmull", "mmul.l", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* mmul.w $rm, $rn, $rd */
|
|
{
|
|
SH_INSN_MMULW, "mmulw", "mmul.w", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* mmulfx.l $rm, $rn, $rd */
|
|
{
|
|
SH_INSN_MMULFXL, "mmulfxl", "mmulfx.l", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* mmulfx.w $rm, $rn, $rd */
|
|
{
|
|
SH_INSN_MMULFXW, "mmulfxw", "mmulfx.w", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* mmulfxrp.w $rm, $rn, $rd */
|
|
{
|
|
SH_INSN_MMULFXRPW, "mmulfxrpw", "mmulfxrp.w", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* mmulhi.wl $rm, $rn, $rd */
|
|
{
|
|
SH_INSN_MMULHIWL, "mmulhiwl", "mmulhi.wl", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* mmullo.wl $rm, $rn, $rd */
|
|
{
|
|
SH_INSN_MMULLOWL, "mmullowl", "mmullo.wl", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* mmulsum.wq $rm, $rn, $rd */
|
|
{
|
|
SH_INSN_MMULSUMWQ, "mmulsumwq", "mmulsum.wq", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* movi $imm16, $rd */
|
|
{
|
|
SH_INSN_MOVI, "movi", "movi", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* mperm.w $rm, $rn, $rd */
|
|
{
|
|
SH_INSN_MPERMW, "mpermw", "mperm.w", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* msad.ubq $rm, $rn, $rd */
|
|
{
|
|
SH_INSN_MSADUBQ, "msadubq", "msad.ubq", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* mshalds.l $rm, $rn, $rd */
|
|
{
|
|
SH_INSN_MSHALDSL, "mshaldsl", "mshalds.l", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* mshalds.w $rm, $rn, $rd */
|
|
{
|
|
SH_INSN_MSHALDSW, "mshaldsw", "mshalds.w", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* mshard.l $rm, $rn, $rd */
|
|
{
|
|
SH_INSN_MSHARDL, "mshardl", "mshard.l", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* mshard.w $rm, $rn, $rd */
|
|
{
|
|
SH_INSN_MSHARDW, "mshardw", "mshard.w", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* mshards.q $rm, $rn, $rd */
|
|
{
|
|
SH_INSN_MSHARDSQ, "mshardsq", "mshards.q", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* mshfhi.b $rm, $rn, $rd */
|
|
{
|
|
SH_INSN_MSHFHIB, "mshfhib", "mshfhi.b", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* mshfhi.l $rm, $rn, $rd */
|
|
{
|
|
SH_INSN_MSHFHIL, "mshfhil", "mshfhi.l", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* mshfhi.w $rm, $rn, $rd */
|
|
{
|
|
SH_INSN_MSHFHIW, "mshfhiw", "mshfhi.w", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* mshflo.b $rm, $rn, $rd */
|
|
{
|
|
SH_INSN_MSHFLOB, "mshflob", "mshflo.b", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* mshflo.l $rm, $rn, $rd */
|
|
{
|
|
SH_INSN_MSHFLOL, "mshflol", "mshflo.l", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* mshflo.w $rm, $rn, $rd */
|
|
{
|
|
SH_INSN_MSHFLOW, "mshflow", "mshflo.w", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* mshlld.l $rm, $rn, $rd */
|
|
{
|
|
SH_INSN_MSHLLDL, "mshlldl", "mshlld.l", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* mshlld.w $rm, $rn, $rd */
|
|
{
|
|
SH_INSN_MSHLLDW, "mshlldw", "mshlld.w", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* mshlrd.l $rm, $rn, $rd */
|
|
{
|
|
SH_INSN_MSHLRDL, "mshlrdl", "mshlrd.l", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* mshlrd.w $rm, $rn, $rd */
|
|
{
|
|
SH_INSN_MSHLRDW, "mshlrdw", "mshlrd.w", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* msub.l $rm, $rn, $rd */
|
|
{
|
|
SH_INSN_MSUBL, "msubl", "msub.l", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* msub.w $rm, $rn, $rd */
|
|
{
|
|
SH_INSN_MSUBW, "msubw", "msub.w", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* msubs.l $rm, $rn, $rd */
|
|
{
|
|
SH_INSN_MSUBSL, "msubsl", "msubs.l", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* msubs.ub $rm, $rn, $rd */
|
|
{
|
|
SH_INSN_MSUBSUB, "msubsub", "msubs.ub", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* msubs.w $rm, $rn, $rd */
|
|
{
|
|
SH_INSN_MSUBSW, "msubsw", "msubs.w", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* muls.l $rm, $rn, $rd */
|
|
{
|
|
SH_INSN_MULSL, "mulsl", "muls.l", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* mulu.l $rm, $rn, $rd */
|
|
{
|
|
SH_INSN_MULUL, "mulul", "mulu.l", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* nop */
|
|
{
|
|
SH_INSN_NOP, "nop", "nop", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* nsb $rm, $rd */
|
|
{
|
|
SH_INSN_NSB, "nsb", "nsb", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* ocbi $rm, $disp6x32 */
|
|
{
|
|
SH_INSN_OCBI, "ocbi", "ocbi", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* ocbp $rm, $disp6x32 */
|
|
{
|
|
SH_INSN_OCBP, "ocbp", "ocbp", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* ocbwb $rm, $disp6x32 */
|
|
{
|
|
SH_INSN_OCBWB, "ocbwb", "ocbwb", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* or $rm, $rn, $rd */
|
|
{
|
|
SH_INSN_OR, "or", "or", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* ori $rm, $imm10, $rd */
|
|
{
|
|
SH_INSN_ORI, "ori", "ori", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* prefi $rm, $disp6x32 */
|
|
{
|
|
SH_INSN_PREFI, "prefi", "prefi", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* pta$likely $disp16, $tra */
|
|
{
|
|
SH_INSN_PTA, "pta", "pta", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* ptabs$likely $rn, $tra */
|
|
{
|
|
SH_INSN_PTABS, "ptabs", "ptabs", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* ptb$likely $disp16, $tra */
|
|
{
|
|
SH_INSN_PTB, "ptb", "ptb", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* ptrel$likely $rn, $tra */
|
|
{
|
|
SH_INSN_PTREL, "ptrel", "ptrel", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* putcfg $rm, $disp6, $rd */
|
|
{
|
|
SH_INSN_PUTCFG, "putcfg", "putcfg", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* putcon $rm, $crj */
|
|
{
|
|
SH_INSN_PUTCON, "putcon", "putcon", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* rte */
|
|
{
|
|
SH_INSN_RTE, "rte", "rte", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* shard $rm, $rn, $rd */
|
|
{
|
|
SH_INSN_SHARD, "shard", "shard", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* shard.l $rm, $rn, $rd */
|
|
{
|
|
SH_INSN_SHARDL, "shardl", "shard.l", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* shari $rm, $uimm6, $rd */
|
|
{
|
|
SH_INSN_SHARI, "shari", "shari", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* shari.l $rm, $uimm6, $rd */
|
|
{
|
|
SH_INSN_SHARIL, "sharil", "shari.l", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* shlld $rm, $rn, $rd */
|
|
{
|
|
SH_INSN_SHLLD, "shlld", "shlld", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* shlld.l $rm, $rn, $rd */
|
|
{
|
|
SH_INSN_SHLLDL, "shlldl", "shlld.l", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* shlli $rm, $uimm6, $rd */
|
|
{
|
|
SH_INSN_SHLLI, "shlli", "shlli", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* shlli.l $rm, $uimm6, $rd */
|
|
{
|
|
SH_INSN_SHLLIL, "shllil", "shlli.l", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* shlrd $rm, $rn, $rd */
|
|
{
|
|
SH_INSN_SHLRD, "shlrd", "shlrd", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* shlrd.l $rm, $rn, $rd */
|
|
{
|
|
SH_INSN_SHLRDL, "shlrdl", "shlrd.l", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* shlri $rm, $uimm6, $rd */
|
|
{
|
|
SH_INSN_SHLRI, "shlri", "shlri", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* shlri.l $rm, $uimm6, $rd */
|
|
{
|
|
SH_INSN_SHLRIL, "shlril", "shlri.l", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* shori $uimm16, $rd */
|
|
{
|
|
SH_INSN_SHORI, "shori", "shori", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* sleep */
|
|
{
|
|
SH_INSN_SLEEP, "sleep", "sleep", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* st.b $rm, $disp10, $rd */
|
|
{
|
|
SH_INSN_STB, "stb", "st.b", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* st.l $rm, $disp10x4, $rd */
|
|
{
|
|
SH_INSN_STL, "stl", "st.l", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* st.q $rm, $disp10x8, $rd */
|
|
{
|
|
SH_INSN_STQ, "stq", "st.q", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* st.w $rm, $disp10x2, $rd */
|
|
{
|
|
SH_INSN_STW, "stw", "st.w", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* sthi.l $rm, $disp6, $rd */
|
|
{
|
|
SH_INSN_STHIL, "sthil", "sthi.l", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* sthi.q $rm, $disp6, $rd */
|
|
{
|
|
SH_INSN_STHIQ, "sthiq", "sthi.q", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* stlo.l $rm, $disp6, $rd */
|
|
{
|
|
SH_INSN_STLOL, "stlol", "stlo.l", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* stlo.q $rm, $disp6, $rd */
|
|
{
|
|
SH_INSN_STLOQ, "stloq", "stlo.q", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* stx.b $rm, $rn, $rd */
|
|
{
|
|
SH_INSN_STXB, "stxb", "stx.b", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* stx.l $rm, $rn, $rd */
|
|
{
|
|
SH_INSN_STXL, "stxl", "stx.l", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* stx.q $rm, $rn, $rd */
|
|
{
|
|
SH_INSN_STXQ, "stxq", "stx.q", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* stx.w $rm, $rn, $rd */
|
|
{
|
|
SH_INSN_STXW, "stxw", "stx.w", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* sub $rm, $rn, $rd */
|
|
{
|
|
SH_INSN_SUB, "sub", "sub", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* sub.l $rm, $rn, $rd */
|
|
{
|
|
SH_INSN_SUBL, "subl", "sub.l", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* swap.q $rm, $rn, $rd */
|
|
{
|
|
SH_INSN_SWAPQ, "swapq", "swap.q", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* synci */
|
|
{
|
|
SH_INSN_SYNCI, "synci", "synci", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* synco */
|
|
{
|
|
SH_INSN_SYNCO, "synco", "synco", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* trapa $rm */
|
|
{
|
|
SH_INSN_TRAPA, "trapa", "trapa", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* xor $rm, $rn, $rd */
|
|
{
|
|
SH_INSN_XOR, "xor", "xor", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
/* xori $rm, $imm6, $rd */
|
|
{
|
|
SH_INSN_XORI, "xori", "xori", 32,
|
|
{ 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
|
|
},
|
|
};
|
|
|
|
#undef OP
|
|
#undef A
|
|
|
|
/* Initialize anything needed to be done once, before any cpu_open call. */
|
|
|
|
static void
|
|
init_tables ()
|
|
{
|
|
}
|
|
|
|
/* Subroutine of sh_cgen_cpu_open to look up a mach via its bfd name. */
|
|
|
|
static const CGEN_MACH *
|
|
lookup_mach_via_bfd_name (table, name)
|
|
const CGEN_MACH *table;
|
|
const char *name;
|
|
{
|
|
while (table->name)
|
|
{
|
|
if (strcmp (name, table->bfd_name) == 0)
|
|
return table;
|
|
++table;
|
|
}
|
|
abort ();
|
|
}
|
|
|
|
/* Subroutine of sh_cgen_cpu_open to build the hardware table. */
|
|
|
|
static void
|
|
build_hw_table (cd)
|
|
CGEN_CPU_TABLE *cd;
|
|
{
|
|
int i;
|
|
int machs = cd->machs;
|
|
const CGEN_HW_ENTRY *init = & sh_cgen_hw_table[0];
|
|
/* MAX_HW is only an upper bound on the number of selected entries.
|
|
However each entry is indexed by it's enum so there can be holes in
|
|
the table. */
|
|
const CGEN_HW_ENTRY **selected =
|
|
(const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
|
|
|
|
cd->hw_table.init_entries = init;
|
|
cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
|
|
memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
|
|
/* ??? For now we just use machs to determine which ones we want. */
|
|
for (i = 0; init[i].name != NULL; ++i)
|
|
if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
|
|
& machs)
|
|
selected[init[i].type] = &init[i];
|
|
cd->hw_table.entries = selected;
|
|
cd->hw_table.num_entries = MAX_HW;
|
|
}
|
|
|
|
/* Subroutine of sh_cgen_cpu_open to build the hardware table. */
|
|
|
|
static void
|
|
build_ifield_table (cd)
|
|
CGEN_CPU_TABLE *cd;
|
|
{
|
|
cd->ifld_table = & sh_cgen_ifld_table[0];
|
|
}
|
|
|
|
/* Subroutine of sh_cgen_cpu_open to build the hardware table. */
|
|
|
|
static void
|
|
build_operand_table (cd)
|
|
CGEN_CPU_TABLE *cd;
|
|
{
|
|
int i;
|
|
int machs = cd->machs;
|
|
const CGEN_OPERAND *init = & sh_cgen_operand_table[0];
|
|
/* MAX_OPERANDS is only an upper bound on the number of selected entries.
|
|
However each entry is indexed by it's enum so there can be holes in
|
|
the table. */
|
|
const CGEN_OPERAND **selected =
|
|
(const CGEN_OPERAND **) xmalloc (MAX_OPERANDS * sizeof (CGEN_OPERAND *));
|
|
|
|
cd->operand_table.init_entries = init;
|
|
cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
|
|
memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
|
|
/* ??? For now we just use mach to determine which ones we want. */
|
|
for (i = 0; init[i].name != NULL; ++i)
|
|
if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
|
|
& machs)
|
|
selected[init[i].type] = &init[i];
|
|
cd->operand_table.entries = selected;
|
|
cd->operand_table.num_entries = MAX_OPERANDS;
|
|
}
|
|
|
|
/* Subroutine of sh_cgen_cpu_open to build the hardware table.
|
|
??? This could leave out insns not supported by the specified mach/isa,
|
|
but that would cause errors like "foo only supported by bar" to become
|
|
"unknown insn", so for now we include all insns and require the app to
|
|
do the checking later.
|
|
??? On the other hand, parsing of such insns may require their hardware or
|
|
operand elements to be in the table [which they mightn't be]. */
|
|
|
|
static void
|
|
build_insn_table (cd)
|
|
CGEN_CPU_TABLE *cd;
|
|
{
|
|
int i;
|
|
const CGEN_IBASE *ib = & sh_cgen_insn_table[0];
|
|
CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
|
|
|
|
memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
|
|
for (i = 0; i < MAX_INSNS; ++i)
|
|
insns[i].base = &ib[i];
|
|
cd->insn_table.init_entries = insns;
|
|
cd->insn_table.entry_size = sizeof (CGEN_IBASE);
|
|
cd->insn_table.num_init_entries = MAX_INSNS;
|
|
}
|
|
|
|
/* Subroutine of sh_cgen_cpu_open to rebuild the tables. */
|
|
|
|
static void
|
|
sh_cgen_rebuild_tables (cd)
|
|
CGEN_CPU_TABLE *cd;
|
|
{
|
|
int i,n_isas;
|
|
unsigned int isas = cd->isas;
|
|
#if 0
|
|
unsigned int machs = cd->machs;
|
|
#endif
|
|
|
|
cd->int_insn_p = CGEN_INT_INSN_P;
|
|
|
|
/* Data derived from the isa spec. */
|
|
#define UNSET (CGEN_SIZE_UNKNOWN + 1)
|
|
cd->default_insn_bitsize = UNSET;
|
|
cd->base_insn_bitsize = UNSET;
|
|
cd->min_insn_bitsize = 65535; /* some ridiculously big number */
|
|
cd->max_insn_bitsize = 0;
|
|
for (i = 0; i < MAX_ISAS; ++i)
|
|
if (((1 << i) & isas) != 0)
|
|
{
|
|
const CGEN_ISA *isa = & sh_cgen_isa_table[i];
|
|
|
|
/* Default insn sizes of all selected isas must be equal or we set
|
|
the result to 0, meaning "unknown". */
|
|
if (cd->default_insn_bitsize == UNSET)
|
|
cd->default_insn_bitsize = isa->default_insn_bitsize;
|
|
else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
|
|
; /* this is ok */
|
|
else
|
|
cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
|
|
|
|
/* Base insn sizes of all selected isas must be equal or we set
|
|
the result to 0, meaning "unknown". */
|
|
if (cd->base_insn_bitsize == UNSET)
|
|
cd->base_insn_bitsize = isa->base_insn_bitsize;
|
|
else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
|
|
; /* this is ok */
|
|
else
|
|
cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
|
|
|
|
/* Set min,max insn sizes. */
|
|
if (isa->min_insn_bitsize < cd->min_insn_bitsize)
|
|
cd->min_insn_bitsize = isa->min_insn_bitsize;
|
|
if (isa->max_insn_bitsize > cd->max_insn_bitsize)
|
|
cd->max_insn_bitsize = isa->max_insn_bitsize;
|
|
|
|
++n_isas;
|
|
}
|
|
|
|
#if 0 /* Does nothing?? */
|
|
/* Data derived from the mach spec. */
|
|
for (i = 0; i < MAX_MACHS; ++i)
|
|
if (((1 << i) & machs) != 0)
|
|
{
|
|
const CGEN_MACH *mach = & sh_cgen_mach_table[i];
|
|
|
|
++n_machs;
|
|
}
|
|
#endif
|
|
|
|
/* Determine which hw elements are used by MACH. */
|
|
build_hw_table (cd);
|
|
|
|
/* Build the ifield table. */
|
|
build_ifield_table (cd);
|
|
|
|
/* Determine which operands are used by MACH/ISA. */
|
|
build_operand_table (cd);
|
|
|
|
/* Build the instruction table. */
|
|
build_insn_table (cd);
|
|
}
|
|
|
|
/* Initialize a cpu table and return a descriptor.
|
|
It's much like opening a file, and must be the first function called.
|
|
The arguments are a set of (type/value) pairs, terminated with
|
|
CGEN_CPU_OPEN_END.
|
|
|
|
Currently supported values:
|
|
CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr
|
|
CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr
|
|
CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
|
|
CGEN_CPU_OPEN_ENDIAN: specify endian choice
|
|
CGEN_CPU_OPEN_END: terminates arguments
|
|
|
|
??? Simultaneous multiple isas might not make sense, but it's not (yet)
|
|
precluded.
|
|
|
|
??? We only support ISO C stdargs here, not K&R.
|
|
Laziness, plus experiment to see if anything requires K&R - eventually
|
|
K&R will no longer be supported - e.g. GDB is currently trying this. */
|
|
|
|
CGEN_CPU_DESC
|
|
sh_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
|
|
{
|
|
CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
|
|
static int init_p;
|
|
unsigned int isas = 0; /* 0 = "unspecified" */
|
|
unsigned int machs = 0; /* 0 = "unspecified" */
|
|
enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
|
|
va_list ap;
|
|
|
|
if (! init_p)
|
|
{
|
|
init_tables ();
|
|
init_p = 1;
|
|
}
|
|
|
|
memset (cd, 0, sizeof (*cd));
|
|
|
|
va_start (ap, arg_type);
|
|
while (arg_type != CGEN_CPU_OPEN_END)
|
|
{
|
|
switch (arg_type)
|
|
{
|
|
case CGEN_CPU_OPEN_ISAS :
|
|
isas = va_arg (ap, unsigned int);
|
|
break;
|
|
case CGEN_CPU_OPEN_MACHS :
|
|
machs = va_arg (ap, unsigned int);
|
|
break;
|
|
case CGEN_CPU_OPEN_BFDMACH :
|
|
{
|
|
const char *name = va_arg (ap, const char *);
|
|
const CGEN_MACH *mach =
|
|
lookup_mach_via_bfd_name (sh_cgen_mach_table, name);
|
|
|
|
machs |= mach->num << 1;
|
|
break;
|
|
}
|
|
case CGEN_CPU_OPEN_ENDIAN :
|
|
endian = va_arg (ap, enum cgen_endian);
|
|
break;
|
|
default :
|
|
fprintf (stderr, "sh_cgen_cpu_open: unsupported argument `%d'\n",
|
|
arg_type);
|
|
abort (); /* ??? return NULL? */
|
|
}
|
|
arg_type = va_arg (ap, enum cgen_cpu_open_arg);
|
|
}
|
|
va_end (ap);
|
|
|
|
/* mach unspecified means "all" */
|
|
if (machs == 0)
|
|
machs = (1 << MAX_MACHS) - 1;
|
|
/* base mach is always selected */
|
|
machs |= 1;
|
|
/* isa unspecified means "all" */
|
|
if (isas == 0)
|
|
isas = (1 << MAX_ISAS) - 1;
|
|
if (endian == CGEN_ENDIAN_UNKNOWN)
|
|
{
|
|
/* ??? If target has only one, could have a default. */
|
|
fprintf (stderr, "sh_cgen_cpu_open: no endianness specified\n");
|
|
abort ();
|
|
}
|
|
|
|
cd->isas = isas;
|
|
cd->machs = machs;
|
|
cd->endian = endian;
|
|
/* FIXME: for the sparc case we can determine insn-endianness statically.
|
|
The worry here is where both data and insn endian can be independently
|
|
chosen, in which case this function will need another argument.
|
|
Actually, will want to allow for more arguments in the future anyway. */
|
|
cd->insn_endian = endian;
|
|
|
|
/* Table (re)builder. */
|
|
cd->rebuild_tables = sh_cgen_rebuild_tables;
|
|
sh_cgen_rebuild_tables (cd);
|
|
|
|
/* Default to not allowing signed overflow. */
|
|
cd->signed_overflow_ok_p = 0;
|
|
|
|
return (CGEN_CPU_DESC) cd;
|
|
}
|
|
|
|
/* Cover fn to sh_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
|
|
MACH_NAME is the bfd name of the mach. */
|
|
|
|
CGEN_CPU_DESC
|
|
sh_cgen_cpu_open_1 (mach_name, endian)
|
|
const char *mach_name;
|
|
enum cgen_endian endian;
|
|
{
|
|
return sh_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
|
|
CGEN_CPU_OPEN_ENDIAN, endian,
|
|
CGEN_CPU_OPEN_END);
|
|
}
|
|
|
|
/* Close a cpu table.
|
|
??? This can live in a machine independent file, but there's currently
|
|
no place to put this file (there's no libcgen). libopcodes is the wrong
|
|
place as some simulator ports use this but they don't use libopcodes. */
|
|
|
|
void
|
|
sh_cgen_cpu_close (cd)
|
|
CGEN_CPU_DESC cd;
|
|
{
|
|
if (cd->insn_table.init_entries)
|
|
free ((CGEN_INSN *) cd->insn_table.init_entries);
|
|
if (cd->hw_table.entries)
|
|
free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
|
|
free (cd);
|
|
}
|
|
|