darlinghq/darling-gdb
1
0
Fork 0
mirror of https://github.com/darlinghq/darling-gdb.git synced 2024-11-27 14:00:30 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity
0cbfa4ee32
darling-gdb/cpu/m32c.cpu
DJ Delorie 43aa3bb1d4 * m32c.cpu (Bit3-S): New. 
(btst:s): New.
* m32c.opc (parse_bit3_S): New.
2006-03-14 04:20:53 +00:00

10431 lines
366 KiB
Scheme
Raw Blame History

This file contains invisible Unicode characters

This file contains invisible Unicode characters that are indistinguishable to humans but may be processed differently by a computer. If you think that this is intentional, you can safely ignore this warning. Use the Escape button to reveal them.

; Renesas M32C CPU description. -*- Scheme -*-
;
; Copyright 2005, 2006 Free Software Foundation, Inc.
;
; Contributed by Red Hat Inc; developed under contract from Renesas.
;
; This file is part of the GNU Binutils.
;
; This program is free software; you can redistribute it and/or modify
; it under the terms of the GNU General Public License as published by
; the Free Software Foundation; either version 2 of the License, or
; (at your option) any later version.
;
; This program is distributed in the hope that it will be useful,
; but WITHOUT ANY WARRANTY; without even the implied warranty of
; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
; GNU General Public License for more details.
;
; You should have received a copy of the GNU General Public License
; along with this program; if not, write to the Free Software
; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
(include "simplify.inc")
(define-arch
(name m32c)
(comment "Renesas M32C")
(default-alignment forced)
(insn-lsb0? #f)
(machs m16c m32c)
(isas m16c m32c)
)
(define-isa
(name m16c)
(default-insn-bitsize 32)
; Number of bytes of insn we can initially fetch.
(base-insn-bitsize 32)
; Used in computing bit numbers.
(default-insn-word-bitsize 32)
(decode-assist (0 1 2 3 4 5 6 7)) ; Initial bitnumbers to decode insns by.
; fetches 1 insn at a time.
(liw-insns 1)
; executes 1 insn at a time.
(parallel-insns 1)
)
(define-isa
(name m32c)
(default-insn-bitsize 32)
; Number of bytes of insn we can initially fetch.
(base-insn-bitsize 32)
; Used in computing bit numbers.
(default-insn-word-bitsize 32)
(decode-assist (0 1 2 3 4 5 6 7)) ; Initial bitnumbers to decode insns by.
; fetches 1 insn at a time.
(liw-insns 1)
; executes 1 insn at a time.
(parallel-insns 1)
)
(define-cpu
; cpu names must be distinct from the architecture name and machine names.
; The "b" suffix stands for "base" and is the convention.
; The "f" suffix stands for "family" and is the convention.
(name m16cbf)
(comment "Renesas M16C base family")
(insn-endian big)
(data-endian little)
(word-bitsize 16)
)
(define-cpu
; cpu names must be distinct from the architecture name and machine names.
; The "b" suffix stands for "base" and is the convention.
; The "f" suffix stands for "family" and is the convention.
(name m32cbf)
(comment "Renesas M32C base family")
(insn-endian big)
(data-endian little)
(word-bitsize 16)
)
(define-mach
(name m16c)
(comment "Generic M16C cpu")
(cpu m32cbf)
)
(define-mach
(name m32c)
(comment "Generic M32C cpu")
(cpu m32cbf)
)
; Model descriptions.
(define-model
(name m16c)
(comment "m16c") (attrs)
(mach m16c)
; `state' is a list of variables for recording model state
; (state)
(unit u-exec "Execution Unit" ()
1 1 ; issue done
() ; state
() ; inputs
() ; outputs
() ; profile action (default)
)
)
(define-model
(name m32c)
(comment "m32c") (attrs)
(mach m32c)
; `state' is a list of variables for recording model state
; (state)
(unit u-exec "Execution Unit" ()
1 1 ; issue done
() ; state
() ; inputs
() ; outputs
() ; profile action (default)
)
)
(define-attr
(type enum)
(name RL_TYPE)
(values NONE JUMP 1ADDR 2ADDR)
(default NONE)
)
; Macros to simplify MACH attribute specification.
(define-pmacro all-isas () (ISA m16c,m32c))
(define-pmacro m16c-isa () (ISA m16c))
(define-pmacro m32c-isa () (ISA m32c))
(define-pmacro MACH16 (MACH m16c))
(define-pmacro MACH32 (MACH m32c))
(define-pmacro (machine size)
(MACH (.sym m size c)) (ISA (.sym m size c)))
(define-pmacro RL_JUMP (RL_TYPE JUMP))
(define-pmacro RL_1ADDR (RL_TYPE 1ADDR))
(define-pmacro RL_2ADDR (RL_TYPE 2ADDR))
;=============================================================
; Fields
;-------------------------------------------------------------
; Main opcodes
;
(dnf f-0-1 "opcode" (all-isas) 0 1)
(dnf f-0-2 "opcode" (all-isas) 0 2)
(dnf f-0-3 "opcode" (all-isas) 0 3)
(dnf f-0-4 "opcode" (all-isas) 0 4)
(dnf f-1-3 "opcode" (all-isas) 1 3)
(dnf f-2-2 "opcode" (all-isas) 2 2)
(dnf f-3-4 "opcode" (all-isas) 3 4)
(dnf f-3-1 "opcode" (all-isas) 3 1)
(dnf f-4-1 "opcode" (all-isas) 4 1)
(dnf f-4-3 "opcode" (all-isas) 4 3)
(dnf f-4-4 "opcode" (all-isas) 4 4)
(dnf f-4-6 "opcode" (all-isas) 4 6)
(dnf f-5-1 "opcode" (all-isas) 5 1)
(dnf f-5-3 "opcode" (all-isas) 5 3)
(dnf f-6-2 "opcode" (all-isas) 6 2)
(dnf f-7-1 "opcode" (all-isas) 7 1)
(dnf f-8-1 "opcode" (all-isas) 8 1)
(dnf f-8-2 "opcode" (all-isas) 8 2)
(dnf f-8-3 "opcode" (all-isas) 8 3)
(dnf f-8-4 "opcode" (all-isas) 8 4)
(dnf f-8-8 "opcode" (all-isas) 8 8)
(dnf f-9-3 "opcode" (all-isas) 9 3)
(dnf f-9-1 "opcode" (all-isas) 9 1)
(dnf f-10-1 "opcode" (all-isas) 10 1)
(dnf f-10-2 "opcode" (all-isas) 10 2)
(dnf f-10-3 "opcode" (all-isas) 10 3)
(dnf f-11-1 "opcode" (all-isas) 11 1)
(dnf f-12-1 "opcode" (all-isas) 12 1)
(dnf f-12-2 "opcode" (all-isas) 12 2)
(dnf f-12-3 "opcode" (all-isas) 12 3)
(dnf f-12-4 "opcode" (all-isas) 12 4)
(dnf f-12-6 "opcode" (all-isas) 12 6)
(dnf f-13-3 "opcode" (all-isas) 13 3)
(dnf f-14-1 "opcode" (all-isas) 14 1)
(dnf f-14-2 "opcode" (all-isas) 14 2)
(dnf f-15-1 "opcode" (all-isas) 15 1)
(dnf f-16-1 "opcode" (all-isas) 16 1)
(dnf f-16-2 "opcode" (all-isas) 16 2)
(dnf f-16-4 "opcode" (all-isas) 16 4)
(dnf f-16-8 "opcode" (all-isas) 16 8)
(dnf f-18-1 "opcode" (all-isas) 18 1)
(dnf f-18-2 "opcode" (all-isas) 18 2)
(dnf f-18-3 "opcode" (all-isas) 18 3)
(dnf f-20-1 "opcode" (all-isas) 20 1)
(dnf f-20-3 "opcode" (all-isas) 20 3)
(dnf f-20-2 "opcode" (all-isas) 20 2)
(dnf f-20-4 "opcode" (all-isas) 20 4)
(dnf f-21-3 "opcode" (all-isas) 21 3)
(dnf f-24-2 "opcode" (all-isas) 24 2)
(dnf f-24-8 "opcode" (all-isas) 24 8)
(dnf f-32-16 "opcode" (all-isas) 32 16)
;-------------------------------------------------------------
; Registers
;-------------------------------------------------------------
(dnf f-src16-rn "source Rn for m16c" (MACH16 m16c-isa) 10 2)
(dnf f-src16-an "source An for m16c" (MACH16 m16c-isa) 11 1)
(dnf f-src32-an-unprefixed "destination An for m32c" (MACH32 m32c-isa) 11 1)
(dnf f-src32-an-prefixed "destination An for m32c" (MACH32 m32c-isa) 19 1)
; QI mode gr encoding for m32c is different than for m16c. The hardware
; is indexed using the m16c encoding, so perform the transformation here.
; register m16c m32c
; ----------------------
; r0l 00'b 10'b
; r0h 01'b 00'b
; r1l 10'b 11'b
; r1h 11'b 01'b
(df f-src32-rn-unprefixed-QI "source Rn QI for m32c" (MACH32 m32c-isa) 10 2 UINT
((value pc) (or USI (and (sll (inv value) 1) 2) (and (srl value 1) 1))) ; insert
((value pc) (or USI (and (inv (srl value 1)) 1) (and (sll value 1) 2))) ; extract
)
; QI mode gr encoding for m32c is different than for m16c. The hardware
; is indexed using the m16c encoding, so perform the transformation here.
; register m16c m32c
; ----------------------
; r0l 00'b 10'b
; r0h 01'b 00'b
; r1l 10'b 11'b
; r1h 11'b 01'b
(df f-src32-rn-prefixed-QI "source Rn QI for m32c" (MACH32 m32c-isa) 18 2 UINT
((value pc) (or USI (and (sll (inv value) 1) 2) (and (srl value 1) 1))) ; insert
((value pc) (or USI (and (inv (srl value 1)) 1) (and (sll value 1) 2))) ; extract
)
; HI mode gr encoding for m32c is different than for m16c. The hardware
; is indexed using the m16c encoding, so perform the transformation here.
; register m16c m32c
; ----------------------
; r0 00'b 10'b
; r1 01'b 11'b
; r2 10'b 00'b
; r3 11'b 01'b
(df f-src32-rn-unprefixed-HI "source Rn HI for m32c" (MACH32 m32c-isa) 10 2 UINT
((value pc) (mod USI (add value 2) 4)) ; insert
((value pc) (mod USI (add value 2) 4)) ; extract
)
; HI mode gr encoding for m32c is different than for m16c. The hardware
; is indexed using the m16c encoding, so perform the transformation here.
; register m16c m32c
; ----------------------
; r0 00'b 10'b
; r1 01'b 11'b
; r2 10'b 00'b
; r3 11'b 01'b
(df f-src32-rn-prefixed-HI "source Rn HI for m32c" (MACH32 m32c-isa) 18 2 UINT
((value pc) (mod USI (add value 2) 4)) ; insert
((value pc) (mod USI (add value 2) 4)) ; extract
)
; SI mode gr encoding for m32c is as follows:
; register encoding index
; -------------------------
; r2r0 10'b 0
; r3r1 11'b 1
(df f-src32-rn-unprefixed-SI "source Rn SI for m32c" (MACH32 m32c-isa) 10 2 UINT
((value pc) (add USI value 2)) ; insert
((value pc) (sub USI value 2)) ; extract
)
(df f-src32-rn-prefixed-SI "source Rn SI for m32c" (MACH32 m32c-isa) 18 2 UINT
((value pc) (add USI value 2)) ; insert
((value pc) (sub USI value 2)) ; extract
)
(dnf f-dst32-rn-ext-unprefixed "destination Rn for m32c" (MACH32 m32c-isa) 9 1)
(dnf f-dst16-rn "destination Rn for m16c" (MACH16 m16c-isa) 14 2)
(dnf f-dst16-rn-ext "destination Rn for m16c" (MACH16 m16c-isa) 14 1)
(dnf f-dst16-rn-QI-s "destination Rn for m16c" (MACH16 m16c-isa) 5 1)
(dnf f-dst16-an "destination An for m16c" (MACH16 m16c-isa) 15 1)
(dnf f-dst16-an-s "destination An for m16c" (MACH16 m16c-isa) 4 1)
(dnf f-dst32-an-unprefixed "destination An for m32c" (MACH32 m32c-isa) 9 1)
(dnf f-dst32-an-prefixed "destination An for m32c" (MACH32 m32c-isa) 17 1)
; QI mode gr encoding for m32c is different than for m16c. The hardware
; is indexed using the m16c encoding, so perform the transformation here.
; register m16c m32c
; ----------------------
; r0l 00'b 10'b
; r0h 01'b 00'b
; r1l 10'b 11'b
; r1h 11'b 01'b
(df f-dst32-rn-unprefixed-QI "destination Rn QI for m32c" (MACH32 m32c-isa) 8 2 UINT
((value pc) (or USI (and (sll (inv value) 1) 2) (and (srl value 1) 1))) ; insert
((value pc) (or USI (and (inv (srl value 1)) 1) (and (sll value 1) 2))) ; extract
)
(df f-dst32-rn-prefixed-QI "destination Rn QI for m32c" (MACH32 m32c-isa) 16 2 UINT
((value pc) (or USI (and (sll (inv value) 1) 2) (and (srl value 1) 1))) ; insert
((value pc) (or USI (and (inv (srl value 1)) 1) (and (sll value 1) 2))) ; extract
)
; HI mode gr encoding for m32c is different than for m16c. The hardware
; is indexed using the m16c encoding, so perform the transformation here.
; register m16c m32c
; ----------------------
; r0 00'b 10'b
; r1 01'b 11'b
; r2 10'b 00'b
; r3 11'b 01'b
(df f-dst32-rn-unprefixed-HI "destination Rn HI for m32c" (MACH32 m32c-isa) 8 2 UINT
((value pc) (mod USI (add value 2) 4)) ; insert
((value pc) (mod USI (add value 2) 4)) ; extract
)
(df f-dst32-rn-prefixed-HI "destination Rn HI for m32c" (MACH32 m32c-isa) 16 2 UINT
((value pc) (mod USI (add value 2) 4)) ; insert
((value pc) (mod USI (add value 2) 4)) ; extract
)
; SI mode gr encoding for m32c is as follows:
; register encoding index
; -------------------------
; r2r0 10'b 0
; r3r1 11'b 1
(df f-dst32-rn-unprefixed-SI "destination Rn SI for m32c" (MACH32 m32c-isa) 8 2 UINT
((value pc) (add USI value 2)) ; insert
((value pc) (sub USI value 2)) ; extract
)
(df f-dst32-rn-prefixed-SI "destination Rn SI for m32c" (MACH32 m32c-isa) 16 2 UINT
((value pc) (add USI value 2)) ; insert
((value pc) (sub USI value 2)) ; extract
)
(dnf f-dst16-1-S "destination R0[hl] for m16c" (MACH16 m16c-isa) 5 1)
;-------------------------------------------------------------
; Immediates embedded in the base insn
;-------------------------------------------------------------
(df f-imm-8-s4 "4 bit signed" (all-isas) 8 4 INT #f #f)
(df f-imm-12-s4 "4 bit signed" (all-isas) 12 4 INT #f #f)
(df f-imm-13-u3 "3 bit unsigned" (all-isas) 13 3 UINT #f #f)
(df f-imm-20-s4 "4 bit signed" (all-isas) 20 4 INT #f #f)
(df f-imm1-S "1 bit immediate for short format binary insns" (MACH32 m32c-isa) 2 1 UINT
((value pc) (sub USI value 1)) ; insert
((value pc) (add USI value 1)) ; extract
)
(dnmf f-imm3-S "3 bit unsigned for short format insns" (all-isas) UINT
(f-2-2 f-7-1)
(sequence () ; insert
(set (ifield f-7-1) (and (sub (ifield f-imm3-S) 1) 1))
(set (ifield f-2-2) (and (srl (sub (ifield f-imm3-S) 1) 1) #x3))
)
(sequence () ; extract
(set (ifield f-imm3-S) (add (or (sll (ifield f-2-2) 1)
(ifield f-7-1))
1))
)
)
;-------------------------------------------------------------
; Immediates and displacements beyond the base insn
;-------------------------------------------------------------
(df f-dsp-8-u6 "6 bit unsigned" (all-isas) 8 6 UINT #f #f)
(df f-dsp-8-u8 "8 bit unsigned" (all-isas) 8 8 UINT #f #f)
(df f-dsp-8-s8 "8 bit signed" (all-isas) 8 8 INT #f #f)
(df f-dsp-10-u6 "6 bit unsigned" (all-isas) 10 6 UINT #f #f)
(df f-dsp-16-u8 "8 bit unsigned" (all-isas) 16 8 UINT #f #f)
(df f-dsp-16-s8 "8 bit signed" (all-isas) 16 8 INT #f #f)
(df f-dsp-24-u8 "8 bit unsigned" (all-isas) 24 8 UINT #f #f)
(df f-dsp-24-s8 "8 bit signed" (all-isas) 24 8 INT #f #f)
(df f-dsp-32-u8 "8 bit unsigned" (all-isas) 32 8 UINT #f #f)
(df f-dsp-32-s8 "8 bit signed" (all-isas) 32 8 INT #f #f)
(df f-dsp-40-u8 "8 bit unsigned" (all-isas) 40 8 UINT #f #f)
(df f-dsp-40-s8 "8 bit signed" (all-isas) 40 8 INT #f #f)
(df f-dsp-48-u8 "8 bit unsigned" (all-isas) 48 8 UINT #f #f)
(df f-dsp-48-s8 "8 bit signed" (all-isas) 48 8 INT #f #f)
(df f-dsp-56-u8 "8 bit unsigned" (all-isas) 56 8 UINT #f #f)
(df f-dsp-56-s8 "8 bit signed" (all-isas) 56 8 INT #f #f)
(df f-dsp-64-u8 "8 bit unsigned" (all-isas) 64 8 UINT #f #f)
(df f-dsp-64-s8 "8 bit signed" (all-isas) 64 8 INT #f #f)
; Insn opcode endianness is big, but the immediate fields are stored
; in little endian. Handle this here at the field level for all immediate
; fields longer that 1 byte.
;
; CGEN can't handle a field which spans a 32 bit word boundary, so
; handle those as multi ifields.
;
; Take care in expressions using 'srl' or 'sll' as part of some larger
; expression meant to yield sign-extended values. CGEN translates
; uses of those operators into C expressions whose type is 'unsigned
; int', which tends to make the whole expression 'unsigned int'.
; Expressions like (set (ifield foo) X), however, just take X and
; store it in some member of 'struct cgen_fields', all of whose
; members are 'long'. On machines where 'long' is larger than
; 'unsigned int', assigning a "sign-extended" unsigned int to a long
; just produces a very large positive value. insert_normal will
; range-check the field's value and produce odd error messages like
; this:
;
; Error: operand out of range (4160684031 not between -2147483648 and 2147483647) `add.l #-265,-270[fb]'
;
; Annoyingly, the code will work fine on machines where 'long' and
; 'unsigned int' are the same size: the assignment will produce a
; negative number.
;
; Just tell yourself over and over: overflow detection is expensive,
; and you're glad C doesn't do it, because it never happens in real
; life.
(df f-dsp-8-u16 "16 bit unsigned" (all-isas) 8 16 UINT
((value pc) (or UHI
(and (srl value 8) #x00ff)
(and (sll value 8) #xff00))) ; insert
((value pc) (or UHI
(and UHI (srl UHI value 8) #x00ff)
(and UHI (sll UHI value 8) #xff00))) ; extract
)
(df f-dsp-8-s16 "8 bit signed" (all-isas) 8 16 INT
((value pc) (ext INT
(trunc HI
(or (and (srl value 8) #x00ff)
(and (sll value 8) #xff00))))) ; insert
((value pc) (ext INT
(trunc HI
(or (and (srl value 8) #x00ff)
(and (sll value 8) #xff00))))) ; extract
)
(df f-dsp-16-u16 "16 bit unsigned" (all-isas) 16 16 UINT
((value pc) (or UHI
(and (srl value 8) #x00ff)
(and (sll value 8) #xff00))) ; insert
((value pc) (or UHI
(and UHI (srl UHI value 8) #x00ff)
(and UHI (sll UHI value 8) #xff00))) ; extract
)
(df f-dsp-16-s16 "16 bit signed" (all-isas) 16 16 INT
((value pc) (ext INT
(trunc HI
(or (and (srl value 8) #x00ff)
(and (sll value 8) #xff00))))) ; insert
((value pc) (ext INT
(trunc HI
(or (and (srl value 8) #x00ff)
(and (sll value 8) #xff00))))) ; extract
)
(dnmf f-dsp-24-u16 "16 bit unsigned" (all-isas) UINT
(f-dsp-24-u8 f-dsp-32-u8)
(sequence () ; insert
(set (ifield f-dsp-24-u8) (and (ifield f-dsp-24-u16) #xff))
(set (ifield f-dsp-32-u8) (and (srl (ifield f-dsp-24-u16) 8) #xff))
)
(sequence () ; extract
(set (ifield f-dsp-24-u16) (or (sll (ifield f-dsp-32-u8) 8)
(ifield f-dsp-24-u8)))
)
)
(dnmf f-dsp-24-s16 "16 bit signed" (all-isas) INT
(f-dsp-24-u8 f-dsp-32-u8)
(sequence () ; insert
(set (ifield f-dsp-24-u8)
(and (ifield f-dsp-24-s16) #xff))
(set (ifield f-dsp-32-u8)
(and (srl (ifield f-dsp-24-s16) 8) #xff))
)
(sequence () ; extract
(set (ifield f-dsp-24-s16)
(ext INT
(trunc HI (or (sll (ifield f-dsp-32-u8) 8)
(ifield f-dsp-24-u8)))))
)
)
(df f-dsp-32-u16 "16 bit unsigned" (all-isas) 32 16 UINT
((value pc) (or UHI
(and (srl value 8) #x00ff)
(and (sll value 8) #xff00))) ; insert
((value pc) (or UHI
(and UHI (srl UHI value 8) #x00ff)
(and UHI (sll UHI value 8) #xff00))) ; extract
)
(df f-dsp-32-s16 "16 bit signed" (all-isas) 32 16 INT
((value pc) (ext INT
(trunc HI
(or (and (srl value 8) #x00ff)
(and (sll value 8) #xff00))))) ; insert
((value pc) (ext INT
(trunc HI
(or (and (srl value 8) #x00ff)
(and (sll value 8) #xff00))))) ; extract
)
(df f-dsp-40-u16 "16 bit unsigned" (all-isas) 40 16 UINT
((value pc) (or UHI
(and (srl value 8) #x00ff)
(and (sll value 8) #xff00))) ; insert
((value pc) (or UHI
(and UHI (srl UHI value 8) #x00ff)
(and UHI (sll UHI value 8) #xff00))) ; extract
)
(df f-dsp-40-s16 "16 bit signed" (all-isas) 40 16 INT
((value pc) (ext INT
(trunc HI
(or (and (srl value 8) #x00ff)
(and (sll value 8) #xff00))))) ; insert
((value pc) (ext INT
(trunc HI
(or (and (srl value 8) #x00ff)
(and (sll value 8) #xff00))))) ; extract
)
(df f-dsp-48-u16 "16 bit unsigned" (all-isas) 48 16 UINT
((value pc) (or UHI
(and (srl value 8) #x00ff)
(and (sll value 8) #xff00))) ; insert
((value pc) (or UHI
(and UHI (srl UHI value 8) #x00ff)
(and UHI (sll UHI value 8) #xff00))) ; extract
)
(df f-dsp-48-s16 "16 bit signed" (all-isas) 48 16 INT
((value pc) (ext INT
(trunc HI
(or (and (srl value 8) #x00ff)
(and (sll value 8) #xff00))))) ; insert
((value pc) (ext INT
(trunc HI
(or (and (srl value 8) #x00ff)
(and (sll value 8) #xff00))))) ; extract
)
(df f-dsp-64-u16 "16 bit unsigned" (all-isas) 64 16 UINT
((value pc) (or UHI
(and (srl value 8) #x00ff)
(and (sll value 8) #xff00))) ; insert
((value pc) (or UHI
(and UHI (srl UHI value 8) #x00ff)
(and UHI (sll UHI value 8) #xff00))) ; extract
)
(df f-dsp-8-s24 "24 bit signed" (all-isas) 8 24 INT
((value pc) (or SI
(or (srl value 16) (and value #xff00))
(sll (ext INT (trunc QI (and value #xff))) 16)))
((value pc) (or SI
(or (srl value 16) (and value #xff00))
(sll (ext INT (trunc QI (and value #xff))) 16)))
)
(df f-dsp-8-u24 "24 bit unsigned" (all-isas) 8 24 UINT
((value pc) (or SI
(or (srl value 16) (and value #xff00))
(sll (and value #xff) 16)))
((value pc) (or SI
(or (srl value 16) (and value #xff00))
(sll (and value #xff) 16)))
)
(dnmf f-dsp-16-u24 "24 bit unsigned" (all-isas) UINT
(f-dsp-16-u16 f-dsp-32-u8)
(sequence () ; insert
(set (ifield f-dsp-16-u16) (and (ifield f-dsp-16-u24) #xffff))
(set (ifield f-dsp-32-u8) (and (srl (ifield f-dsp-16-u24) 16) #xff))
)
(sequence () ; extract
(set (ifield f-dsp-16-u24) (or (sll (ifield f-dsp-32-u8) 16)
(ifield f-dsp-16-u16)))
)
)
(dnmf f-dsp-24-u24 "24 bit unsigned" (all-isas) UINT
(f-dsp-24-u8 f-dsp-32-u16)
(sequence () ; insert
(set (ifield f-dsp-24-u8) (and (ifield f-dsp-24-u24) #xff))
(set (ifield f-dsp-32-u16) (and (srl (ifield f-dsp-24-u24) 8) #xffff))
)
(sequence () ; extract
(set (ifield f-dsp-24-u24) (or (sll (ifield f-dsp-32-u16) 8)
(ifield f-dsp-24-u8)))
)
)
(df f-dsp-32-u24 "24 bit unsigned" (all-isas) 32 24 UINT
((value pc) (or USI
(or USI
(and (srl value 16) #x0000ff)
(and value #x00ff00))
(and (sll value 16) #xff0000))) ; insert
((value pc) (or USI
(or USI
(and USI (srl UHI value 16) #x0000ff)
(and USI value #x00ff00))
(and USI (sll UHI value 16) #xff0000))) ; extract
)
(df f-dsp-40-u24 "24 bit unsigned" (all-isas) 40 24 UINT
((value pc) (or USI
(or USI
(and (srl value 16) #x0000ff)
(and value #x00ff00))
(and (sll value 16) #xff0000))) ; insert
((value pc) (or USI
(or USI
(and USI (srl UHI value 16) #x0000ff)
(and USI value #x00ff00))
(and USI (sll UHI value 16) #xff0000))) ; extract
)
(dnmf f-dsp-40-s32 "32 bit signed" (all-isas) INT
(f-dsp-40-u24 f-dsp-64-u8)
(sequence () ; insert
(set (ifield f-dsp-64-u8) (and (srl (ifield f-dsp-40-s32) 24) #xff))
(set (ifield f-dsp-40-u24) (and (ifield f-dsp-40-s32) #xffffff))
)
(sequence () ; extract
(set (ifield f-dsp-40-s32) (or (and (ifield f-dsp-40-u24) #xffffff)
(and (sll (ifield f-dsp-64-u8) 24) #xff000000)))
)
)
(dnmf f-dsp-48-u24 "24 bit unsigned" (all-isas) UINT
(f-dsp-48-u16 f-dsp-64-u8)
(sequence () ; insert
(set (ifield f-dsp-64-u8) (and (srl (ifield f-dsp-48-u24) 16) #xff))
(set (ifield f-dsp-48-u16) (and (ifield f-dsp-48-u24) #xffff))
)
(sequence () ; extract
(set (ifield f-dsp-48-u24) (or (and (ifield f-dsp-48-u16) #xffff)
(and (sll (ifield f-dsp-64-u8) 16) #xff0000)))
)
)
(dnmf f-dsp-16-s32 "32 bit signed" (all-isas) INT
(f-dsp-16-u16 f-dsp-32-u16)
(sequence () ; insert
(set (ifield f-dsp-32-u16) (and (srl (ifield f-dsp-16-s32) 16) #xffff))
(set (ifield f-dsp-16-u16) (and (ifield f-dsp-16-s32) #xffff))
)
(sequence () ; extract
(set (ifield f-dsp-16-s32) (or (and (ifield f-dsp-16-u16) #xffff)
(and (sll (ifield f-dsp-32-u16) 16) #xffff0000)))
)
)
(dnmf f-dsp-24-s32 "32 bit signed" (all-isas) INT
(f-dsp-24-u8 f-dsp-32-u24)
(sequence () ; insert
(set (ifield f-dsp-32-u24) (and (srl (ifield f-dsp-24-s32) 8) #xffffff))
(set (ifield f-dsp-24-u8) (and (ifield f-dsp-24-s32) #xff))
)
(sequence () ; extract
(set (ifield f-dsp-24-s32) (or (and (ifield f-dsp-24-u8) #xff)
(and (sll (ifield f-dsp-32-u24) 8) #xffffff00)))
)
)
(df f-dsp-32-s32 "32 bit signed" (all-isas) 32 32 INT
((value pc)
;; insert
(ext INT
(or SI
(or SI
(and (srl value 24) #x000000ff)
(and (srl value 8) #x0000ff00))
(or SI
(and (sll value 8) #x00ff0000)
(and (sll value 24) #xff000000)))))
;; extract
((value pc)
(ext INT
(or SI
(or SI
(and (srl value 24) #x000000ff)
(and (srl value 8) #x0000ff00))
(or SI
(and (sll value 8) #x00ff0000)
(and (sll value 24) #xff000000)))))
)
(dnmf f-dsp-48-u32 "32 bit unsigned" (all-isas) UINT
(f-dsp-48-u16 f-dsp-64-u16)
(sequence () ; insert
(set (ifield f-dsp-64-u16) (and (srl (ifield f-dsp-48-u32) 16) #xffff))
(set (ifield f-dsp-48-u16) (and (ifield f-dsp-48-u32) #xffff))
)
(sequence () ; extract
(set (ifield f-dsp-48-u32) (or (and (ifield f-dsp-48-u16) #xffff)
(and (sll (ifield f-dsp-64-u16) 16) #xffff0000)))
)
)
(dnmf f-dsp-48-s32 "32 bit signed" (all-isas) INT
(f-dsp-48-u16 f-dsp-64-u16)
(sequence () ; insert
(set (ifield f-dsp-64-u16) (and (srl (ifield f-dsp-48-s32) 16) #xffff))
(set (ifield f-dsp-48-u16) (and (ifield f-dsp-48-s32) #xffff))
)
(sequence () ; extract
(set (ifield f-dsp-48-s32) (or (and (ifield f-dsp-48-u16) #xffff)
(and (sll (ifield f-dsp-64-u16) 16) #xffff0000)))
)
)
(dnmf f-dsp-56-s16 "16 bit signed" (all-isas) INT
(f-dsp-56-u8 f-dsp-64-u8)
(sequence () ; insert
(set (ifield f-dsp-56-u8)
(and (ifield f-dsp-56-s16) #xff))
(set (ifield f-dsp-64-u8)
(and (srl (ifield f-dsp-56-s16) 8) #xff))
)
(sequence () ; extract
(set (ifield f-dsp-56-s16)
(ext INT
(trunc HI (or (sll (ifield f-dsp-64-u8) 8)
(ifield f-dsp-56-u8)))))
)
)
(df f-dsp-64-s16 " 16 bit signed" (all-isas) 64 16 INT
((value pc) (ext INT
(trunc HI
(or (and (srl value 8) #x00ff)
(and (sll value 8) #xff00))))) ; insert
((value pc) (ext INT
(trunc HI
(or (and (srl value 8) #x00ff)
(and (sll value 8) #xff00))))) ; extract
)
;-------------------------------------------------------------
; Bit indices
;-------------------------------------------------------------
(dnf f-bitno16-S "bit index for m16c" (all-isas) 5 3)
(dnf f-bitno32-prefixed "bit index for m32c" (all-isas) 21 3)
(dnf f-bitno32-unprefixed "bit index for m32c" (all-isas) 13 3)
(dnmf f-bitbase16-u11-S "unsigned bit,base:11" (all-isas) UINT
(f-bitno16-S f-dsp-8-u8)
(sequence () ; insert
(set (ifield f-bitno16-S) (and f-bitbase16-u11-S #x7))
(set (ifield f-dsp-8-u8) (and (srl (ifield f-bitbase16-u11-S) 3) #xff))
)
(sequence () ; extract
(set (ifield f-bitbase16-u11-S) (or (sll (ifield f-dsp-8-u8) 3)
(ifield f-bitno16-S)))
)
)
(dnmf f-bitbase32-16-u11-unprefixed "unsigned bit,base:11" (all-isas) UINT
(f-bitno32-unprefixed f-dsp-16-u8)
(sequence () ; insert
(set (ifield f-bitno32-unprefixed) (and f-bitbase32-16-u11-unprefixed #x7))
(set (ifield f-dsp-16-u8) (and (srl (ifield f-bitbase32-16-u11-unprefixed) 3) #xff))
)
(sequence () ; extract
(set (ifield f-bitbase32-16-u11-unprefixed) (or (sll (ifield f-dsp-16-u8) 3)
(ifield f-bitno32-unprefixed)))
)
)
(dnmf f-bitbase32-16-s11-unprefixed "signed bit,base:11" (all-isas) INT
(f-bitno32-unprefixed f-dsp-16-s8)
(sequence () ; insert
(set (ifield f-bitno32-unprefixed) (and f-bitbase32-16-s11-unprefixed #x7))
(set (ifield f-dsp-16-s8) (sra INT (ifield f-bitbase32-16-s11-unprefixed) 3))
)
(sequence () ; extract
(set (ifield f-bitbase32-16-s11-unprefixed) (or (sll (ifield f-dsp-16-s8) 3)
(ifield f-bitno32-unprefixed)))
)
)
(dnmf f-bitbase32-16-u19-unprefixed "unsigned bit,base:19" (all-isas) UINT
(f-bitno32-unprefixed f-dsp-16-u16)
(sequence () ; insert
(set (ifield f-bitno32-unprefixed) (and f-bitbase32-16-u19-unprefixed #x7))
(set (ifield f-dsp-16-u16) (and (srl (ifield f-bitbase32-16-u19-unprefixed) 3) #xffff))
)
(sequence () ; extract
(set (ifield f-bitbase32-16-u19-unprefixed) (or (sll (ifield f-dsp-16-u16) 3)
(ifield f-bitno32-unprefixed)))
)
)
(dnmf f-bitbase32-16-s19-unprefixed "signed bit,base:11" (all-isas) INT
(f-bitno32-unprefixed f-dsp-16-s16)
(sequence () ; insert
(set (ifield f-bitno32-unprefixed) (and f-bitbase32-16-s19-unprefixed #x7))
(set (ifield f-dsp-16-s16) (sra INT (ifield f-bitbase32-16-s19-unprefixed) 3))
)
(sequence () ; extract
(set (ifield f-bitbase32-16-s19-unprefixed) (or (sll (ifield f-dsp-16-s16) 3)
(ifield f-bitno32-unprefixed)))
)
)
; SID decoder doesn't handle multi-ifield referencing another multi-ifield :-(
(dnmf f-bitbase32-16-u27-unprefixed "unsigned bit,base:27" (all-isas) UINT
(f-bitno32-unprefixed f-dsp-16-u16 f-dsp-32-u8)
(sequence () ; insert
(set (ifield f-bitno32-unprefixed) (and f-bitbase32-16-u27-unprefixed #x7))
(set (ifield f-dsp-16-u16) (and (srl (ifield f-bitbase32-16-u27-unprefixed) 3) #xffff))
(set (ifield f-dsp-32-u8) (and (srl (ifield f-bitbase32-16-u27-unprefixed) 19) #xff))
)
(sequence () ; extract
(set (ifield f-bitbase32-16-u27-unprefixed) (or (sll (ifield f-dsp-16-u16) 3)
(or (sll (ifield f-dsp-32-u8) 19)
(ifield f-bitno32-unprefixed))))
)
)
(dnmf f-bitbase32-24-u11-prefixed "unsigned bit,base:11" (all-isas) UINT
(f-bitno32-prefixed f-dsp-24-u8)
(sequence () ; insert
(set (ifield f-bitno32-prefixed) (and f-bitbase32-24-u11-prefixed #x7))
(set (ifield f-dsp-24-u8) (and (srl (ifield f-bitbase32-24-u11-prefixed) 3) #xff))
)
(sequence () ; extract
(set (ifield f-bitbase32-24-u11-prefixed) (or (sll (ifield f-dsp-24-u8) 3)
(ifield f-bitno32-prefixed)))
)
)
(dnmf f-bitbase32-24-s11-prefixed "signed bit,base:11" (all-isas) INT
(f-bitno32-prefixed f-dsp-24-s8)
(sequence () ; insert
(set (ifield f-bitno32-prefixed) (and f-bitbase32-24-s11-prefixed #x7))
(set (ifield f-dsp-24-s8) (sra INT (ifield f-bitbase32-24-s11-prefixed) 3))
)
(sequence () ; extract
(set (ifield f-bitbase32-24-s11-prefixed) (or (sll (ifield f-dsp-24-s8) 3)
(ifield f-bitno32-prefixed)))
)
)
; SID decoder doesn't handle multi-ifield referencing another multi-ifield :-(
(dnmf f-bitbase32-24-u19-prefixed "unsigned bit,base:19" (all-isas) UINT
(f-bitno32-prefixed f-dsp-24-u8 f-dsp-32-u8)
(sequence () ; insert
(set (ifield f-bitno32-prefixed) (and f-bitbase32-24-u19-prefixed #x7))
(set (ifield f-dsp-24-u8) (and (srl (ifield f-bitbase32-24-u19-prefixed) 3) #xff))
(set (ifield f-dsp-32-u8) (and (srl (ifield f-bitbase32-24-u19-prefixed) 11) #xff))
)
(sequence () ; extract
(set (ifield f-bitbase32-24-u19-prefixed) (or (sll (ifield f-dsp-24-u8) 3)
(or (sll (ifield f-dsp-32-u8) 11)
(ifield f-bitno32-prefixed))))
)
)
; SID decoder doesn't handle multi-ifield referencing another multi-ifield :-(
(dnmf f-bitbase32-24-s19-prefixed "signed bit,base:11" (all-isas) INT
(f-bitno32-prefixed f-dsp-24-u8 f-dsp-32-s8)
(sequence () ; insert
(set (ifield f-bitno32-prefixed) (and f-bitbase32-24-s19-prefixed #x7))
(set (ifield f-dsp-24-u8) (and (srl (ifield f-bitbase32-24-s19-prefixed) 3) #xff))
(set (ifield f-dsp-32-s8) (sra INT (ifield f-bitbase32-24-s19-prefixed) 11))
)
(sequence () ; extract
(set (ifield f-bitbase32-24-s19-prefixed) (or (sll (ifield f-dsp-24-u8) 3)
(or (sll (ifield f-dsp-32-s8) 11)
(ifield f-bitno32-prefixed))))
)
)
; SID decoder doesn't handle multi-ifield referencing another multi-ifield :-(
(dnmf f-bitbase32-24-u27-prefixed "unsigned bit,base:27" (all-isas) UINT
(f-bitno32-prefixed f-dsp-24-u8 f-dsp-32-u16)
(sequence () ; insert
(set (ifield f-bitno32-prefixed) (and f-bitbase32-24-u27-prefixed #x7))
(set (ifield f-dsp-24-u8) (and (srl (ifield f-bitbase32-24-u27-prefixed) 3) #xff))
(set (ifield f-dsp-32-u16) (and (srl (ifield f-bitbase32-24-u27-prefixed) 11) #xffff))
)
(sequence () ; extract
(set (ifield f-bitbase32-24-u27-prefixed) (or (sll (ifield f-dsp-24-u8) 3)
(or (sll (ifield f-dsp-32-u16) 11)
(ifield f-bitno32-prefixed))))
)
)
;-------------------------------------------------------------
; Labels
;-------------------------------------------------------------
(df f-lab-5-3 "3 bit pc relative unsigned offset" (PCREL-ADDR all-isas) 5 3 UINT
((value pc) (sub SI value (add SI pc 2))) ; insert
((value pc) (add SI value (add SI pc 2))) ; extract
)
(dnmf f-lab32-jmp-s "unsigned 3 bit pc relative offset" (PCREL-ADDR all-isas) UINT
(f-2-2 f-7-1)
(sequence ((SI val)) ; insert
(set val (sub (sub (ifield f-lab32-jmp-s) pc) 2))
(set (ifield f-7-1) (and val #x1))
(set (ifield f-2-2) (srl val 1))
)
(sequence () ; extract
(set (ifield f-lab32-jmp-s) (add pc (add (or (sll (ifield f-2-2) 1)
(ifield f-7-1))
2)))
)
)
(df f-lab-8-8 "8 bit pc relative signed offset" (PCREL-ADDR all-isas) 8 8 INT
((value pc) (sub SI value (add SI pc 1))) ; insert
((value pc) (add SI value (add SI pc 1))) ; extract
)
(df f-lab-8-16 "16 bit pc relative signed offset" (PCREL-ADDR SIGN-OPT all-isas) 8 16 UINT
((value pc) (or SI (sll (and (sub value (add pc 1)) #xff) 8)
(srl (and (sub value (add pc 1)) #xffff) 8)))
((value pc) (add SI (or (srl (and value #xffff) 8)
(sra (sll (and value #xff) 24) 16)) (add pc 1)))
)
(df f-lab-8-24 "24 bit absolute" (all-isas ABS-ADDR) 8 24 UINT
((value pc) (or SI
(or (srl value 16) (and value #xff00))
(sll (and value #xff) 16)))
((value pc) (or SI
(or (srl value 16) (and value #xff00))
(sll (and value #xff) 16)))
)
(df f-lab-16-8 "8 bit pc relative signed offset" (PCREL-ADDR all-isas) 16 8 INT
((value pc) (sub SI value (add SI pc 2))) ; insert
((value pc) (add SI value (add SI pc 2))) ; extract
)
(df f-lab-24-8 "8 bit pc relative signed offset" (PCREL-ADDR all-isas) 24 8 INT
((value pc) (sub SI value (add SI pc 2))) ; insert
((value pc) (add SI value (add SI pc 2))) ; extract
)
(df f-lab-32-8 "8 bit pc relative signed offset" (PCREL-ADDR all-isas) 32 8 INT
((value pc) (sub SI value (add SI pc 2))) ; insert
((value pc) (add SI value (add SI pc 2))) ; extract
)
(df f-lab-40-8 "8 bit pc relative signed offset" (PCREL-ADDR all-isas) 40 8 INT
((value pc) (sub SI value (add SI pc 2))) ; insert
((value pc) (add SI value (add SI pc 2))) ; extract
)
;-------------------------------------------------------------
; Condition codes
;-------------------------------------------------------------
(dnf f-cond16 "condition code" (all-isas) 12 4)
(dnf f-cond16j-5 "condition code" (all-isas) 5 3)
(dnmf f-cond32 "condition code" (all-isas) UINT
(f-9-1 f-13-3)
(sequence () ; insert
(set (ifield f-9-1) (and (srl (ifield f-cond32) 3) 1))
(set (ifield f-13-3) (and (ifield f-cond32) #x7))
)
(sequence () ; extract
(set (ifield f-cond32) (or (sll (ifield f-9-1) 3)
(ifield f-13-3)))
)
)
(dnmf f-cond32j "condition code" (all-isas) UINT
(f-1-3 f-7-1)
(sequence () ; insert
(set (ifield f-1-3) (and (srl (ifield f-cond32j) 1) #x7))
(set (ifield f-7-1) (and (ifield f-cond32j) #x1))
)
(sequence () ; extract
(set (ifield f-cond32j) (or (sll (ifield f-1-3) 1)
(ifield f-7-1)))
)
)
;=============================================================
; Hardware
;
(dnh h-pc "program counter" (PC all-isas) (pc USI) () () ())
;-------------------------------------------------------------
; General registers
; The actual registers are 16 bits
;-------------------------------------------------------------
(define-hardware
(name h-gr)
(comment "general 16 bit registers")
(attrs all-isas CACHE-ADDR)
(type register HI (4))
(indices keyword "" (("r0" 0) ("r1" 1) ("r2" 2) ("r3" 3))))
; Define different views of the grs as VIRTUAL with getter/setter specs
;
(define-hardware
(name h-gr-QI)
(comment "general 8 bit registers")
(attrs all-isas VIRTUAL)
(type register QI (4))
(indices keyword "" (("r0l" 0) ("r0h" 1) ("r1l" 2) ("r1h" 3)))
(get (index) (and (if SI (mod index 2)
(srl (reg h-gr (div index 2)) 8)
(reg h-gr (div index 2)))
#xff))
(set (index newval) (set (reg h-gr (div index 2))
(if SI (mod index 2)
(or (and (reg h-gr (div index 2)) #xff)
(sll (and newval #xff) 8))
(or (and (reg h-gr (div index 2)) #xff00)
(and newval #xff))))))
(define-hardware
(name h-gr-HI)
(comment "general 16 bit registers")
(attrs all-isas VIRTUAL)
(type register HI (4))
(indices keyword "" (("r0" 0) ("r1" 1) ("r2" 2) ("r3" 3)))
(get (index) (reg h-gr index))
(set (index newval) (set (reg h-gr index) newval)))
(define-hardware
(name h-gr-SI)
(comment "general 32 bit registers")
(attrs all-isas VIRTUAL)
(type register SI (2))
(indices keyword "" (("r2r0" 0) ("r3r1" 1)))
(get (index) (or SI
(and (reg h-gr index) #xffff)
(and (sll (reg h-gr (add index 2)) 16) #xffff0000)))
(set (index newval) (sequence ()
(set (reg h-gr index) (and newval #xffff))
(set (reg h-gr (add index 2)) (srl newval 16)))))
(define-hardware
(name h-gr-ext-QI)
(comment "general 16 bit registers")
(attrs all-isas VIRTUAL)
(type register HI (2))
(indices keyword "" (("r0l" 0) ("r1l" 1)))
(get (index) (reg h-gr-QI (mul index 2)))
(set (index newval) (set (reg h-gr (mul index 2)) newval)))
(define-hardware
(name h-gr-ext-HI)
(comment "general 16 bit registers")
(attrs all-isas VIRTUAL)
(type register SI (2))
(indices keyword "" (("r0" 0) ("r1" 1)))
(get (index) (reg h-gr (mul index 2)))
(set (index newval) (set (reg h-gr-SI index) newval)))
(define-hardware
(name h-r0l)
(comment "r0l register")
(attrs all-isas VIRTUAL)
(type register QI)
(indices keyword "" (("r0l" 0)))
(get () (reg h-gr-QI 0))
(set (newval) (set (reg h-gr-QI 0) newval)))
(define-hardware
(name h-r0h)
(comment "r0h register")
(attrs all-isas VIRTUAL)
(type register QI)
(indices keyword "" (("r0h" 0)))
(get () (reg h-gr-QI 1))
(set (newval) (set (reg h-gr-QI 1) newval)))
(define-hardware
(name h-r1l)
(comment "r1l register")
(attrs all-isas VIRTUAL)
(type register QI)
(indices keyword "" (("r1l" 0)))
(get () (reg h-gr-QI 2))
(set (newval) (set (reg h-gr-QI 2) newval)))
(define-hardware
(name h-r1h)
(comment "r1h register")
(attrs all-isas VIRTUAL)
(type register QI)
(indices keyword "" (("r1h" 0)))
(get () (reg h-gr-QI 3))
(set (newval) (set (reg h-gr-QI 3) newval)))
(define-hardware
(name h-r0)
(comment "r0 register")
(attrs all-isas VIRTUAL)
(type register HI)
(indices keyword "" (("r0" 0)))
(get () (reg h-gr 0))
(set (newval) (set (reg h-gr 0) newval)))
(define-hardware
(name h-r1)
(comment "r1 register")
(attrs all-isas VIRTUAL)
(type register HI)
(indices keyword "" (("r1" 0)))
(get () (reg h-gr 1))
(set (newval) (set (reg h-gr 1) newval)))
(define-hardware
(name h-r2)
(comment "r2 register")
(attrs all-isas VIRTUAL)
(type register HI)
(indices keyword "" (("r2" 0)))
(get () (reg h-gr 2))
(set (newval) (set (reg h-gr 2) newval)))
(define-hardware
(name h-r3)
(comment "r3 register")
(attrs all-isas VIRTUAL)
(type register HI)
(indices keyword "" (("r3" 0)))
(get () (reg h-gr 3))
(set (newval) (set (reg h-gr 3) newval)))
(define-hardware
(name h-r0l-r0h)
(comment "r0l or r0h")
(attrs all-isas VIRTUAL)
(type register QI (2))
(indices keyword "" (("r0l" 0) ("r0h" 1)))
(get (index) (reg h-gr-QI index))
(set (index newval) (set (reg h-gr-QI index) newval)))
(define-hardware
(name h-r2r0)
(comment "r2r0 register")
(attrs all-isas VIRTUAL)
(type register SI)
(indices keyword "" (("r2r0" 0)))
(get () (or (sll (reg h-gr 2) 16) (reg h-gr 0)))
(set (newval)
(sequence ()
(set (reg h-gr 0) newval)
(set (reg h-gr 2) (sra newval 16)))))
(define-hardware
(name h-r3r1)
(comment "r3r1 register")
(attrs all-isas VIRTUAL)
(type register SI)
(indices keyword "" (("r3r1" 0)))
(get () (or (sll (reg h-gr 3) 16) (reg h-gr 1)))
(set (newval)
(sequence ()
(set (reg h-gr 1) newval)
(set (reg h-gr 3) (sra newval 16)))))
(define-hardware
(name h-r1r2r0)
(comment "r1r2r0 register")
(attrs all-isas VIRTUAL)
(type register DI)
(indices keyword "" (("r1r2r0" 0)))
(get () (or DI (sll DI (reg h-gr 1) 32) (or (sll (reg h-gr 2) 16) (reg h-gr 0))))
(set (newval)
(sequence ()
(set (reg h-gr 0) newval)
(set (reg h-gr 2) (sra newval 16))
(set (reg h-gr 1) (sra newval 32)))))
;-------------------------------------------------------------
; Address registers
;-------------------------------------------------------------
(define-hardware
(name h-ar)
(comment "address registers")
(attrs all-isas)
(type register USI (2))
(indices keyword "" (("a0" 0) ("a1" 1)))
(get (index) (c-call USI "h_ar_get_handler" index))
(set (index newval) (c-call VOID "h_ar_set_handler" index newval)))
; Define different views of the ars as VIRTUAL with getter/setter specs
(define-hardware
(name h-ar-QI)
(comment "8 bit view of address register")
(attrs all-isas VIRTUAL)
(type register QI (2))
(indices keyword "" (("a0" 0) ("a1" 1)))
(get (index) (reg h-ar index))
(set (index newval) (set (reg h-ar index) newval)))
(define-hardware
(name h-ar-HI)
(comment "16 bit view of address register")
(attrs all-isas VIRTUAL)
(type register HI (2))
(indices keyword "" (("a0" 0) ("a1" 1)))
(get (index) (reg h-ar index))
(set (index newval) (set (reg h-ar index) newval)))
(define-hardware
(name h-ar-SI)
(comment "32 bit view of address register")
(attrs all-isas VIRTUAL)
(type register SI)
(indices keyword "" (("a1a0" 0)))
(get () (or SI (sll SI (ext SI (reg h-ar 1)) 16) (ext SI (reg h-ar 0))))
(set (newval) (sequence ()
(set (reg h-ar 0) (and newval #xffff))
(set (reg h-ar 1) (and (srl newval 16) #xffff)))))
(define-hardware
(name h-a0)
(comment "16 bit view of address register")
(attrs all-isas VIRTUAL)
(type register HI)
(indices keyword "" (("a0" 0)))
(get () (reg h-ar 0))
(set (newval) (set (reg h-ar 0) newval)))
(define-hardware
(name h-a1)
(comment "16 bit view of address register")
(attrs all-isas VIRTUAL)
(type register HI)
(indices keyword "" (("a1" 1)))
(get () (reg h-ar 1))
(set (newval) (set (reg h-ar 1) newval)))
; SB Register
(define-hardware
(name h-sb)
(comment "SB register")
(attrs all-isas)
(type register USI)
(get () (c-call USI "h_sb_get_handler"))
(set (newval) (c-call VOID "h_sb_set_handler" newval))
)
; FB Register
(define-hardware
(name h-fb)
(comment "FB register")
(attrs all-isas)
(type register USI)
(get () (c-call USI "h_fb_get_handler"))
(set (newval) (c-call VOID "h_fb_set_handler" newval))
)
; SP Register
(define-hardware
(name h-sp)
(comment "SP register")
(attrs all-isas)
(type register USI)
(get () (c-call USI "h_sp_get_handler"))
(set (newval) (c-call VOID "h_sp_set_handler" newval))
)
;-------------------------------------------------------------
; condition-code bits
;-------------------------------------------------------------
(define-hardware
(name h-sbit)
(comment "sign bit")
(attrs all-isas)
(type register BI)
)
(define-hardware
(name h-zbit)
(comment "zero bit")
(attrs all-isas)
(type register BI)
)
(define-hardware
(name h-obit)
(comment "overflow bit")
(attrs all-isas)
(type register BI)
)
(define-hardware
(name h-cbit)
(comment "carry bit")
(attrs all-isas)
(type register BI)
)
(define-hardware
(name h-ubit)
(comment "stack pointer select bit")
(attrs all-isas)
(type register BI)
)
(define-hardware
(name h-ibit)
(comment "interrupt enable bit")
(attrs all-isas)
(type register BI)
)
(define-hardware
(name h-bbit)
(comment "register bank select bit")
(attrs all-isas)
(type register BI)
)
(define-hardware
(name h-dbit)
(comment "debug bit")
(attrs all-isas)
(type register BI)
)
(define-hardware
(name h-dct0)
(comment "dma transfer count 000")
(attrs all-isas)
(type register UHI)
)
(define-hardware
(name h-dct1)
(comment "dma transfer count 001")
(attrs all-isas)
(type register UHI)
)
(define-hardware
(name h-svf)
(comment "save flag 011")
(attrs all-isas)
(type register UHI)
)
(define-hardware
(name h-drc0)
(comment "dma transfer count reload 100")
(attrs all-isas)
(type register UHI)
)
(define-hardware
(name h-drc1)
(comment "dma transfer count reload 101")
(attrs all-isas)
(type register UHI)
)
(define-hardware
(name h-dmd0)
(comment "dma mode 110")
(attrs all-isas)
(type register UQI)
)
(define-hardware
(name h-dmd1)
(comment "dma mode 111")
(attrs all-isas)
(type register UQI)
)
(define-hardware
(name h-intb)
(comment "interrupt table 000")
(attrs all-isas)
(type register USI)
)
(define-hardware
(name h-svp)
(comment "save pc 100")
(attrs all-isas)
(type register UHI)
)
(define-hardware
(name h-vct)
(comment "vector 101")
(attrs all-isas)
(type register USI)
)
(define-hardware
(name h-isp)
(comment "interrupt stack ptr 111")
(attrs all-isas)
(type register USI)
)
(define-hardware
(name h-dma0)
(comment "dma mem addr 010")
(attrs all-isas)
(type register USI)
)
(define-hardware
(name h-dma1)
(comment "dma mem addr 011")
(attrs all-isas)
(type register USI)
)
(define-hardware
(name h-dra0)
(comment "dma mem addr reload 100")
(attrs all-isas)
(type register USI)
)
(define-hardware
(name h-dra1)
(comment "dma mem addr reload 101")
(attrs all-isas)
(type register USI)
)
(define-hardware
(name h-dsa0)
(comment "dma sfr addr 110")
(attrs all-isas)
(type register USI)
)
(define-hardware
(name h-dsa1)
(comment "dma sfr addr 111")
(attrs all-isas)
(type register USI)
)
;-------------------------------------------------------------
; Condition code operand hardware
;-------------------------------------------------------------
(define-hardware
(name h-cond16)
(comment "condition code hardware for m16c")
(attrs m16c-isa MACH16)
(type immediate UQI)
(values keyword ""
(("geu" #x00) ("c" #x00)
("gtu" #x01)
("eq" #x02) ("z" #x02)
("n" #x03)
("le" #x04)
("o" #x05)
("ge" #x06)
("ltu" #xf8) ("nc" #xf8)
("leu" #xf9)
("ne" #xfa) ("nz" #xfa)
("pz" #xfb)
("gt" #xfc)
("no" #xfd)
("lt" #xfe)
)
)
)
(define-hardware
(name h-cond16c)
(comment "condition code hardware for m16c")
(attrs m16c-isa MACH16)
(type immediate UQI)
(values keyword ""
(("geu" #x00) ("c" #x00)
("gtu" #x01)
("eq" #x02) ("z" #x02)
("n" #x03)
("ltu" #x04) ("nc" #x04)
("leu" #x05)
("ne" #x06) ("nz" #x06)
("pz" #x07)
("le" #x08)
("o" #x09)
("ge" #x0a)
("gt" #x0c)
("no" #x0d)
("lt" #x0e)
)
)
)
(define-hardware
(name h-cond16j)
(comment "condition code hardware for m16c")
(attrs m16c-isa MACH16)
(type immediate UQI)
(values keyword ""
(("le" #x08)
("o" #x09)
("ge" #x0a)
("gt" #x0c)
("no" #x0d)
("lt" #x0e)
)
)
)
(define-hardware
(name h-cond16j-5)
(comment "condition code hardware for m16c")
(attrs m16c-isa MACH16)
(type immediate UQI)
(values keyword ""
(("geu" #x00) ("c" #x00)
("gtu" #x01)
("eq" #x02) ("z" #x02)
("n" #x03)
("ltu" #x04) ("nc" #x04)
("leu" #x05)
("ne" #x06) ("nz" #x06)
("pz" #x07)
)
)
)
(define-hardware
(name h-cond32)
(comment "condition code hardware for m32c")
(attrs m32c-isa MACH32)
(type immediate UQI)
(values keyword ""
(("ltu" #x00) ("nc" #x00)
("leu" #x01)
("ne" #x02) ("nz" #x02)
("pz" #x03)
("no" #x04)
("gt" #x05)
("ge" #x06)
("geu" #x08) ("c" #x08)
("gtu" #x09)
("eq" #x0a) ("z" #x0a)
("n" #x0b)
("o" #x0c)
("le" #x0d)
("lt" #x0e)
)
)
)
(define-hardware
(name h-cr1-32)
(comment "control registers")
(attrs m32c-isa MACH32)
(type immediate UQI)
(values keyword "" (("dct0" 0) ("dct1" 1) ("flg" 2) ("svf" 3) ("drc0" 4)
("drc1" 5) ("dmd0" 6) ("dmd1" 7))))
(define-hardware
(name h-cr2-32)
(comment "control registers")
(attrs m32c-isa MACH32)
(type immediate UQI)
(values keyword "" (("intb" 0) ("sp" 1) ("sb" 2) ("fb" 3) ("svp" 4)
("vct" 5) ("isp" 7))))
(define-hardware
(name h-cr3-32)
(comment "control registers")
(attrs m32c-isa MACH32)
(type immediate UQI)
(values keyword "" (("dma0" 2) ("dma1" 3) ("dra0" 4)
("dra1" 5) ("dsa0" 6) ("dsa1" 7))))
(define-hardware
(name h-cr-16)
(comment "control registers")
(attrs m16c-isa MACH16)
(type immediate UQI)
(values keyword "" (("intbl" 1) ("intbh" 2) ("flg" 3) ("isp" 4)
("sp" 5) ("sb" 6) ("fb" 7))))
(define-hardware
(name h-flags)
(comment "flag hardware for m32c")
(attrs all-isas)
(type immediate UQI)
(values keyword ""
(("c" #x0)
("d" #x1)
("z" #x2)
("s" #x3)
("b" #x4)
("o" #x5)
("i" #x6)
("u" #x7)
)
)
)
;-------------------------------------------------------------
; Misc helper hardware
;-------------------------------------------------------------
(define-hardware
(name h-shimm)
(comment "shift immediate")
(attrs all-isas)
(type immediate (INT 4))
(values keyword "" (("1" 0) ("2" 1) ("3" 2) ("4" 3) ("5" 4) ("6" 5) ("7" 6)
("8" 7) ("-1" -8) ("-2" -7) ("-3" -6) ("-4" -5) ("-5" -4)
("-6" -3) ("-7" -2) ("-8" -1)
)))
(define-hardware
(name h-bit-index)
(comment "bit index for the next insn")
(attrs m32c-isa MACH32)
(type register UHI)
)
(define-hardware
(name h-src-index)
(comment "source index for the next insn")
(attrs m32c-isa MACH32)
(type register UHI)
)
(define-hardware
(name h-dst-index)
(comment "destination index for the next insn")
(attrs m32c-isa MACH32)
(type register UHI)
)
(define-hardware
(name h-src-indirect)
(comment "indirect src for the next insn")
(attrs all-isas)
(type register UHI)
)
(define-hardware
(name h-dst-indirect)
(comment "indirect dst for the next insn")
(attrs all-isas)
(type register UHI)
)
(define-hardware
(name h-none)
(comment "for storing unused values")
(attrs m32c-isa MACH32)
(type register SI)
)
;=============================================================
; Operands
;-------------------------------------------------------------
; Source Registers
;-------------------------------------------------------------
(dnop Src16RnQI "general register QI view" (MACH16 m16c-isa) h-gr-QI f-src16-rn)
(dnop Src16RnHI "general register QH view" (MACH16 m16c-isa) h-gr-HI f-src16-rn)
(dnop Src32RnUnprefixedQI "general register QI view" (MACH32 m32c-isa) h-gr-QI f-src32-rn-unprefixed-QI)
(dnop Src32RnUnprefixedHI "general register HI view" (MACH32 m32c-isa) h-gr-HI f-src32-rn-unprefixed-HI)
(dnop Src32RnUnprefixedSI "general register SI view" (MACH32 m32c-isa) h-gr-SI f-src32-rn-unprefixed-SI)
(dnop Src32RnPrefixedQI "general register QI view" (MACH32 m32c-isa) h-gr-QI f-src32-rn-prefixed-QI)
(dnop Src32RnPrefixedHI "general register HI view" (MACH32 m32c-isa) h-gr-HI f-src32-rn-prefixed-HI)
(dnop Src32RnPrefixedSI "general register SI view" (MACH32 m32c-isa) h-gr-SI f-src32-rn-prefixed-SI)
(dnop Src16An "address register" (MACH16 m16c-isa) h-ar f-src16-an)
(dnop Src16AnQI "address register QI view" (MACH16 m16c-isa) h-ar-QI f-src16-an)
(dnop Src16AnHI "address register HI view" (MACH16 m16c-isa) h-ar-HI f-src16-an)
(dnop Src32AnUnprefixed "address register" (MACH32 m32c-isa) h-ar f-src32-an-unprefixed)
(dnop Src32AnUnprefixedQI "address register QI view" (MACH32 m32c-isa) h-ar-QI f-src32-an-unprefixed)
(dnop Src32AnUnprefixedHI "address register HI view" (MACH32 m32c-isa) h-ar-HI f-src32-an-unprefixed)
(dnop Src32AnUnprefixedSI "address register SI view" (MACH32 m32c-isa) h-ar f-src32-an-unprefixed)
(dnop Src32AnPrefixed "address register" (MACH32 m32c-isa) h-ar f-src32-an-prefixed)
(dnop Src32AnPrefixedQI "address register QI view" (MACH32 m32c-isa) h-ar-QI f-src32-an-prefixed)
(dnop Src32AnPrefixedHI "address register HI view" (MACH32 m32c-isa) h-ar-HI f-src32-an-prefixed)
(dnop Src32AnPrefixedSI "address register SI view" (MACH32 m32c-isa) h-ar f-src32-an-prefixed)
; Destination Registers
;
(dnop Dst16RnQI "general register QI view" (MACH16 m16c-isa) h-gr-QI f-dst16-rn)
(dnop Dst16RnHI "general register HI view" (MACH16 m16c-isa) h-gr-HI f-dst16-rn)
(dnop Dst16RnSI "general register SI view" (MACH16 m16c-isa) h-gr-SI f-dst16-rn)
(dnop Dst16RnExtQI "general register QI/HI view for 'ext' insns" (MACH16 m16c-isa) h-gr-ext-QI f-dst16-rn-ext)
(dnop Dst32R0QI-S "general register QI view" (MACH32 m32c-isa) h-r0l f-nil)
(dnop Dst32R0HI-S "general register HI view" (MACH32 m32c-isa) h-r0 f-nil)
(dnop Dst32RnUnprefixedQI "general register QI view" (MACH32 m32c-isa) h-gr-QI f-dst32-rn-unprefixed-QI)
(dnop Dst32RnUnprefixedHI "general register HI view" (MACH32 m32c-isa) h-gr-HI f-dst32-rn-unprefixed-HI)
(dnop Dst32RnUnprefixedSI "general register SI view" (MACH32 m32c-isa) h-gr-SI f-dst32-rn-unprefixed-SI)
(dnop Dst32RnExtUnprefixedQI "general register QI view" (MACH32 m32c-isa) h-gr-ext-QI f-dst32-rn-ext-unprefixed)
(dnop Dst32RnExtUnprefixedHI "general register HI view" (MACH32 m32c-isa) h-gr-ext-HI f-dst32-rn-ext-unprefixed)
(dnop Dst32RnPrefixedQI "general register QI view" (MACH32 m32c-isa) h-gr-QI f-dst32-rn-prefixed-QI)
(dnop Dst32RnPrefixedHI "general register HI view" (MACH32 m32c-isa) h-gr-HI f-dst32-rn-prefixed-HI)
(dnop Dst32RnPrefixedSI "general register SI view" (MACH32 m32c-isa) h-gr-SI f-dst32-rn-prefixed-SI)
(dnop Dst16RnQI-S "general register QI view" (MACH16 m16c-isa) h-r0l-r0h f-dst16-rn-QI-s)
(dnop Dst16AnQI-S "address register QI view" (MACH16 m16c-isa) h-ar-QI f-dst16-rn-QI-s)
(dnop Bit16Rn "general register bit view" (MACH16 m16c-isa) h-gr-HI f-dst16-rn)
(dnop Bit32RnPrefixed "general register bit view" (MACH32 m32c-isa) h-gr-QI f-dst32-rn-prefixed-QI)
(dnop Bit32RnUnprefixed "general register bit view" (MACH32 m32c-isa) h-gr-QI f-dst32-rn-unprefixed-QI)
(dnop R0 "r0" (all-isas) h-r0 f-nil)
(dnop R1 "r1" (all-isas) h-r1 f-nil)
(dnop R2 "r2" (all-isas) h-r2 f-nil)
(dnop R3 "r3" (all-isas) h-r3 f-nil)
(dnop R0l "r0l" (all-isas) h-r0l f-nil)
(dnop R0h "r0h" (all-isas) h-r0h f-nil)
(dnop R2R0 "r2r0" (all-isas) h-r2r0 f-nil)
(dnop R3R1 "r3r1" (all-isas) h-r3r1 f-nil)
(dnop R1R2R0 "r1r2r0" (all-isas) h-r1r2r0 f-nil)
(dnop Dst16An "address register" (MACH16 m16c-isa) h-ar f-dst16-an)
(dnop Dst16AnQI "address register QI view" (MACH16 m16c-isa) h-ar-QI f-dst16-an)
(dnop Dst16AnHI "address register HI view" (MACH16 m16c-isa) h-ar-HI f-dst16-an)
(dnop Dst16AnSI "address register SI view" (MACH16 m16c-isa) h-ar-SI f-dst16-an)
(dnop Dst16An-S "address register HI view" (MACH16 m16c-isa) h-ar-HI f-dst16-an-s)
(dnop Dst32AnUnprefixed "address register" (MACH32 m32c-isa) h-ar f-dst32-an-unprefixed)
(dnop Dst32AnUnprefixedQI "address register QI view" (MACH32 m32c-isa) h-ar-QI f-dst32-an-unprefixed)
(dnop Dst32AnUnprefixedHI "address register HI view" (MACH32 m32c-isa) h-ar-HI f-dst32-an-unprefixed)
(dnop Dst32AnUnprefixedSI "address register SI view" (MACH32 m32c-isa) h-ar f-dst32-an-unprefixed)
(dnop Dst32AnExtUnprefixed "address register" (MACH32 m32c-isa) h-ar f-dst32-an-unprefixed)
(dnop Dst32AnPrefixed "address register" (MACH32 m32c-isa) h-ar f-dst32-an-prefixed)
(dnop Dst32AnPrefixedQI "address register QI view" (MACH32 m32c-isa) h-ar-QI f-dst32-an-prefixed)
(dnop Dst32AnPrefixedHI "address register HI view" (MACH32 m32c-isa) h-ar-HI f-dst32-an-prefixed)
(dnop Dst32AnPrefixedSI "address register SI view" (MACH32 m32c-isa) h-ar f-dst32-an-prefixed)
(dnop Bit16An "address register bit view" (MACH16 m16c-isa) h-ar f-dst16-an)
(dnop Bit32AnPrefixed "address register bit" (MACH32 m32c-isa) h-ar f-dst32-an-prefixed)
(dnop Bit32AnUnprefixed "address register bit" (MACH32 m32c-isa) h-ar f-dst32-an-unprefixed)
(dnop A0 "a0" (all-isas) h-a0 f-nil)
(dnop A1 "a1" (all-isas) h-a1 f-nil)
(dnop sb "SB register" (all-isas SEM-ONLY) h-sb f-nil)
(dnop fb "FB register" (all-isas SEM-ONLY) h-fb f-nil)
(dnop sp "SP register" (all-isas SEM-ONLY) h-sp f-nil)
(define-full-operand SrcDst16-r0l-r0h-S-normal "r0l/r0h pair" (MACH16 m16c-isa)
h-sint DFLT f-5-1
((parse "r0l_r0h") (print "r0l_r0h")) () ()
)
(define-full-operand Regsetpop "popm regset" (all-isas) h-uint
DFLT f-8-8 ((parse "pop_regset") (print "pop_regset")) () ())
(define-full-operand Regsetpush "pushm regset" (all-isas) h-uint
DFLT f-8-8 ((parse "push_regset") (print "push_regset")) () ())
(dnop Rn16-push-S "r0[lh]" (MACH16 m16c-isa) h-gr-QI f-4-1)
(dnop An16-push-S "a[01]" (MACH16 m16c-isa) h-ar-HI f-4-1)
;-------------------------------------------------------------
; Offsets and absolutes
;-------------------------------------------------------------
(define-full-operand Dsp-8-u6 "unsigned 6 bit displacement at offset 8 bits" (all-isas)
h-uint DFLT f-dsp-8-u6
((parse "unsigned6")) () ()
)
(define-full-operand Dsp-8-u8 "unsigned 8 bit displacement at offset 8 bits" (all-isas)
h-uint DFLT f-dsp-8-u8
((parse "unsigned8")) () ()
)
(define-full-operand Dsp-8-u16 "unsigned 16 bit displacement at offset 8 bits" (all-isas)
h-uint DFLT f-dsp-8-u16
((parse "unsigned16")) () ()
)
(define-full-operand Dsp-8-s8 "signed 8 bit displacement at offset 8 bits" (all-isas)
h-sint DFLT f-dsp-8-s8
((parse "signed8")) () ()
)
(define-full-operand Dsp-8-s24 "signed 24 bit displacement at offset 8 bits" (all-isas)
h-sint DFLT f-dsp-8-s24
((parse "signed24")) () ()
)
(define-full-operand Dsp-8-u24 "unsigned 24 bit displacement at offset 8 bits" (all-isas)
h-uint DFLT f-dsp-8-u24
((parse "unsigned24")) () ()
)
(define-full-operand Dsp-10-u6 "unsigned 6 bit displacement at offset 10 bits" (all-isas)
h-uint DFLT f-dsp-10-u6
((parse "unsigned6")) () ()
)
(define-full-operand Dsp-16-u8 "unsigned 8 bit displacement at offset 16 bits" (all-isas)
h-uint DFLT f-dsp-16-u8
((parse "unsigned8")) () ()
)
(define-full-operand Dsp-16-u16 "unsigned 16 bit displacement at offset 16 bits" (all-isas)
h-uint DFLT f-dsp-16-u16
((parse "unsigned16")) () ()
)
(define-full-operand Dsp-16-u20 "unsigned 20 bit displacement at offset 16 bits" (all-isas)
h-uint DFLT f-dsp-16-u24
((parse "unsigned20")) () ()
)
(define-full-operand Dsp-16-u24 "unsigned 24 bit displacement at offset 16 bits" (all-isas)
h-uint DFLT f-dsp-16-u24
((parse "unsigned24")) () ()
)
(define-full-operand Dsp-16-s8 "signed 8 bit displacement at offset 16 bits" (all-isas)
h-sint DFLT f-dsp-16-s8
((parse "signed8")) () ()
)
(define-full-operand Dsp-16-s16 "signed 16 bit displacement at offset 16 bits" (all-isas)
h-sint DFLT f-dsp-16-s16
((parse "signed16")) () ()
)
(define-full-operand Dsp-24-u8 "unsigned 8 bit displacement at offset 24 bits" (all-isas)
h-uint DFLT f-dsp-24-u8
((parse "unsigned8")) () ()
)
(define-full-operand Dsp-24-u16 "unsigned 16 bit displacement at offset 24 bits" (all-isas)
h-uint DFLT f-dsp-24-u16
((parse "unsigned16")) () ()
)
(define-full-operand Dsp-24-u20 "unsigned 20 bit displacement at offset 24 bits" (all-isas)
h-uint DFLT f-dsp-24-u24
((parse "unsigned20")) () ()
)
(define-full-operand Dsp-24-u24 "unsigned 24 bit displacement at offset 24 bits" (all-isas)
h-uint DFLT f-dsp-24-u24
((parse "unsigned24")) () ()
)
(define-full-operand Dsp-24-s8 "signed 8 bit displacement at offset 24 bits" (all-isas)
h-sint DFLT f-dsp-24-s8
((parse "signed8")) () ()
)
(define-full-operand Dsp-24-s16 "signed 16 bit displacement at offset 24 bits" (all-isas)
h-sint DFLT f-dsp-24-s16
((parse "signed16")) () ()
)
(define-full-operand Dsp-32-u8 "unsigned 8 bit displacement at offset 32 bits" (all-isas)
h-uint DFLT f-dsp-32-u8
((parse "unsigned8")) () ()
)
(define-full-operand Dsp-32-u16 "unsigned 16 bit displacement at offset 32 bits" (all-isas)
h-uint DFLT f-dsp-32-u16
((parse "unsigned16")) () ()
)
(define-full-operand Dsp-32-u24 "unsigned 24 bit displacement at offset 32 bits" (all-isas)
h-uint DFLT f-dsp-32-u24
((parse "unsigned24")) () ()
)
(define-full-operand Dsp-32-u20 "unsigned 20 bit displacement at offset 32 bits" (all-isas)
h-uint DFLT f-dsp-32-u24
((parse "unsigned20")) () ()
)
(define-full-operand Dsp-32-s8 "signed 8 bit displacement at offset 32 bits" (all-isas)
h-sint DFLT f-dsp-32-s8
((parse "signed8")) () ()
)
(define-full-operand Dsp-32-s16 "signed 16 bit displacement at offset 32 bits" (all-isas)
h-sint DFLT f-dsp-32-s16
((parse "signed16")) () ()
)
(define-full-operand Dsp-40-u8 "unsigned 8 bit displacement at offset 40 bits" (all-isas)
h-uint DFLT f-dsp-40-u8
((parse "unsigned8")) () ()
)
(define-full-operand Dsp-40-s8 "signed 8 bit displacement at offset 40 bits" (all-isas)
h-sint DFLT f-dsp-40-s8
((parse "signed8")) () ()
)
(define-full-operand Dsp-40-u16 "unsigned 16 bit displacement at offset 40 bits" (all-isas)
h-uint DFLT f-dsp-40-u16
((parse "unsigned16")) () ()
)
(define-full-operand Dsp-40-s16 "signed 16 bit displacement at offset 40 bits" (all-isas)
h-sint DFLT f-dsp-40-s16
((parse "signed16")) () ()
)
(define-full-operand Dsp-40-u24 "unsigned 24 bit displacement at offset 40 bits" (all-isas)
h-uint DFLT f-dsp-40-u24
((parse "unsigned24")) () ()
)
(define-full-operand Dsp-48-u8 "unsigned 8 bit displacement at offset 48 bits" (all-isas)
h-uint DFLT f-dsp-48-u8
((parse "unsigned8")) () ()
)
(define-full-operand Dsp-48-s8 "signed 8 bit displacement at offset 48 bits" (all-isas)
h-sint DFLT f-dsp-48-s8
((parse "signed8")) () ()
)
(define-full-operand Dsp-48-u16 "unsigned 16 bit displacement at offset 48 bits" (all-isas)
h-uint DFLT f-dsp-48-u16
((parse "unsigned16")) () ()
)
(define-full-operand Dsp-48-s16 "signed 16 bit displacement at offset 48 bits" (all-isas)
h-sint DFLT f-dsp-48-s16
((parse "signed16")) () ()
)
(define-full-operand Dsp-48-u24 "unsigned 24 bit displacement at offset 48 bits" (all-isas)
h-uint DFLT f-dsp-48-u24
((parse "unsigned24")) () ()
)
(define-full-operand Imm-8-s4 "signed 4 bit immediate at offset 8 bits" (all-isas)
h-sint DFLT f-imm-8-s4
((parse "signed4")) () ()
)
(define-full-operand Imm-8-s4n "negated 4 bit immediate at offset 8 bits" (all-isas)
h-sint DFLT f-imm-8-s4
((parse "signed4n")) () ()
)
(define-full-operand Imm-sh-8-s4 "signed 4 bit shift immediate at offset 8 bits" (all-isas)
h-shimm DFLT f-imm-8-s4
() () ()
)
(define-full-operand Imm-8-QI "signed 8 bit immediate at offset 8 bits" (all-isas)
h-sint DFLT f-dsp-8-s8
((parse "signed8")) () ()
)
(define-full-operand Imm-8-HI "signed 16 bit immediate at offset 8 bits" (all-isas)
h-sint DFLT f-dsp-8-s16
((parse "signed16")) () ()
)
(define-full-operand Imm-12-s4 "signed 4 bit immediate at offset 12 bits" (all-isas)
h-sint DFLT f-imm-12-s4
((parse "signed4")) () ()
)
(define-full-operand Imm-12-s4n "negated 4 bit immediate at offset 12 bits" (all-isas)
h-sint DFLT f-imm-12-s4
((parse "signed4n") (print "signed4n")) () ()
)
(define-full-operand Imm-sh-12-s4 "signed 4 bit shift immediate at offset 12 bits" (all-isas)
h-shimm DFLT f-imm-12-s4
() () ()
)
(define-full-operand Imm-13-u3 "signed 3 bit immediate at offset 13 bits" (all-isas)
h-sint DFLT f-imm-13-u3
((parse "signed4")) () ()
)
(define-full-operand Imm-20-s4 "signed 4 bit immediate at offset 20 bits" (all-isas)
h-sint DFLT f-imm-20-s4
((parse "signed4")) () ()
)
(define-full-operand Imm-sh-20-s4 "signed 4 bit shift immediate at offset 12 bits" (all-isas)
h-shimm DFLT f-imm-20-s4
() () ()
)
(define-full-operand Imm-16-QI "signed 8 bit immediate at offset 16 bits" (all-isas)
h-sint DFLT f-dsp-16-s8
((parse "signed8")) () ()
)
(define-full-operand Imm-16-HI "signed 16 bit immediate at offset 16 bits" (all-isas)
h-sint DFLT f-dsp-16-s16
((parse "signed16")) () ()
)
(define-full-operand Imm-16-SI "signed 32 bit immediate at offset 16 bits" (all-isas)
h-sint DFLT f-dsp-16-s32
((parse "signed32")) () ()
)
(define-full-operand Imm-24-QI "signed 8 bit immediate at offset 24 bits" (all-isas)
h-sint DFLT f-dsp-24-s8
((parse "signed8")) () ()
)
(define-full-operand Imm-24-HI "signed 16 bit immediate at offset 24 bits" (all-isas)
h-sint DFLT f-dsp-24-s16
((parse "signed16")) () ()
)
(define-full-operand Imm-24-SI "signed 32 bit immediate at offset 24 bits" (all-isas)
h-sint DFLT f-dsp-24-s32
((parse "signed32")) () ()
)
(define-full-operand Imm-32-QI "signed 8 bit immediate at offset 32 bits" (all-isas)
h-sint DFLT f-dsp-32-s8
((parse "signed8")) () ()
)
(define-full-operand Imm-32-SI "signed 32 bit immediate at offset 32 bits" (all-isas)
h-sint DFLT f-dsp-32-s32
((parse "signed32")) () ()
)
(define-full-operand Imm-32-HI "signed 16 bit immediate at offset 32 bits" (all-isas)
h-sint DFLT f-dsp-32-s16
((parse "signed16")) () ()
)
(define-full-operand Imm-40-QI "signed 8 bit immediate at offset 40 bits" (all-isas)
h-sint DFLT f-dsp-40-s8
((parse "signed8")) () ()
)
(define-full-operand Imm-40-HI "signed 16 bit immediate at offset 40 bits" (all-isas)
h-sint DFLT f-dsp-40-s16
((parse "signed16")) () ()
)
(define-full-operand Imm-40-SI "signed 32 bit immediate at offset 40 bits" (all-isas)
h-sint DFLT f-dsp-40-s32
((parse "signed32")) () ()
)
(define-full-operand Imm-48-QI "signed 8 bit immediate at offset 48 bits" (all-isas)
h-sint DFLT f-dsp-48-s8
((parse "signed8")) () ()
)
(define-full-operand Imm-48-HI "signed 16 bit immediate at offset 48 bits" (all-isas)
h-sint DFLT f-dsp-48-s16
((parse "signed16")) () ()
)
(define-full-operand Imm-48-SI "signed 32 bit immediate at offset 48 bits" (all-isas)
h-sint DFLT f-dsp-48-s32
((parse "signed32")) () ()
)
(define-full-operand Imm-56-QI "signed 8 bit immediate at offset 56 bits" (all-isas)
h-sint DFLT f-dsp-56-s8
((parse "signed8")) () ()
)
(define-full-operand Imm-56-HI "signed 16 bit immediate at offset 56 bits" (all-isas)
h-sint DFLT f-dsp-56-s16
((parse "signed16")) () ()
)
(define-full-operand Imm-64-HI "signed 16 bit immediate at offset 64 bits" (all-isas)
h-sint DFLT f-dsp-64-s16
((parse "signed16")) () ()
)
(define-full-operand Imm1-S "signed 1 bit immediate for short format binary insns" (m32c-isa)
h-sint DFLT f-imm1-S
((parse "imm1_S")) () ()
)
(define-full-operand Imm3-S "signed 3 bit immediate for short format binary insns" (m32c-isa)
h-sint DFLT f-imm3-S
((parse "imm3_S")) () ()
)
(define-full-operand Bit3-S "3 bit bit number" (m32c-isa)
h-sint DFLT f-imm3-S
((parse "bit3_S")) () ()
)
;-------------------------------------------------------------
; Bit numbers
;-------------------------------------------------------------
(define-full-operand Bitno16R "bit number for indexing registers" (m16c-isa)
h-uint DFLT f-dsp-16-u8
((parse "Bitno16R")) () ()
)
(dnop Bitno32Prefixed "bit number for indexing objects" (m32c-isa) h-uint f-bitno32-prefixed)
(dnop Bitno32Unprefixed "bit number for indexing objects" (m32c-isa) h-uint f-bitno32-unprefixed)
(define-full-operand BitBase16-16-u8 "unsigned bit,base:8 at offset 16for m16c" (m16c-isa)
h-uint DFLT f-dsp-16-u8
((parse "unsigned_bitbase8") (print "unsigned_bitbase")) () ()
)
(define-full-operand BitBase16-16-s8 "signed bit,base:8 at offset 16for m16c" (m16c-isa)
h-sint DFLT f-dsp-16-s8
((parse "signed_bitbase8") (print "signed_bitbase")) () ()
)
(define-full-operand BitBase16-16-u16 "unsigned bit,base:16 at offset 16 for m16c" (m16c-isa)
h-uint DFLT f-dsp-16-u16
((parse "unsigned_bitbase16") (print "unsigned_bitbase")) () ()
)
(define-full-operand BitBase16-8-u11-S "signed bit,base:11 at offset 16 for m16c" (m16c-isa)
h-uint DFLT f-bitbase16-u11-S
((parse "unsigned_bitbase11") (print "unsigned_bitbase")) () ()
)
(define-full-operand BitBase32-16-u11-Unprefixed "unsigned bit,base:11 at offset 16 for m32c" (m32c-isa)
h-uint DFLT f-bitbase32-16-u11-unprefixed
((parse "unsigned_bitbase11") (print "unsigned_bitbase")) () ()
)
(define-full-operand BitBase32-16-s11-Unprefixed "signed bit,base:11 at offset 16 for m32c" (m32c-isa)
h-sint DFLT f-bitbase32-16-s11-unprefixed
((parse "signed_bitbase11") (print "signed_bitbase")) () ()
)
(define-full-operand BitBase32-16-u19-Unprefixed "unsigned bit,base:19 at offset 16 for m32c" (m32c-isa)
h-uint DFLT f-bitbase32-16-u19-unprefixed
((parse "unsigned_bitbase19") (print "unsigned_bitbase")) () ()
)
(define-full-operand BitBase32-16-s19-Unprefixed "signed bit,base:19 at offset 16 for m32c" (m32c-isa)
h-sint DFLT f-bitbase32-16-s19-unprefixed
((parse "signed_bitbase19") (print "signed_bitbase")) () ()
)
(define-full-operand BitBase32-16-u27-Unprefixed "unsigned bit,base:27 at offset 16 for m32c" (m32c-isa)
h-uint DFLT f-bitbase32-16-u27-unprefixed
((parse "unsigned_bitbase27") (print "unsigned_bitbase")) () ()
)
(define-full-operand BitBase32-24-u11-Prefixed "unsigned bit,base:11 at offset 24 for m32c" (m32c-isa)
h-uint DFLT f-bitbase32-24-u11-prefixed
((parse "unsigned_bitbase11") (print "unsigned_bitbase")) () ()
)
(define-full-operand BitBase32-24-s11-Prefixed "signed bit,base:11 at offset 24 for m32c" (m32c-isa)
h-sint DFLT f-bitbase32-24-s11-prefixed
((parse "signed_bitbase11") (print "signed_bitbase")) () ()
)
(define-full-operand BitBase32-24-u19-Prefixed "unsigned bit,base:19 at offset 24 for m32c" (m32c-isa)
h-uint DFLT f-bitbase32-24-u19-prefixed
((parse "unsigned_bitbase19") (print "unsigned_bitbase")) () ()
)
(define-full-operand BitBase32-24-s19-Prefixed "signed bit,base:19 at offset 24 for m32c" (m32c-isa)
h-sint DFLT f-bitbase32-24-s19-prefixed
((parse "signed_bitbase19") (print "signed_bitbase")) () ()
)
(define-full-operand BitBase32-24-u27-Prefixed "unsigned bit,base:27 at offset 24 for m32c" (m32c-isa)
h-uint DFLT f-bitbase32-24-u27-prefixed
((parse "unsigned_bitbase27") (print "unsigned_bitbase")) () ()
)
;-------------------------------------------------------------
; Labels
;-------------------------------------------------------------
(define-full-operand Lab-5-3 "3 bit label" (all-isas RELAX)
h-iaddr DFLT f-lab-5-3
((parse "lab_5_3")) () () )
(define-full-operand Lab32-jmp-s "3 bit label" (all-isas RELAX)
h-iaddr DFLT f-lab32-jmp-s
((parse "lab_5_3")) () () )
(dnop Lab-8-8 "8 bit label" (all-isas RELAX) h-iaddr f-lab-8-8)
(dnop Lab-8-16 "16 bit label" (all-isas RELAX) h-iaddr f-lab-8-16)
(dnop Lab-8-24 "24 bit label" (all-isas RELAX) h-iaddr f-lab-8-24)
(dnop Lab-16-8 "8 bit label" (all-isas RELAX) h-iaddr f-lab-16-8)
(dnop Lab-24-8 "8 bit label" (all-isas) h-iaddr f-lab-24-8)
(dnop Lab-32-8 "8 bit label" (all-isas) h-iaddr f-lab-32-8)
(dnop Lab-40-8 "8 bit label" (all-isas) h-iaddr f-lab-40-8)
;-------------------------------------------------------------
; Condition code bits
;-------------------------------------------------------------
(dnop sbit "negative bit" (SEM-ONLY all-isas) h-sbit f-nil)
(dnop obit "overflow bit" (SEM-ONLY all-isas) h-obit f-nil)
(dnop zbit "zero bit" (SEM-ONLY all-isas) h-zbit f-nil)
(dnop cbit "carry bit" (SEM-ONLY all-isas) h-cbit f-nil)
(dnop ubit "stack ptr select bit" (SEM-ONLY all-isas) h-ubit f-nil)
(dnop ibit "interrupt enable bit" (SEM-ONLY all-isas) h-ibit f-nil)
(dnop bbit "reg bank select bit" (SEM-ONLY all-isas) h-bbit f-nil)
(dnop dbit "debug bit" (SEM-ONLY all-isas) h-dbit f-nil)
;-------------------------------------------------------------
; Condition operands
;-------------------------------------------------------------
(define-pmacro (cond-operand mach offset)
(dnop (.sym cond mach - offset) "condition" ((.sym m mach c-isa)) (.sym h-cond mach) (.sym f-dsp- offset -u8))
)
(cond-operand 16 16)
(cond-operand 16 24)
(cond-operand 16 32)
(cond-operand 32 16)
(cond-operand 32 24)
(cond-operand 32 32)
(cond-operand 32 40)
(dnop cond16c "condition" (m16c-isa) h-cond16c f-cond16)
(dnop cond16j "condition" (m16c-isa) h-cond16j f-cond16)
(dnop cond16j5 "condition" (m16c-isa) h-cond16j-5 f-cond16j-5)
(dnop cond32 "condition" (m32c-isa) h-cond32 f-cond32)
(dnop cond32j "condition" (m32c-isa) h-cond32 f-cond32j)
(dnop sccond32 "scCND condition" (m32c-isa) h-cond32 f-cond16)
(dnop flags16 "flags" (m16c-isa) h-flags f-9-3)
(dnop flags32 "flags" (m32c-isa) h-flags f-13-3)
(dnop cr16 "control" (m16c-isa) h-cr-16 f-9-3)
(dnop cr1-Unprefixed-32 "control" (m32c-isa) h-cr1-32 f-13-3)
(dnop cr1-Prefixed-32 "control" (m32c-isa) h-cr1-32 f-21-3)
(dnop cr2-32 "control" (m32c-isa) h-cr2-32 f-13-3)
(dnop cr3-Unprefixed-32 "control" (m32c-isa) h-cr3-32 f-13-3)
(dnop cr3-Prefixed-32 "control" (m32c-isa) h-cr3-32 f-21-3)
;-------------------------------------------------------------
; Suffixes
;-------------------------------------------------------------
(define-full-operand Z "Suffix for zero format insns" (all-isas)
h-sint DFLT f-nil
((parse "Z") (print "Z")) () ()
)
(define-full-operand S "Suffix for short format insns" (all-isas)
h-sint DFLT f-nil
((parse "S") (print "S")) () ()
)
(define-full-operand Q "Suffix for quick format insns" (all-isas)
h-sint DFLT f-nil
((parse "Q") (print "Q")) () ()
)
(define-full-operand G "Suffix for general format insns" (all-isas)
h-sint DFLT f-nil
((parse "G") (print "G")) () ()
)
(define-full-operand X "Empty suffix" (all-isas)
h-sint DFLT f-nil
((parse "X") (print "X")) () ()
)
(define-full-operand size "any size specifier" (all-isas)
h-sint DFLT f-nil
((parse "size") (print "size")) () ()
)
;-------------------------------------------------------------
; Misc
;-------------------------------------------------------------
(dnop BitIndex "Bit Index for the next insn" (SEM-ONLY MACH32 m32c-isa) h-bit-index f-nil)
(dnop SrcIndex "Source Index for the next insn" (SEM-ONLY MACH32 m32c-isa) h-src-index f-nil)
(dnop DstIndex "Destination Index for the next insn" (SEM-ONLY MACH32 m32c-isa) h-dst-index f-nil)
(dnop NoRemainder "Place holder for when the remainder is not kept" (SEM-ONLY MACH32 m32c-isa) h-none f-nil)
;=============================================================
; Derived Operands
; Memory reference macros that clip addresses appropriately. Refer to
; memory at ADDRESS in MODE, clipped appropriately for either the m16c
; or m32c.
(define-pmacro (mem16 mode address)
(mem mode (and #xffff address)))
(define-pmacro (mem32 mode address)
(mem mode (and #xffffff address)))
; Like mem16 and mem32, but takes MACH as a parameter. MACH must be
; either 16 or 32.
(define-pmacro (mem-mach mach mode address)
((.sym mem mach) mode address))
;-------------------------------------------------------------
; Source
;-------------------------------------------------------------
; Rn direct
;-------------------------------------------------------------
(define-pmacro (src16-Rn-direct-operand xmode)
(begin
(define-derived-operand
(name (.sym src16-Rn-direct- xmode))
(comment (.str "m16c Rn direct source " xmode))
(attrs (machine 16))
(mode xmode)
(args ((.sym Src16Rn xmode)))
(syntax (.str "$Src16Rn" xmode))
(base-ifield f-8-4)
(encoding (+ (f-8-2 0) (.sym Src16Rn xmode)))
(ifield-assertion (eq f-8-2 0))
(getter (trunc xmode (.sym Src16Rn xmode)))
(setter (set (.sym Src16Rn xmode) newval))
)
)
)
(src16-Rn-direct-operand QI)
(src16-Rn-direct-operand HI)
(define-pmacro (src32-Rn-direct-operand group base xmode)
(begin
(define-derived-operand
(name (.sym src32-Rn-direct- group - xmode))
(comment (.str "m32c Rn direct source " xmode))
(attrs (machine 32))
(mode xmode)
(args ((.sym Src32Rn group xmode)))
(syntax (.str "$Src32Rn" group xmode))
(base-ifield (.sym f- base -11))
(encoding (+ ((.sym f- base -3) 4) (.sym Src32Rn group xmode)))
(ifield-assertion (eq (.sym f- base -3) 4))
(getter (trunc xmode (.sym Src32Rn group xmode)))
(setter (set (.sym Src32Rn group xmode) newval))
)
)
)
(src32-Rn-direct-operand Unprefixed 1 QI)
(src32-Rn-direct-operand Prefixed 9 QI)
(src32-Rn-direct-operand Unprefixed 1 HI)
(src32-Rn-direct-operand Prefixed 9 HI)
(src32-Rn-direct-operand Unprefixed 1 SI)
(src32-Rn-direct-operand Prefixed 9 SI)
;-------------------------------------------------------------
; An direct
;-------------------------------------------------------------
(define-pmacro (src16-An-direct-operand xmode)
(begin
(define-derived-operand
(name (.sym src16-An-direct- xmode))
(comment (.str "m16c An direct destination " xmode))
(attrs (machine 16))
(mode xmode)
(args ((.sym Src16An xmode)))
(syntax (.str "$Src16An" xmode))
(base-ifield f-8-4)
(encoding (+ (f-8-2 1) (f-10-1 0) (.sym Src16An xmode)))
(ifield-assertion (andif (eq f-8-2 1) (eq f-10-1 0)))
(getter (trunc xmode (.sym Src16An xmode)))
(setter (set (.sym Src16An xmode) newval))
)
)
)
(src16-An-direct-operand QI)
(src16-An-direct-operand HI)
(define-pmacro (src32-An-direct-operand group base1 base2 xmode)
(begin
(define-derived-operand
(name (.sym src32-An-direct- group - xmode))
(comment (.str "m32c An direct destination " xmode))
(attrs (machine 32))
(mode xmode)
(args ((.sym Src32An group xmode)))
(syntax (.str "$Src32An" group xmode))
(base-ifield (.sym f- base1 -11))
(encoding (+ ((.sym f- base1 -3) 0) ((.sym f- base2 -1) 1) (.sym Src32An group xmode)))
(ifield-assertion (andif (eq (.sym f- base1 -3) 0) (eq (.sym f- base2 -1) 1)))
(getter (trunc xmode (.sym Src32An group xmode)))
(setter (set (.sym Src32An group xmode) newval))
)
)
)
(src32-An-direct-operand Unprefixed 1 10 QI)
(src32-An-direct-operand Unprefixed 1 10 HI)
(src32-An-direct-operand Unprefixed 1 10 SI)
(src32-An-direct-operand Prefixed 9 18 QI)
(src32-An-direct-operand Prefixed 9 18 HI)
(src32-An-direct-operand Prefixed 9 18 SI)
;-------------------------------------------------------------
; An indirect
;-------------------------------------------------------------
(define-pmacro (src16-An-indirect-operand xmode)
(begin
(define-derived-operand
(name (.sym src16-An-indirect- xmode))
(comment (.str "m16c An indirect destination " xmode))
(attrs (machine 16))
(mode xmode)
(args (Src16An))
(syntax "[$Src16An]")
(base-ifield f-8-4)
(encoding (+ (f-8-2 1) (f-10-1 1) Src16An))
(ifield-assertion (andif (eq f-8-2 1) (eq f-10-1 1)))
(getter (mem16 xmode Src16An))
(setter (set (mem16 xmode Src16An) newval))
)
)
)
(src16-An-indirect-operand QI)
(src16-An-indirect-operand HI)
(define-pmacro (src32-An-indirect-operand group base1 base2 xmode)
(begin
(define-derived-operand
(name (.sym src32-An-indirect- group - xmode))
(comment (.str "m32c An indirect destination " xmode))
(attrs (machine 32))
(mode xmode)
(args ((.sym Src32An group)))
(syntax (.str "[$Src32An" group "]"))
(base-ifield (.sym f- base1 -11))
(encoding (+ ((.sym f- base1 -3) 0) ((.sym f- base2 -1) 0) (.sym Src32An group)))
(ifield-assertion (andif (eq (.sym f- base1 -3) 0) (eq (.sym f- base2 -1) 0)))
(getter (c-call xmode (.str "operand_getter_" xmode) (.sym Src32An group)
(const 0)))
(setter (c-call DFLT (.str "operand_setter_" xmode) newval
(.sym Src32An group) (const 0)))
; (getter (mem32 xmode (.sym Src32An group)))
; (setter (set (mem32 xmode (.sym Src32An group)) newval))
)
)
)
(src32-An-indirect-operand Unprefixed 1 10 QI)
(src32-An-indirect-operand Unprefixed 1 10 HI)
(src32-An-indirect-operand Unprefixed 1 10 SI)
(src32-An-indirect-operand Prefixed 9 18 QI)
(src32-An-indirect-operand Prefixed 9 18 HI)
(src32-An-indirect-operand Prefixed 9 18 SI)
;-------------------------------------------------------------
; dsp:d[r] relative
;-------------------------------------------------------------
(define-pmacro (src16-relative-operand xmode)
(begin
(define-derived-operand
(name (.sym src16-16-8-SB-relative- xmode))
(comment (.str "m16c dsp:8[sb] relative destination " xmode))
(attrs (machine 16))
(mode xmode)
(args (Dsp-16-u8))
(syntax "${Dsp-16-u8}[sb]")
(base-ifield f-8-4)
(encoding (+ (f-8-4 #xA) Dsp-16-u8))
(ifield-assertion (eq f-8-4 #xA))
(getter (mem16 xmode (add Dsp-16-u8 (reg h-sb))))
(setter (set (mem16 xmode (add Dsp-16-u8 (reg h-sb))) newval))
)
(define-derived-operand
(name (.sym src16-16-16-SB-relative- xmode))
(comment (.str "m16c dsp:16[sb] relative destination " xmode))
(attrs (machine 16))
(mode xmode)
(args (Dsp-16-u16))
(syntax "${Dsp-16-u16}[sb]")
(base-ifield f-8-4)
(encoding (+ (f-8-4 #xE) Dsp-16-u16))
(ifield-assertion (eq f-8-4 #xE))
(getter (mem16 xmode (add Dsp-16-u16 (reg h-sb))))
(setter (set (mem16 xmode (add Dsp-16-u16 (reg h-sb))) newval))
)
(define-derived-operand
(name (.sym src16-16-8-FB-relative- xmode))
(comment (.str "m16c dsp:8[fb] relative destination " xmode))
(attrs (machine 16))
(mode xmode)
(args (Dsp-16-s8))
(syntax "${Dsp-16-s8}[fb]")
(base-ifield f-8-4)
(encoding (+ (f-8-4 #xB) Dsp-16-s8))
(ifield-assertion (eq f-8-4 #xB))
(getter (mem16 xmode (add Dsp-16-s8 (reg h-fb))))
(setter (set (mem16 xmode (add Dsp-16-s8 (reg h-fb))) newval))
)
(define-derived-operand
(name (.sym src16-16-8-An-relative- xmode))
(comment (.str "m16c dsp:8[An] relative destination " xmode))
(attrs (machine 16))
(mode xmode)
(args (Src16An Dsp-16-u8))
(syntax "${Dsp-16-u8}[$Src16An]")
(base-ifield f-8-4)
(encoding (+ (f-8-2 2) (f-10-1 0) Dsp-16-u8 Src16An))
(ifield-assertion (andif (eq f-8-2 2) (eq f-10-1 0)))
(getter (mem16 xmode (add Dsp-16-u8 Src16An)))
(setter (set (mem16 xmode (add Dsp-16-u8 Src16An)) newval))
)
(define-derived-operand
(name (.sym src16-16-16-An-relative- xmode))
(comment (.str "m16c dsp:16[An] relative destination " xmode))
(attrs (machine 16))
(mode xmode)
(args (Src16An Dsp-16-u16))
(syntax "${Dsp-16-u16}[$Src16An]")
(base-ifield f-8-4)
(encoding (+ (f-8-2 3) (f-10-1 0) Dsp-16-u16 Src16An))
(ifield-assertion (andif (eq f-8-2 3) (eq f-10-1 0)))
(getter (mem16 xmode (add Dsp-16-u16 Src16An)))
(setter (set (mem16 xmode (add Dsp-16-u16 Src16An)) newval))
)
)
)
(src16-relative-operand QI)
(src16-relative-operand HI)
(define-pmacro (src32-relative-operand offset group base1 base2 xmode)
(begin
(define-derived-operand
(name (.sym src32- offset -8-SB-relative- group - xmode))
(comment (.str "m32c dsp:8[sb] relative destination " xmode))
(attrs (machine 32))
(mode xmode)
(args ((.sym Dsp- offset -u8)))
(syntax (.str "${Dsp-" offset "-u8}[sb]"))
(base-ifield (.sym f- base1 -11))
(encoding (+ ((.sym f- base1 -3) 1) ((.sym f- base2 -2) 2) (.sym Dsp- offset -u8)))
(ifield-assertion (andif (eq (.sym f- base1 -3) 1) (eq (.sym f- base2 -2) 2)))
(getter (c-call xmode (.str "operand_getter_" xmode) sb (.sym Dsp- offset -u8)))
(setter (c-call DFLT (.str "operand_setter_" xmode) newval sb (.sym Dsp- offset -u8)))
; (getter (mem32 xmode (add (.sym Dsp- offset -u8) (reg h-sb))))
; (setter (set (mem32 xmode (add (.sym Dsp- offset -u8) (reg h-sb))) newval))
)
(define-derived-operand
(name (.sym src32- offset -16-SB-relative- group - xmode))
(comment (.str "m32c dsp:16[sb] relative destination " xmode))
(attrs (machine 32))
(mode xmode)
(args ((.sym Dsp- offset -u16)))
(syntax (.str "${Dsp-" offset "-u16}[sb]"))
(base-ifield (.sym f- base1 -11))
(encoding (+ ((.sym f- base1 -3) 2) ((.sym f- base2 -2) 2) (.sym Dsp- offset -u16)))
(ifield-assertion (andif (eq (.sym f- base1 -3) 2) (eq (.sym f- base2 -2) 2)))
(getter (c-call xmode (.str "operand_getter_" xmode) sb (.sym Dsp- offset -u16)))
(setter (c-call DFLT (.str "operand_setter_" xmode) newval sb (.sym Dsp- offset -u16)))
; (getter (mem32 xmode (add (.sym Dsp- offset -u16) (reg h-sb))))
; (setter (set (mem32 xmode (add (.sym Dsp- offset -u16) (reg h-sb))) newval))
)
(define-derived-operand
(name (.sym src32- offset -8-FB-relative- group - xmode))
(comment (.str "m32c dsp:8[fb] relative destination " xmode))
(attrs (machine 32))
(mode xmode)
(args ((.sym Dsp- offset -s8)))
(syntax (.str "${Dsp-" offset "-s8}[fb]"))
(base-ifield (.sym f- base1 -11))
(encoding (+ ((.sym f- base1 -3) 1) ((.sym f- base2 -2) 3) (.sym Dsp- offset -s8)))
(ifield-assertion (andif (eq (.sym f- base1 -3) 1) (eq (.sym f- base2 -2) 3)))
(getter (c-call xmode (.str "operand_getter_" xmode) fb (.sym Dsp- offset -s8)))
(setter (c-call DFLT (.str "operand_setter_" xmode) newval fb (.sym Dsp- offset -s8)))
; (getter (mem32 xmode (add (.sym Dsp- offset -s8) (reg h-fb))))
; (setter (set (mem32 xmode (add (.sym Dsp- offset -s8) (reg h-fb))) newval))
)
(define-derived-operand
(name (.sym src32- offset -16-FB-relative- group - xmode))
(comment (.str "m32c dsp:16[fb] relative destination " xmode))
(attrs (machine 32))
(mode xmode)
(args ((.sym Dsp- offset -s16)))
(syntax (.str "${Dsp-" offset "-s16}[fb]"))
(base-ifield (.sym f- base1 -11))
(encoding (+ ((.sym f- base1 -3) 2) ((.sym f- base2 -2) 3) (.sym Dsp- offset -s16)))
(ifield-assertion (andif (eq (.sym f- base1 -3) 2) (eq (.sym f- base2 -2) 3)))
(getter (c-call xmode (.str "operand_getter_" xmode) fb (.sym Dsp- offset -s16)))
(setter (c-call DFLT (.str "operand_setter_" xmode) newval fb (.sym Dsp- offset -s16)))
; (getter (mem32 xmode (add (.sym Dsp- offset -s16) (reg h-fb))))
; (setter (set (mem32 xmode (add (.sym Dsp- offset -s16) (reg h-fb))) newval))
)
(define-derived-operand
(name (.sym src32- offset -8-An-relative- group - xmode))
(comment (.str "m32c dsp:8[An] relative destination " xmode))
(attrs (machine 32))
(mode xmode)
(args ((.sym Src32An group) (.sym Dsp- offset -u8)))
(syntax (.str "${Dsp-" offset "-u8}[$Src32An" group "]"))
(base-ifield (.sym f- base1 -11))
(encoding (+ ((.sym f- base1 -3) 1) ((.sym f- base2 -1) 0) (.sym Dsp- offset -u8) (.sym Src32An group)))
(ifield-assertion (andif (eq (.sym f- base1 -3) 1) (eq (.sym f- base2 -1) 0)))
(getter (c-call xmode (.str "operand_getter_" xmode) (.sym Src32An group) (.sym Dsp- offset -u8)))
(setter (c-call DFLT (.str "operand_setter_" xmode) newval (.sym Src32An group) (.sym Dsp- offset -u8)))
; (getter (mem32 xmode (add (.sym Dsp- offset -u8) (.sym Src32An group))))
; (setter (set (mem32 xmode (add (.sym Dsp- offset -u8) (.sym Src32An group))) newval))
)
(define-derived-operand
(name (.sym src32- offset -16-An-relative- group - xmode))
(comment (.str "m32c dsp:16[An] relative destination " xmode))
(attrs (machine 32))
(mode xmode)
(args ((.sym Src32An group) (.sym Dsp- offset -u16)))
(syntax (.str "${Dsp-" offset "-u16}[$Src32An" group "]"))
(base-ifield (.sym f- base1 -11))
(encoding (+ ((.sym f- base1 -3) 2) ((.sym f- base2 -1) 0) (.sym Dsp- offset -u16) (.sym Src32An group)))
(ifield-assertion (andif (eq (.sym f- base1 -3) 2) (eq (.sym f- base2 -1) 0)))
(getter (c-call xmode (.str "operand_getter_" xmode) (.sym Src32An group) (.sym Dsp- offset -u16)))
(setter (c-call DFLT (.str "operand_setter_" xmode) newval (.sym Src32An group) (.sym Dsp- offset -u16)))
; (getter (mem32 xmode (add (.sym Dsp- offset -u16) (.sym Src32An group))))
; (setter (set (mem32 xmode (add (.sym Dsp- offset -u16) (.sym Src32An group))) newval))
)
(define-derived-operand
(name (.sym src32- offset -24-An-relative- group - xmode))
(comment (.str "m32c dsp:16[An] relative destination " xmode))
(attrs (machine 32))
(mode xmode)
(args ((.sym Src32An group) (.sym Dsp- offset -u24)))
(syntax (.str "${Dsp-" offset "-u24}[$Src32An" group "]"))
(base-ifield (.sym f- base1 -11))
(encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -1) 0) (.sym Dsp- offset -u24) (.sym Src32An group)))
(ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -1) 0)))
(getter (c-call xmode (.str "operand_getter_" xmode) (.sym Src32An group) (.sym Dsp- offset -u24) ))
(setter (c-call DFLT (.str "operand_setter_" xmode) newval (.sym Src32An group) (.sym Dsp- offset -u24)))
; (getter (mem32 xmode (add (.sym Dsp- offset -u24) (.sym Src32An group))))
; (setter (set (mem32 xmode (add (.sym Dsp- offset -u24) (.sym Src32An group))) newval))
)
)
)
(src32-relative-operand 16 Unprefixed 1 10 QI)
(src32-relative-operand 16 Unprefixed 1 10 HI)
(src32-relative-operand 16 Unprefixed 1 10 SI)
(src32-relative-operand 24 Prefixed 9 18 QI)
(src32-relative-operand 24 Prefixed 9 18 HI)
(src32-relative-operand 24 Prefixed 9 18 SI)
;-------------------------------------------------------------
; Absolute address
;-------------------------------------------------------------
(define-pmacro (src16-absolute xmode)
(begin
(define-derived-operand
(name (.sym src16-16-16-absolute- xmode))
(comment (.str "m16c absolute address " xmode))
(attrs (machine 16))
(mode xmode)
(args (Dsp-16-u16))
(syntax (.str "${Dsp-16-u16}"))
(base-ifield f-8-4)
(encoding (+ (f-8-4 #xF) Dsp-16-u16))
(ifield-assertion (eq f-8-4 #xF))
(getter (mem16 xmode Dsp-16-u16))
(setter (set (mem16 xmode Dsp-16-u16) newval))
)
)
)
(src16-absolute QI)
(src16-absolute HI)
(define-pmacro (src32-absolute offset group base1 base2 xmode)
(begin
(define-derived-operand
(name (.sym src32- offset -16-absolute- group - xmode))
(comment (.str "m32c absolute address " xmode))
(attrs (machine 32))
(mode xmode)
(args ((.sym Dsp- offset -u16)))
(syntax (.str "${Dsp-" offset "-u16}"))
(base-ifield (.sym f- base1 -11))
(encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -2) 3) (.sym Dsp- offset -u16)))
(ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -2) 3)))
(getter (c-call xmode (.str "operand_getter_" xmode) (const 0) (.sym Dsp- offset -u16)))
(setter (c-call DFLT (.str "operand_setter_" xmode) newval (const 0) (.sym Dsp- offset -u16)))
; (getter (mem32 xmode (.sym Dsp- offset -u16)))
; (setter (set (mem32 xmode (.sym Dsp- offset -u16)) newval))
)
(define-derived-operand
(name (.sym src32- offset -24-absolute- group - xmode))
(comment (.str "m32c absolute address " xmode))
(attrs (machine 32))
(mode xmode)
(args ((.sym Dsp- offset -u24)))
(syntax (.str "${Dsp-" offset "-u24}"))
(base-ifield (.sym f- base1 -11))
(encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -2) 2) (.sym Dsp- offset -u24)))
(ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -2) 2)))
(getter (c-call xmode (.str "operand_getter_" xmode) (const 0) (.sym Dsp- offset -u24)))
(setter (c-call DFLT (.str "operand_setter_" xmode) newval (const 0) (.sym Dsp- offset -u24)))
; (getter (mem32 xmode (.sym Dsp- offset -u24)))
; (setter (set (mem32 xmode (.sym Dsp- offset -u24)) newval))
)
)
)
(src32-absolute 16 Unprefixed 1 10 QI)
(src32-absolute 16 Unprefixed 1 10 HI)
(src32-absolute 16 Unprefixed 1 10 SI)
(src32-absolute 24 Prefixed 9 18 QI)
(src32-absolute 24 Prefixed 9 18 HI)
(src32-absolute 24 Prefixed 9 18 SI)
;-------------------------------------------------------------
; An indirect indirect
;
; Double indirect addressing uses the lower 3 bytes of the value stored
; at the address referenced by 'op' as the effective address.
;-------------------------------------------------------------
(define-pmacro (indirect-addr op) (and USI (mem32 USI op) #x00ffffff))
; (define-pmacro (src-An-indirect-indirect-operand xmode)
; (define-derived-operand
; (name (.sym src32-An-indirect-indirect- xmode))
; (comment (.str "m32c An indirect indirect destination " xmode))
; (attrs (machine 32))
; (mode xmode)
; (args (Src32AnPrefixed))
; (syntax (.str "[[$Src32AnPrefixed]]"))
; (base-ifield f-9-11)
; (encoding (+ (f-9-3 0) (f-18-1 0) Src32AnPrefixed))
; (ifield-assertion (andif (eq f-9-3 0) (eq f-18-1 0)))
; (getter (mem32 xmode (indirect-addr Src32AnPrefixed)))
; (setter (set (mem32 xmode (indirect-addr Src32AnPrefixed)) newval))
; )
; )
; (src-An-indirect-indirect-operand QI)
; (src-An-indirect-indirect-operand HI)
; (src-An-indirect-indirect-operand SI)
;-------------------------------------------------------------
; Relative indirect
;-------------------------------------------------------------
(define-pmacro (src-relative-indirect-operand xmode)
(begin
; (define-derived-operand
; (name (.sym src32-24-8-SB-relative-indirect- xmode))
; (comment (.str "m32c dsp:8[sb] relative source " xmode))
; (attrs (machine 32))
; (mode xmode)
; (args (Dsp-24-u8))
; (syntax "[${Dsp-24-u8}[sb]]")
; (base-ifield f-9-11)
; (encoding (+ (f-9-3 1) (f-18-2 2) Dsp-24-u8))
; (ifield-assertion (andif (eq f-9-3 1) (eq f-18-2 2)))
; (getter (mem32 xmode (indirect-addr (add Dsp-24-u8 (reg h-sb)))))
; (setter (set (mem32 xmode (indirect-addr (add Dsp-24-u8 (reg h-sb)))) newval))
; )
; (define-derived-operand
; (name (.sym src32-24-16-SB-relative-indirect- xmode))
; (comment (.str "m32c dsp:16[sb] relative source " xmode))
; (attrs (machine 32))
; (mode xmode)
; (args (Dsp-24-u16))
; (syntax "[${Dsp-24-u16}[sb]]")
; (base-ifield f-9-11)
; (encoding (+ (f-9-3 2) (f-18-2 2) Dsp-24-u16))
; (ifield-assertion (andif (eq f-9-3 2) (eq f-18-2 2)))
; (getter (mem32 xmode (indirect-addr (add Dsp-24-u16 (reg h-sb)))))
; (setter (set (mem32 xmode (indirect-addr (add Dsp-24-u16 (reg h-sb)))) newval))
; )
; (define-derived-operand
; (name (.sym src32-24-8-FB-relative-indirect- xmode))
; (comment (.str "m32c dsp:8[fb] relative source " xmode))
; (attrs (machine 32))
; (mode xmode)
; (args (Dsp-24-s8))
; (syntax "[${Dsp-24-s8}[fb]]")
; (base-ifield f-9-11)
; (encoding (+ (f-9-3 1) (f-18-2 3) Dsp-24-s8))
; (ifield-assertion (andif (eq f-9-3 1) (eq f-18-2 3)))
; (getter (mem32 xmode (indirect-addr (add Dsp-24-s8 (reg h-fb)))))
; (setter (set (mem32 xmode (indirect-addr (add Dsp-24-s8 (reg h-fb)))) newval))
; )
; (define-derived-operand
; (name (.sym src32-24-16-FB-relative-indirect- xmode))
; (comment (.str "m32c dsp:16[fb] relative source " xmode))
; (attrs (machine 32))
; (mode xmode)
; (args (Dsp-24-s16))
; (syntax "[${Dsp-24-s16}[fb]]")
; (base-ifield f-9-11)
; (encoding (+ (f-9-3 2) (f-18-2 3) Dsp-24-s16))
; (ifield-assertion (andif (eq f-9-3 2) (eq f-18-2 3)))
; (getter (mem32 xmode (indirect-addr (add Dsp-24-s16 (reg h-fb)))))
; (setter (set (mem32 xmode (indirect-addr (add Dsp-24-s16 (reg h-fb)))) newval))
; )
; (define-derived-operand
; (name (.sym src32-24-8-An-relative-indirect- xmode))
; (comment (.str "m32c dsp:8[An] relative indirect source " xmode))
; (attrs (machine 32))
; (mode xmode)
; (args (Src32AnPrefixed Dsp-24-u8))
; (syntax "[${Dsp-24-u8}[$Src32AnPrefixed]]")
; (base-ifield f-9-11)
; (encoding (+ (f-9-3 1) (f-18-1 0) Dsp-24-u8 Src32AnPrefixed))
; (ifield-assertion (andif (eq f-9-3 1) (eq f-18-1 0)))
; (getter (mem32 xmode (indirect-addr (add Dsp-24-u8 Src32AnPrefixed))))
; (setter (set (mem32 xmode (indirect-addr (add Dsp-24-u8 Src32AnPrefixed))) newval))
; )
; (define-derived-operand
; (name (.sym src32-24-16-An-relative-indirect- xmode))
; (comment (.str "m32c dsp:16[An] relative source " xmode))
; (attrs (machine 32))
; (mode xmode)
; (args (Src32AnPrefixed Dsp-24-u16))
; (syntax "[${Dsp-24-u16}[$Src32AnPrefixed]]")
; (base-ifield f-9-11)
; (encoding (+ (f-9-3 2) (f-18-1 0) Dsp-24-u16 Src32AnPrefixed))
; (ifield-assertion (andif (eq f-9-3 2) (eq f-18-1 0)))
; (getter (mem32 xmode (indirect-addr (add Dsp-24-u16 Src32AnPrefixed))))
; (setter (set (mem32 xmode (indirect-addr (add Dsp-24-u16 Src32AnPrefixed))) newval))
; )
; (define-derived-operand
; (name (.sym src32-24-24-An-relative-indirect- xmode))
; (comment (.str "m32c dsp:24[An] relative source " xmode))
; (attrs (machine 32))
; (mode xmode)
; (args (Src32AnPrefixed Dsp-24-u24))
; (syntax "[${Dsp-24-u24}[$Src32AnPrefixed]]")
; (base-ifield f-9-11)
; (encoding (+ (f-9-3 3) (f-18-1 0) Dsp-24-u24 Src32AnPrefixed))
; (ifield-assertion (andif (eq f-9-3 3) (eq f-18-1 0)))
; (getter (mem32 xmode (indirect-addr (add Dsp-24-u24 Src32AnPrefixed))))
; (setter (set (mem32 xmode (indirect-addr (add Dsp-24-u24 Src32AnPrefixed))) newval))
; )
)
)
; (src-relative-indirect-operand QI)
; (src-relative-indirect-operand HI)
; (src-relative-indirect-operand SI)
;-------------------------------------------------------------
; Absolute Indirect address
;-------------------------------------------------------------
(define-pmacro (src32-absolute-indirect offset base1 base2 xmode)
(begin
; (define-derived-operand
; (name (.sym src32- offset -16-absolute-indirect-derived- xmode))
; (comment (.str "m32c absolute indirect address " xmode))
; (attrs (machine 32))
; (mode xmode)
; (args ((.sym Dsp- offset -u16)))
; (syntax (.str "[${Dsp-" offset "-u16}]"))
; (base-ifield (.sym f- base1 -11))
; (encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -2) 3) (.sym Dsp- offset -u16)))
; (ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -2) 3)))
; (getter (mem32 xmode (indirect-addr (.sym Dsp- offset -u16))))
; (setter (set (mem32 xmode (indirect-addr (.sym Dsp- offset -u16))) newval))
; )
; (define-derived-operand
; (name (.sym src32- offset -24-absolute-indirect-derived- xmode))
; (comment (.str "m32c absolute indirect address " xmode))
; (attrs (machine 32))
; (mode xmode)
; (args ((.sym Dsp- offset -u24)))
; (syntax (.str "[${Dsp-" offset "-u24}]"))
; (base-ifield (.sym f- base1 -11))
; (encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -2) 2) (.sym Dsp- offset -u24)))
; (ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -2) 2)))
; (getter (mem32 xmode (indirect-addr (.sym Dsp- offset -u24))))
; (setter (set (mem32 xmode (indirect-addr (.sym Dsp- offset -u24))) newval))
; )
)
)
(src32-absolute-indirect 24 9 18 QI)
(src32-absolute-indirect 24 9 18 HI)
(src32-absolute-indirect 24 9 18 SI)
;-------------------------------------------------------------
; Register relative source operands for short format insns
;-------------------------------------------------------------
(define-pmacro (src-2-S-operands mach xmode base opc1 opc2 opc3)
(begin
(define-derived-operand
(name (.sym src mach -2-S-8-SB-relative- xmode))
(comment (.str "m" mach "c SB relative address"))
(attrs (machine mach))
(mode xmode)
(args (Dsp-8-u8))
(syntax "${Dsp-8-u8}[sb]")
(base-ifield (.sym f- base -2))
(encoding (+ ((.sym f- base -2) opc1) Dsp-8-u8))
(ifield-assertion (eq (.sym f- base -2) opc1))
(getter (c-call xmode (.str "operand_getter_" xmode) sb Dsp-8-u8))
(setter (c-call DFLT (.str "operand_setter_" xmode) newval sb Dsp-8-u8))
; (getter (mem-mach mach xmode (indirect-addr (add (reg h-sb) Dsp-8-u8))))
; (setter (set (mem-mach mach xmode (indirect-addr (add (reg h-sb) Dsp-8-u8))) newval))
)
(define-derived-operand
(name (.sym src mach -2-S-8-FB-relative- xmode))
(comment (.str "m" mach "c FB relative address"))
(attrs (machine mach))
(mode xmode)
(args (Dsp-8-s8))
(syntax "${Dsp-8-s8}[fb]")
(base-ifield (.sym f- base -2))
(encoding (+ ((.sym f- base -2) opc2) Dsp-8-s8))
(ifield-assertion (eq (.sym f- base -2) opc2))
(getter (c-call xmode (.str "operand_getter_" xmode) fb Dsp-8-s8))
(setter (c-call DFLT (.str "operand_setter_" xmode) newval fb Dsp-8-s8))
; (getter (mem-mach mach xmode (indirect-addr (add (reg h-fb) Dsp-8-s8))))
; (setter (set (mem-mach mach xmode (indirect-addr (add (reg h-fb) Dsp-8-s8))) newval))
)
(define-derived-operand
(name (.sym src mach -2-S-16-absolute- xmode))
(comment (.str "m" mach "c absolute address"))
(attrs (machine mach))
(mode xmode)
(args (Dsp-8-u16))
(syntax "${Dsp-8-u16}")
(base-ifield (.sym f- base -2))
(encoding (+ ((.sym f- base -2) opc3) Dsp-8-u16))
(ifield-assertion (eq (.sym f- base -2) opc3))
(getter (c-call xmode (.str "operand_getter_" xmode) (const 0) Dsp-8-u16))
(setter (c-call DFLT (.str "operand_setter_" xmode) newval (const 0) Dsp-8-u16))
; (getter (mem-mach mach xmode Dsp-8-u16))
; (setter (set (mem-mach mach xmode Dsp-8-u16) newval))
)
)
)
(src-2-S-operands 16 QI 6 1 2 3)
(src-2-S-operands 32 QI 2 2 3 1)
(src-2-S-operands 32 HI 2 2 3 1)
;=============================================================
; Derived Operands
;-------------------------------------------------------------
; Destination
;-------------------------------------------------------------
; Rn direct
;-------------------------------------------------------------
(define-pmacro (dst16-Rn-direct-operand xmode)
(begin
(define-derived-operand
(name (.sym dst16-Rn-direct- xmode))
(comment (.str "m16c Rn direct destination " xmode))
(attrs (machine 16))
(mode xmode)
(args ((.sym Dst16Rn xmode)))
(syntax (.str "$Dst16Rn" xmode))
(base-ifield f-12-4)
(encoding (+ (f-12-2 0) (.sym Dst16Rn xmode)))
(ifield-assertion (eq f-12-2 0))
(getter (trunc xmode (.sym Dst16Rn xmode)))
(setter (set (.sym Dst16Rn xmode) newval))
)
)
)
(dst16-Rn-direct-operand QI)
(dst16-Rn-direct-operand HI)
(dst16-Rn-direct-operand SI)
(define-derived-operand
(name dst16-Rn-direct-Ext-QI)
(comment "m16c Rn direct destination QI")
(attrs (machine 16))
(mode HI)
(args (Dst16RnExtQI))
(syntax "$Dst16RnExtQI")
(base-ifield f-12-4)
(encoding (+ (f-12-2 0) Dst16RnExtQI (f-15-1 0)))
(ifield-assertion (andif (eq f-12-2 0) (eq f-15-1 0)))
(getter (trunc QI (.sym Dst16RnExtQI)))
(setter (set Dst16RnExtQI newval))
)
(define-pmacro (dst32-Rn-direct-operand group base xmode)
(begin
(define-derived-operand
(name (.sym dst32-Rn-direct- group - xmode))
(comment (.str "m32c Rn direct destination " xmode))
(attrs (machine 32))
(mode xmode)
(args ((.sym Dst32Rn group xmode)))
(syntax (.str "$Dst32Rn" group xmode))
(base-ifield (.sym f- base -6))
(encoding (+ ((.sym f- base -3) 4) (.sym Dst32Rn group xmode)))
(ifield-assertion (eq (.sym f- base -3) 4))
(getter (trunc xmode (.sym Dst32Rn group xmode)))
(setter (set (.sym Dst32Rn group xmode) newval))
)
)
)
(dst32-Rn-direct-operand Unprefixed 4 QI)
(dst32-Rn-direct-operand Prefixed 12 QI)
(dst32-Rn-direct-operand Unprefixed 4 HI)
(dst32-Rn-direct-operand Prefixed 12 HI)
(dst32-Rn-direct-operand Unprefixed 4 SI)
(dst32-Rn-direct-operand Prefixed 12 SI)
(define-pmacro (dst32-Rn-direct-Ext-operand group base1 base2 smode dmode)
(begin
(define-derived-operand
(name (.sym dst32-Rn-direct- group - smode))
(comment (.str "m32c Rn direct destination " smode))
(attrs (machine 32))
(mode dmode)
(args ((.sym Dst32Rn group smode)))
(syntax (.str "$Dst32Rn" group smode))
(base-ifield (.sym f- base1 -6))
(encoding (+ ((.sym f- base1 -3) 4) ((.sym f- base2 -1) 1) (.sym Dst32Rn group smode)))
(ifield-assertion (andif (eq (.sym f- base1 -3) 4) (eq (.sym f- base2 -1) 1)))
(getter (trunc smode (.sym Dst32Rn group smode)))
(setter (set (.sym Dst32Rn group smode) newval))
)
)
)
(dst32-Rn-direct-Ext-operand ExtUnprefixed 4 8 QI HI)
(dst32-Rn-direct-Ext-operand ExtUnprefixed 4 8 HI SI)
(define-derived-operand
(name dst32-R3-direct-Unprefixed-HI)
(comment "m32c R3 direct HI")
(attrs (machine 32))
(mode HI)
(args (R3))
(syntax "$R3")
(base-ifield f-4-6)
(encoding (+ (f-4-3 4) (f-8-2 #x1)))
(ifield-assertion (andif (eq f-4-3 4) (eq f-8-2 #x1)))
(getter (trunc HI R3))
(setter (set R3 newval))
)
;-------------------------------------------------------------
; An direct
;-------------------------------------------------------------
(define-pmacro (dst16-An-direct-operand xmode)
(begin
(define-derived-operand
(name (.sym dst16-An-direct- xmode))
(comment (.str "m16c An direct destination " xmode))
(attrs (machine 16))
(mode xmode)
(args ((.sym Dst16An xmode)))
(syntax (.str "$Dst16An" xmode))
(base-ifield f-12-4)
(encoding (+ (f-12-2 1) (f-14-1 0) (.sym Dst16An xmode)))
(ifield-assertion (andif (eq f-12-2 1) (eq f-14-1 0)))
(getter (trunc xmode (.sym Dst16An xmode)))
(setter (set (.sym Dst16An xmode) newval))
)
)
)
(dst16-An-direct-operand QI)
(dst16-An-direct-operand HI)
(dst16-An-direct-operand SI)
(define-pmacro (dst32-An-direct-operand group base1 base2 xmode)
(begin
(define-derived-operand
(name (.sym dst32-An-direct- group - xmode))
(comment (.str "m32c An direct destination " xmode))
(attrs (machine 32))
(mode xmode)
(args ((.sym Dst32An group xmode)))
(syntax (.str "$Dst32An" group xmode))
(base-ifield (.sym f- base1 -6))
(encoding (+ ((.sym f- base1 -3) 0) ((.sym f- base2 -1) 1) (.sym Dst32An group xmode)))
(ifield-assertion (andif (eq (.sym f- base1 -3) 0) (eq (.sym f- base2 -1) 1)))
(getter (trunc xmode (.sym Dst32An group xmode)))
(setter (set (.sym Dst32An group xmode) newval))
)
)
)
(dst32-An-direct-operand Unprefixed 4 8 QI)
(dst32-An-direct-operand Prefixed 12 16 QI)
(dst32-An-direct-operand Unprefixed 4 8 HI)
(dst32-An-direct-operand Prefixed 12 16 HI)
(dst32-An-direct-operand Unprefixed 4 8 SI)
(dst32-An-direct-operand Prefixed 12 16 SI)
;-------------------------------------------------------------
; An indirect
;-------------------------------------------------------------
(define-pmacro (dst16-An-indirect-operand xmode)
(begin
(define-derived-operand
(name (.sym dst16-An-indirect- xmode))
(comment (.str "m16c An indirect destination " xmode))
(attrs (machine 16))
(mode xmode)
(args (Dst16An))
(syntax "[$Dst16An]")
(base-ifield f-12-4)
(encoding (+ (f-12-2 1) (f-14-1 1) Dst16An))
(ifield-assertion (andif (eq f-12-2 1) (eq f-14-1 1)))
(getter (mem16 xmode Dst16An))
(setter (set (mem16 xmode Dst16An) newval))
)
)
)
(dst16-An-indirect-operand QI)
(dst16-An-indirect-operand HI)
(dst16-An-indirect-operand SI)
(define-derived-operand
(name dst16-An-indirect-Ext-QI)
(comment "m16c An indirect destination QI")
(attrs (machine 16))
(mode HI)
(args (Dst16An))
(syntax "[$Dst16An]")
(base-ifield f-12-4)
(encoding (+ (f-12-2 1) (f-14-1 1) Dst16An))
(ifield-assertion (andif (eq f-12-2 1) (eq f-14-1 1)))
(getter (mem16 QI Dst16An))
(setter (set (mem16 HI Dst16An) newval))
)
(define-pmacro (dst32-An-indirect-operand group base1 base2 smode dmode)
(begin
(define-derived-operand
(name (.sym dst32-An-indirect- group - smode))
(comment (.str "m32c An indirect destination " smode))
(attrs (machine 32))
(mode dmode)
(args ((.sym Dst32An group)))
(syntax (.str "[$Dst32An" group "]"))
(base-ifield (.sym f- base1 -6))
(encoding (+ ((.sym f- base1 -3) 0) ((.sym f- base2 -1) 0) (.sym Dst32An group)))
(ifield-assertion (andif (eq (.sym f- base1 -3) 0) (eq (.sym f- base2 -1) 0)))
(getter (c-call dmode (.str "operand_getter_" dmode) (.sym Dst32An group)
(const 0)))
(setter (c-call DFLT (.str "operand_setter_" dmode) newval
(.sym Dst32An group) (const 0)))
; (getter (mem32 smode (.sym Dst32An group)))
; (setter (set (mem32 dmode (.sym Dst32An group)) newval))
)
)
)
(dst32-An-indirect-operand Unprefixed 4 8 QI QI)
(dst32-An-indirect-operand Prefixed 12 16 QI QI)
(dst32-An-indirect-operand Unprefixed 4 8 HI HI)
(dst32-An-indirect-operand Prefixed 12 16 HI HI)
(dst32-An-indirect-operand Unprefixed 4 8 SI SI)
(dst32-An-indirect-operand Prefixed 12 16 SI SI)
(dst32-An-indirect-operand ExtUnprefixed 4 8 QI HI)
(dst32-An-indirect-operand ExtUnprefixed 4 8 HI SI)
;-------------------------------------------------------------
; dsp:d[r] relative
;-------------------------------------------------------------
(define-pmacro (dst16-relative-operand offset xmode)
(begin
(define-derived-operand
(name (.sym dst16- offset -8-SB-relative- xmode))
(comment (.str "m16c dsp:8[sb] relative destination " xmode))
(attrs (machine 16))
(mode xmode)
(args ((.sym Dsp- offset -u8)))
(syntax (.str "${Dsp-" offset "-u8}[sb]"))
(base-ifield f-12-4)
(encoding (+ (f-12-4 #xA) (.sym Dsp- offset -u8)))
(ifield-assertion (eq f-12-4 #xA))
(getter (mem16 xmode (add (.sym Dsp- offset -u8) (reg h-sb))))
(setter (set (mem16 xmode (add (.sym Dsp- offset -u8) (reg h-sb))) newval))
)
(define-derived-operand
(name (.sym dst16- offset -16-SB-relative- xmode))
(comment (.str "m16c dsp:16[sb] relative destination " xmode))
(attrs (machine 16))
(mode xmode)
(args ((.sym Dsp- offset -u16)))
(syntax (.str "${Dsp-" offset "-u16}[sb]"))
(base-ifield f-12-4)
(encoding (+ (f-12-4 #xE) (.sym Dsp- offset -u16)))
(ifield-assertion (eq f-12-4 #xE))
(getter (mem16 xmode (add (.sym Dsp- offset -u16) (reg h-sb))))
(setter (set (mem16 xmode (add (.sym Dsp- offset -u16) (reg h-sb))) newval))
)
(define-derived-operand
(name (.sym dst16- offset -8-FB-relative- xmode))
(comment (.str "m16c dsp:8[fb] relative destination " xmode))
(attrs (machine 16))
(mode xmode)
(args ((.sym Dsp- offset -s8)))
(syntax (.str "${Dsp-" offset "-s8}[fb]"))
(base-ifield f-12-4)
(encoding (+ (f-12-4 #xB) (.sym Dsp- offset -s8)))
(ifield-assertion (eq f-12-4 #xB))
(getter (mem16 xmode (add (.sym Dsp- offset -s8) (reg h-fb))))
(setter (set (mem16 xmode (add (.sym Dsp- offset -s8) (reg h-fb))) newval))
)
(define-derived-operand
(name (.sym dst16- offset -8-An-relative- xmode))
(comment (.str "m16c dsp:8[An] relative destination " xmode))
(attrs (machine 16))
(mode xmode)
(args (Dst16An (.sym Dsp- offset -u8)))
(syntax (.str "${Dsp-" offset "-u8}[$Dst16An]"))
(base-ifield f-12-4)
(encoding (+ (f-12-2 2) (f-14-1 0) (.sym Dsp- offset -u8) Dst16An))
(ifield-assertion (andif (eq f-12-2 2) (eq f-14-1 0)))
(getter (mem16 xmode (add (.sym Dsp- offset -u8) Dst16An)))
(setter (set (mem16 xmode (add (.sym Dsp- offset -u8) Dst16An)) newval))
)
(define-derived-operand
(name (.sym dst16- offset -16-An-relative- xmode))
(comment (.str "m16c dsp:16[An] relative destination " xmode))
(attrs (machine 16))
(mode xmode)
(args (Dst16An (.sym Dsp- offset -u16)))
(syntax (.str "${Dsp-" offset "-u16}[$Dst16An]"))
(base-ifield f-12-4)
(encoding (+ (f-12-2 3) (f-14-1 0) (.sym Dsp- offset -u16) Dst16An))
(ifield-assertion (andif (eq f-12-2 3) (eq f-14-1 0)))
(getter (mem16 xmode (add (.sym Dsp- offset -u16) Dst16An)))
(setter (set (mem16 xmode (add (.sym Dsp- offset -u16) Dst16An)) newval))
)
)
)
(dst16-relative-operand 16 QI)
(dst16-relative-operand 24 QI)
(dst16-relative-operand 32 QI)
(dst16-relative-operand 40 QI)
(dst16-relative-operand 48 QI)
(dst16-relative-operand 16 HI)
(dst16-relative-operand 24 HI)
(dst16-relative-operand 32 HI)
(dst16-relative-operand 40 HI)
(dst16-relative-operand 48 HI)
(dst16-relative-operand 16 SI)
(dst16-relative-operand 24 SI)
(dst16-relative-operand 32 SI)
(dst16-relative-operand 40 SI)
(dst16-relative-operand 48 SI)
(define-pmacro (dst16-relative-Ext-operand offset smode dmode)
(begin
(define-derived-operand
(name (.sym dst16- offset -8-SB-relative-Ext- smode))
(comment (.str "m16c dsp:8[sb] relative destination " smode))
(attrs (machine 16))
(mode dmode)
(args ((.sym Dsp- offset -u8)))
(syntax (.str "${Dsp-" offset "-u8}[sb]"))
(base-ifield f-12-4)
(encoding (+ (f-12-4 #xA) (.sym Dsp- offset -u8)))
(ifield-assertion (eq f-12-4 #xA))
(getter (mem16 smode (add (.sym Dsp- offset -u8) (reg h-sb))))
(setter (set (mem16 dmode (add (.sym Dsp- offset -u8) (reg h-sb))) newval))
)
(define-derived-operand
(name (.sym dst16- offset -16-SB-relative-Ext- smode))
(comment (.str "m16c dsp:16[sb] relative destination " smode))
(attrs (machine 16))
(mode dmode)
(args ((.sym Dsp- offset -u16)))
(syntax (.str "${Dsp-" offset "-u16}[sb]"))
(base-ifield f-12-4)
(encoding (+ (f-12-4 #xE) (.sym Dsp- offset -u16)))
(ifield-assertion (eq f-12-4 #xE))
(getter (mem16 smode (add (.sym Dsp- offset -u16) (reg h-sb))))
(setter (set (mem16 dmode (add (.sym Dsp- offset -u16) (reg h-sb))) newval))
)
(define-derived-operand
(name (.sym dst16- offset -8-FB-relative-Ext- smode))
(comment (.str "m16c dsp:8[fb] relative destination " smode))
(attrs (machine 16))
(mode dmode)
(args ((.sym Dsp- offset -s8)))
(syntax (.str "${Dsp-" offset "-s8}[fb]"))
(base-ifield f-12-4)
(encoding (+ (f-12-4 #xB) (.sym Dsp- offset -s8)))
(ifield-assertion (eq f-12-4 #xB))
(getter (mem16 smode (add (.sym Dsp- offset -s8) (reg h-fb))))
(setter (set (mem16 dmode (add (.sym Dsp- offset -s8) (reg h-fb))) newval))
)
(define-derived-operand
(name (.sym dst16- offset -8-An-relative-Ext- smode))
(comment (.str "m16c dsp:8[An] relative destination " smode))
(attrs (machine 16))
(mode dmode)
(args (Dst16An (.sym Dsp- offset -u8)))
(syntax (.str "${Dsp-" offset "-u8}[$Dst16An]"))
(base-ifield f-12-4)
(encoding (+ (f-12-2 2) (f-14-1 0) (.sym Dsp- offset -u8) Dst16An))
(ifield-assertion (andif (eq f-12-2 2) (eq f-14-1 0)))
(getter (mem16 smode (add (.sym Dsp- offset -u8) Dst16An)))
(setter (set (mem16 dmode (add (.sym Dsp- offset -u8) Dst16An)) newval))
)
(define-derived-operand
(name (.sym dst16- offset -16-An-relative-Ext- smode))
(comment (.str "m16c dsp:16[An] relative destination " smode))
(attrs (machine 16))
(mode dmode)
(args (Dst16An (.sym Dsp- offset -u16)))
(syntax (.str "${Dsp-" offset "-u16}[$Dst16An]"))
(base-ifield f-12-4)
(encoding (+ (f-12-2 3) (f-14-1 0) (.sym Dsp- offset -u16) Dst16An))
(ifield-assertion (andif (eq f-12-2 3) (eq f-14-1 0)))
(getter (mem16 smode (add (.sym Dsp- offset -u16) Dst16An)))
(setter (set (mem16 dmode (add (.sym Dsp- offset -u16) Dst16An)) newval))
)
)
)
(dst16-relative-Ext-operand 16 QI HI)
(define-pmacro (dst32-relative-operand offset group base1 base2 smode dmode)
(begin
(define-derived-operand
(name (.sym dst32- offset -8-SB-relative- group - smode))
(comment (.str "m32c dsp:8[sb] relative destination " smode))
(attrs (machine 32))
(mode dmode)
(args ((.sym Dsp- offset -u8)))
(syntax (.str "${Dsp-" offset "-u8}[sb]"))
(base-ifield (.sym f- base1 -6))
(encoding (+ ((.sym f- base1 -3) 1) ((.sym f- base2 -2) 2) (.sym Dsp- offset -u8)))
(ifield-assertion (andif (eq (.sym f- base1 -3) 1) (eq (.sym f- base2 -2) 2)))
(getter (c-call dmode (.str "operand_getter_" dmode) sb (.sym Dsp- offset -u8)))
(setter (c-call DFLT (.str "operand_setter_" dmode) newval sb (.sym Dsp- offset -u8)))
; (getter (mem32 smode (add (.sym Dsp- offset -u8) (reg h-sb))))
; (setter (set (mem32 dmode (add (.sym Dsp- offset -u8) (reg h-sb))) newval))
)
(define-derived-operand
(name (.sym dst32- offset -16-SB-relative- group - smode))
(comment (.str "m32c dsp:16[sb] relative destination " smode))
(attrs (machine 32))
(mode dmode)
(args ((.sym Dsp- offset -u16)))
(syntax (.str "${Dsp-" offset "-u16}[sb]"))
(base-ifield (.sym f- base1 -6))
(encoding (+ ((.sym f- base1 -3) 2) ((.sym f- base2 -2) 2) (.sym Dsp- offset -u16)))
(ifield-assertion (andif (eq (.sym f- base1 -3) 2) (eq (.sym f- base2 -2) 2)))
(getter (c-call dmode (.str "operand_getter_" dmode) sb (.sym Dsp- offset -u16)))
(setter (c-call DFLT (.str "operand_setter_" dmode) newval sb (.sym Dsp- offset -u16)))
; (getter (mem32 smode (add (.sym Dsp- offset -u16) (reg h-sb))))
; (setter (set (mem32 dmode (add (.sym Dsp- offset -u16) (reg h-sb))) newval))
)
(define-derived-operand
(name (.sym dst32- offset -8-FB-relative- group - smode))
(comment (.str "m32c dsp:8[fb] relative destination " smode))
(attrs (machine 32))
(mode dmode)
(args ((.sym Dsp- offset -s8)))
(syntax (.str "${Dsp-" offset "-s8}[fb]"))
(base-ifield (.sym f- base1 -6))
(encoding (+ ((.sym f- base1 -3) 1) ((.sym f- base2 -2) 3) (.sym Dsp- offset -s8)))
(ifield-assertion (andif (eq (.sym f- base1 -3) 1) (eq (.sym f- base2 -2) 3)))
(getter (c-call dmode (.str "operand_getter_" dmode) fb (.sym Dsp- offset -s8)))
(setter (c-call DFLT (.str "operand_setter_" dmode) newval fb (.sym Dsp- offset -s8)))
; (getter (mem32 smode (add (.sym Dsp- offset -s8) (reg h-fb))))
; (setter (set (mem32 dmode (add (.sym Dsp- offset -s8) (reg h-fb))) newval))
)
(define-derived-operand
(name (.sym dst32- offset -16-FB-relative- group - smode))
(comment (.str "m32c dsp:16[fb] relative destination " smode))
(attrs (machine 32))
(mode dmode)
(args ((.sym Dsp- offset -s16)))
(syntax (.str "${Dsp-" offset "-s16}[fb]"))
(base-ifield (.sym f- base1 -6))
(encoding (+ ((.sym f- base1 -3) 2) ((.sym f- base2 -2) 3) (.sym Dsp- offset -s16)))
(ifield-assertion (andif (eq (.sym f- base1 -3) 2) (eq (.sym f- base2 -2) 3)))
(getter (c-call dmode (.str "operand_getter_" dmode) fb (.sym Dsp- offset -s16)))
(setter (c-call DFLT (.str "operand_setter_" dmode) newval fb (.sym Dsp- offset -s16)))
; (getter (mem32 smode (add (.sym Dsp- offset -s16) (reg h-fb))))
; (setter (set (mem32 dmode (add (.sym Dsp- offset -s16) (reg h-fb))) newval))
)
(define-derived-operand
(name (.sym dst32- offset -8-An-relative- group - smode))
(comment (.str "m32c dsp:8[An] relative destination " smode))
(attrs (machine 32))
(mode dmode)
(args ((.sym Dst32An group) (.sym Dsp- offset -u8)))
(syntax (.str "${Dsp-" offset "-u8}[$Dst32An" group "]"))
(base-ifield (.sym f- base1 -6))
(encoding (+ ((.sym f- base1 -3) 1) ((.sym f- base2 -1) 0) (.sym Dsp- offset -u8) (.sym Dst32An group)))
(ifield-assertion (andif (eq (.sym f- base1 -3) 1) (eq (.sym f- base2 -1) 0)))
(getter (c-call dmode (.str "operand_getter_" dmode) (.sym Dst32An group) (.sym Dsp- offset -u8)))
(setter (c-call DFLT (.str "operand_setter_" dmode) newval (.sym Dst32An group) (.sym Dsp- offset -u8)))
; (getter (mem32 smode (add (.sym Dsp- offset -u8) (.sym Dst32An group))))
; (setter (set (mem32 dmode (add (.sym Dsp- offset -u8) (.sym Dst32An group))) newval))
)
(define-derived-operand
(name (.sym dst32- offset -16-An-relative- group - smode))
(comment (.str "m32c dsp:16[An] relative destination " smode))
(attrs (machine 32))
(mode dmode)
(args ((.sym Dst32An group) (.sym Dsp- offset -u16)))
(syntax (.str "${Dsp-" offset "-u16}[$Dst32An" group "]"))
(base-ifield (.sym f- base1 -6))
(encoding (+ ((.sym f- base1 -3) 2) ((.sym f- base2 -1) 0) (.sym Dsp- offset -u16) (.sym Dst32An group)))
(ifield-assertion (andif (eq (.sym f- base1 -3) 2) (eq (.sym f- base2 -1) 0)))
(getter (c-call dmode (.str "operand_getter_" dmode) (.sym Dst32An group) (.sym Dsp- offset -u16)))
(setter (c-call DFLT (.str "operand_setter_" dmode) newval (.sym Dst32An group) (.sym Dsp- offset -u16)))
; (getter (mem32 smode (add (.sym Dsp- offset -u16) (.sym Dst32An group))))
; (setter (set (mem32 dmode (add (.sym Dsp- offset -u16) (.sym Dst32An group))) newval))
)
(define-derived-operand
(name (.sym dst32- offset -24-An-relative- group - smode))
(comment (.str "m32c dsp:16[An] relative destination " smode))
(attrs (machine 32))
(mode dmode)
(args ((.sym Dst32An group) (.sym Dsp- offset -u24)))
(syntax (.str "${Dsp-" offset "-u24}[$Dst32An" group "]"))
(base-ifield (.sym f- base1 -6))
(encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -1) 0) (.sym Dsp- offset -u24) (.sym Dst32An group)))
(ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -1) 0)))
(getter (c-call dmode (.str "operand_getter_" dmode) (.sym Dst32An group) (.sym Dsp- offset -u24)))
(setter (c-call DFLT (.str "operand_setter_" dmode) newval (.sym Dst32An group) (.sym Dsp- offset -u24)))
; (getter (mem32 smode (add (.sym Dsp- offset -u24) (.sym Dst32An group))))
; (setter (set (mem32 dmode (add (.sym Dsp- offset -u24) (.sym Dst32An group))) newval))
)
)
)
(dst32-relative-operand 16 Unprefixed 4 8 QI QI)
(dst32-relative-operand 24 Unprefixed 4 8 QI QI)
(dst32-relative-operand 32 Unprefixed 4 8 QI QI)
(dst32-relative-operand 40 Unprefixed 4 8 QI QI)
(dst32-relative-operand 16 Unprefixed 4 8 HI HI)
(dst32-relative-operand 24 Unprefixed 4 8 HI HI)
(dst32-relative-operand 32 Unprefixed 4 8 HI HI)
(dst32-relative-operand 40 Unprefixed 4 8 HI HI)
(dst32-relative-operand 16 Unprefixed 4 8 SI SI)
(dst32-relative-operand 24 Unprefixed 4 8 SI SI)
(dst32-relative-operand 32 Unprefixed 4 8 SI SI)
(dst32-relative-operand 40 Unprefixed 4 8 SI SI)
(dst32-relative-operand 24 Prefixed 12 16 QI QI)
(dst32-relative-operand 32 Prefixed 12 16 QI QI)
(dst32-relative-operand 40 Prefixed 12 16 QI QI)
(dst32-relative-operand 48 Prefixed 12 16 QI QI)
(dst32-relative-operand 24 Prefixed 12 16 HI HI)
(dst32-relative-operand 32 Prefixed 12 16 HI HI)
(dst32-relative-operand 40 Prefixed 12 16 HI HI)
(dst32-relative-operand 48 Prefixed 12 16 HI HI)
(dst32-relative-operand 24 Prefixed 12 16 SI SI)
(dst32-relative-operand 32 Prefixed 12 16 SI SI)
(dst32-relative-operand 40 Prefixed 12 16 SI SI)
(dst32-relative-operand 48 Prefixed 12 16 SI SI)
(dst32-relative-operand 16 ExtUnprefixed 4 8 QI HI)
(dst32-relative-operand 16 ExtUnprefixed 4 8 HI SI)
;-------------------------------------------------------------
; Absolute address
;-------------------------------------------------------------
(define-pmacro (dst16-absolute offset xmode)
(begin
(define-derived-operand
(name (.sym dst16- offset -16-absolute- xmode))
(comment (.str "m16c absolute address " xmode))
(attrs (machine 16))
(mode xmode)
(args ((.sym Dsp- offset -u16)))
(syntax (.str "${Dsp-" offset "-u16}"))
(base-ifield f-12-4)
(encoding (+ (f-12-4 #xF) (.sym Dsp- offset -u16)))
(ifield-assertion (eq f-12-4 #xF))
(getter (mem16 xmode (.sym Dsp- offset -u16)))
(setter (set (mem16 xmode (.sym Dsp- offset -u16)) newval))
)
)
)
(dst16-absolute 16 QI)
(dst16-absolute 24 QI)
(dst16-absolute 32 QI)
(dst16-absolute 40 QI)
(dst16-absolute 48 QI)
(dst16-absolute 16 HI)
(dst16-absolute 24 HI)
(dst16-absolute 32 HI)
(dst16-absolute 40 HI)
(dst16-absolute 48 HI)
(dst16-absolute 16 SI)
(dst16-absolute 24 SI)
(dst16-absolute 32 SI)
(dst16-absolute 40 SI)
(dst16-absolute 48 SI)
(define-derived-operand
(name dst16-16-16-absolute-Ext-QI)
(comment "m16c absolute address QI")
(attrs (machine 16))
(mode HI)
(args (Dsp-16-u16))
(syntax "${Dsp-16-u16}")
(base-ifield f-12-4)
(encoding (+ (f-12-4 #xF) Dsp-16-u16))
(ifield-assertion (eq f-12-4 #xF))
(getter (mem16 QI Dsp-16-u16))
(setter (set (mem16 HI Dsp-16-u16) newval))
)
(define-pmacro (dst32-absolute offset group base1 base2 smode dmode)
(begin
(define-derived-operand
(name (.sym dst32- offset -16-absolute- group - smode))
(comment (.str "m32c absolute address " smode))
(attrs (machine 32))
(mode dmode)
(args ((.sym Dsp- offset -u16)))
(syntax (.str "${Dsp-" offset "-u16}"))
(base-ifield (.sym f- base1 -6))
(encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -2) 3) (.sym Dsp- offset -u16)))
(ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -2) 3)))
(getter (c-call smode (.str "operand_getter_" smode) (const 0) (.sym Dsp- offset -u16)))
(setter (c-call DFLT (.str "operand_setter_" dmode) newval (const 0) (.sym Dsp- offset -u16)))
; (getter (mem32 smode (.sym Dsp- offset -u16)))
; (setter (set (mem32 dmode (.sym Dsp- offset -u16)) newval))
)
(define-derived-operand
(name (.sym dst32- offset -24-absolute- group - smode))
(comment (.str "m32c absolute address " smode))
(attrs (machine 32))
(mode dmode)
(args ((.sym Dsp- offset -u24)))
(syntax (.str "${Dsp-" offset "-u24}"))
(base-ifield (.sym f- base1 -6))
(encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -2) 2) (.sym Dsp- offset -u24)))
(ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -2) 2)))
(getter (c-call smode (.str "operand_getter_" smode) (const 0) (.sym Dsp- offset -u24)))
(setter (c-call DFLT (.str "operand_setter_" dmode) newval (const 0) (.sym Dsp- offset -u24)))
; (getter (mem32 smode (.sym Dsp- offset -u24)))
; (setter (set (mem32 dmode (.sym Dsp- offset -u24)) newval))
)
)
)
(dst32-absolute 16 Unprefixed 4 8 QI QI)
(dst32-absolute 24 Unprefixed 4 8 QI QI)
(dst32-absolute 32 Unprefixed 4 8 QI QI)
(dst32-absolute 40 Unprefixed 4 8 QI QI)
(dst32-absolute 16 Unprefixed 4 8 HI HI)
(dst32-absolute 24 Unprefixed 4 8 HI HI)
(dst32-absolute 32 Unprefixed 4 8 HI HI)
(dst32-absolute 40 Unprefixed 4 8 HI HI)
(dst32-absolute 16 Unprefixed 4 8 SI SI)
(dst32-absolute 24 Unprefixed 4 8 SI SI)
(dst32-absolute 32 Unprefixed 4 8 SI SI)
(dst32-absolute 40 Unprefixed 4 8 SI SI)
(dst32-absolute 24 Prefixed 12 16 QI QI)
(dst32-absolute 32 Prefixed 12 16 QI QI)
(dst32-absolute 40 Prefixed 12 16 QI QI)
(dst32-absolute 48 Prefixed 12 16 QI QI)
(dst32-absolute 24 Prefixed 12 16 HI HI)
(dst32-absolute 32 Prefixed 12 16 HI HI)
(dst32-absolute 40 Prefixed 12 16 HI HI)
(dst32-absolute 48 Prefixed 12 16 HI HI)
(dst32-absolute 24 Prefixed 12 16 SI SI)
(dst32-absolute 32 Prefixed 12 16 SI SI)
(dst32-absolute 40 Prefixed 12 16 SI SI)
(dst32-absolute 48 Prefixed 12 16 SI SI)
(dst32-absolute 16 ExtUnprefixed 4 8 QI HI)
(dst32-absolute 16 ExtUnprefixed 4 8 HI SI)
;-------------------------------------------------------------
; An indirect indirect
;-------------------------------------------------------------
;(define-pmacro (dst-An-indirect-indirect-operand xmode)
; (define-derived-operand
; (name (.sym dst32-An-indirect-indirect- xmode))
; (comment (.str "m32c An indirect indirect destination " xmode))
; (attrs (machine 32))
; (mode xmode)
; (args (Dst32AnPrefixed))
; (syntax (.str "[[$Dst32AnPrefixed]]"))
; (base-ifield f-12-6)
; (encoding (+ (f-12-3 0) (f-16-1 0) Dst32AnPrefixed))
; (ifield-assertion (andif (eq f-12-3 0) (eq f-16-1 0)))
; (getter (mem32 xmode (indirect-addr Dst32AnPrefixed)))
; (setter (set (mem32 xmode (indirect-addr Dst32AnPrefixed)) newval))
; )
;)
; (dst-An-indirect-indirect-operand QI)
; (dst-An-indirect-indirect-operand HI)
; (dst-An-indirect-indirect-operand SI)
;-------------------------------------------------------------
; Relative indirect
;-------------------------------------------------------------
(define-pmacro (dst-relative-indirect-operand offset xmode)
(begin
; (define-derived-operand
; (name (.sym dst32- offset -8-SB-relative-indirect- xmode))
; (comment (.str "m32c dsp:8[sb] relative destination " xmode))
; (attrs (machine 32))
; (mode xmode)
; (args ((.sym Dsp- offset -u8)))
; (syntax (.str "[${Dsp-" offset "-u8}[sb]]"))
; (base-ifield f-12-6)
; (encoding (+ (f-12-3 1) (f-16-2 2) (.sym Dsp- offset -u8)))
; (ifield-assertion (andif (eq f-12-3 1) (eq f-16-2 2)))
; (getter (mem32 xmode (indirect-addr (add (.sym Dsp- offset -u8) (reg h-sb)))))
; (setter (set (mem32 xmode (indirect-addr (add (.sym Dsp- offset -u8) (reg h-sb)))) newval))
; )
; (define-derived-operand
; (name (.sym dst32- offset -16-SB-relative-indirect- xmode))
; (comment (.str "m32c dsp:16[sb] relative destination " xmode))
; (attrs (machine 32))
; (mode xmode)
; (args ((.sym Dsp- offset -u16)))
; (syntax (.str "[${Dsp-" offset "-u16}[sb]]"))
; (base-ifield f-12-6)
; (encoding (+ (f-12-3 2) (f-16-2 2) (.sym Dsp- offset -u16)))
; (ifield-assertion (andif (eq f-12-3 2) (eq f-16-2 2)))
; (getter (mem32 xmode (indirect-addr (add (.sym Dsp- offset -u16) (reg h-sb)))))
; (setter (set (mem32 xmode (indirect-addr (add (.sym Dsp- offset -u16) (reg h-sb)))) newval))
; )
; (define-derived-operand
; (name (.sym dst32- offset -8-FB-relative-indirect- xmode))
; (comment (.str "m32c dsp:8[fb] relative destination " xmode))
; (attrs (machine 32))
; (mode xmode)
; (args ((.sym Dsp- offset -s8)))
; (syntax (.str "[${Dsp-" offset "-s8}[fb]]"))
; (base-ifield f-12-6)
; (encoding (+ (f-12-3 1) (f-16-2 3) (.sym Dsp- offset -s8)))
; (ifield-assertion (andif (eq f-12-3 1) (eq f-16-2 3)))
; (getter (mem32 xmode (indirect-addr (add (.sym Dsp- offset -s8) (reg h-fb)))))
; (setter (set (mem32 xmode (indirect-addr (add (.sym Dsp- offset -s8) (reg h-fb)))) newval))
; )
; (define-derived-operand
; (name (.sym dst32- offset -16-FB-relative-indirect- xmode))
; (comment (.str "m32c dsp:16[fb] relative destination " xmode))
; (attrs (machine 32))
; (mode xmode)
; (args ((.sym Dsp- offset -s16)))
; (syntax (.str "[${Dsp-" offset "-s16}[fb]]"))
; (base-ifield f-12-6)
; (encoding (+ (f-12-3 2) (f-16-2 3) (.sym Dsp- offset -s16)))
; (ifield-assertion (andif (eq f-12-3 2) (eq f-16-2 3)))
; (getter (mem32 xmode (indirect-addr (add (.sym Dsp- offset -s16) (reg h-fb)))))
; (setter (set (mem32 xmode (indirect-addr (add (.sym Dsp- offset -s16) (reg h-fb)))) newval))
; )
; (define-derived-operand
; (name (.sym dst32- offset -8-An-relative-indirect- xmode))
; (comment (.str "m32c dsp:8[An] relative indirect destination " xmode))
; (attrs (machine 32))
; (mode xmode)
; (args (Dst32AnPrefixed (.sym Dsp- offset -u8)))
; (syntax (.str "[${Dsp-" offset "-u8}[$Dst32AnPrefixed]]"))
; (base-ifield f-12-6)
; (encoding (+ (f-12-3 1) (f-16-1 0) (.sym Dsp- offset -u8) Dst32AnPrefixed))
; (ifield-assertion (andif (eq f-12-3 1) (eq f-16-1 0)))
; (getter (mem32 xmode (indirect-addr (add (.sym Dsp- offset -u8) Dst32AnPrefixed))))
; (setter (set (mem32 xmode (indirect-addr (add (.sym Dsp- offset -u8) Dst32AnPrefixed))) newval))
; )
; (define-derived-operand
; (name (.sym dst32- offset -16-An-relative-indirect- xmode))
; (comment (.str "m32c dsp:16[An] relative destination " xmode))
; (attrs (machine 32))
; (mode xmode)
; (args (Dst32AnPrefixed (.sym Dsp- offset -u16)))
; (syntax (.str "[${Dsp-" offset "-u16}[$Dst32AnPrefixed]]"))
; (base-ifield f-12-6)
; (encoding (+ (f-12-3 2) (f-16-1 0) (.sym Dsp- offset -u16) Dst32AnPrefixed))
; (ifield-assertion (andif (eq f-12-3 2) (eq f-16-1 0)))
; (getter (mem32 xmode (indirect-addr (add (.sym Dsp- offset -u16) Dst32AnPrefixed))))
; (setter (set (mem32 xmode (indirect-addr (add (.sym Dsp- offset -u16) Dst32AnPrefixed))) newval))
; )
; (define-derived-operand
; (name (.sym dst32- offset -24-An-relative-indirect- xmode))
; (comment (.str "m32c dsp:24[An] relative destination " xmode))
; (attrs (machine 32))
; (mode xmode)
; (args (Dst32AnPrefixed (.sym Dsp- offset -u24)))
; (syntax (.str "[${Dsp-" offset "-u24}[$Dst32AnPrefixed]]"))
; (base-ifield f-12-6)
; (encoding (+ (f-12-3 3) (f-16-1 0) (.sym Dsp- offset -u24) Dst32AnPrefixed))
; (ifield-assertion (andif (eq f-12-3 3) (eq f-16-1 0)))
; (getter (mem32 xmode (indirect-addr (add (.sym Dsp- offset -u24) Dst32AnPrefixed))))
; (setter (set (mem32 xmode (indirect-addr (add (.sym Dsp- offset -u24) Dst32AnPrefixed))) newval))
; )
)
)
; (dst-relative-indirect-operand 24 QI)
; (dst-relative-indirect-operand 32 QI)
; (dst-relative-indirect-operand 40 QI)
; (dst-relative-indirect-operand 48 QI)
; (dst-relative-indirect-operand 24 HI)
; (dst-relative-indirect-operand 32 HI)
; (dst-relative-indirect-operand 40 HI)
; (dst-relative-indirect-operand 48 HI)
; (dst-relative-indirect-operand 24 SI)
; (dst-relative-indirect-operand 32 SI)
; (dst-relative-indirect-operand 40 SI)
; (dst-relative-indirect-operand 48 SI)
;-------------------------------------------------------------
; Absolute indirect
;-------------------------------------------------------------
(define-pmacro (dst-absolute-indirect offset xmode)
(begin
; (define-derived-operand
; (name (.sym dst32- offset -16-absolute-indirect-derived- xmode))
; (comment (.str "m32c absolute indirect address " xmode))
; (attrs (machine 32))
; (mode xmode)
; (args ((.sym Dsp- offset -u16)))
; (syntax (.str "[${Dsp-" offset "-u16}]"))
; (base-ifield f-12-6)
; (encoding (+ (f-12-3 3) (f-16-2 3) (.sym Dsp- offset -u16)))
; (ifield-assertion (andif (eq f-12-3 3) (eq f-16-2 3)))
; (getter (mem32 xmode (indirect-addr (.sym Dsp- offset -u16))))
; (setter (set (mem32 xmode (indirect-addr (.sym Dsp- offset -u16))) newval))
; )
; (define-derived-operand
; (name (.sym dst32- offset -24-absolute-indirect-derived- xmode))
; (comment (.str "m32c absolute indirect address " xmode))
; (attrs (machine 32))
; (mode xmode)
; (args ((.sym Dsp- offset -u24)))
; (syntax (.str "[${Dsp-" offset "-u24}]"))
; (base-ifield f-12-6)
; (encoding (+ (f-12-3 3) (f-16-2 2) (.sym Dsp- offset -u24)))
; (ifield-assertion (andif (eq f-12-3 3) (eq f-16-2 2)))
; (getter (mem32 xmode (indirect-addr (.sym Dsp- offset -u24))))
; (setter (set (mem32 xmode (indirect-addr (.sym Dsp- offset -u24))) newval))
; )
)
)
(dst-absolute-indirect 24 QI)
(dst-absolute-indirect 32 QI)
(dst-absolute-indirect 40 QI)
(dst-absolute-indirect 48 QI)
(dst-absolute-indirect 24 HI)
(dst-absolute-indirect 32 HI)
(dst-absolute-indirect 40 HI)
(dst-absolute-indirect 48 HI)
(dst-absolute-indirect 24 SI)
(dst-absolute-indirect 32 SI)
(dst-absolute-indirect 40 SI)
(dst-absolute-indirect 48 SI)
;-------------------------------------------------------------
; Bit operands
;-------------------------------------------------------------
(define-pmacro (get-register-bit reg bitno)
(and (srl reg bitno) 1)
)
(define-pmacro (set-register-bit reg bitno value)
(set reg (or (and reg (inv (sll 1 bitno)))
(sll (and QI value 1) bitno)))
)
(define-pmacro (get-memory-bit mach base bitno)
(and (srl (mem-mach mach QI (add base (div bitno 8)))
(mod bitno 8))
1)
)
(define-pmacro (set-memory-bit mach base bitno value)
(sequence ((USI addr))
(set addr (add base (div bitno 8)))
(set (mem-mach mach QI addr)
(or (and (mem-mach mach QI addr)
(inv (sll 1 (mod bitno 8))))
(sll (and QI value 1) (mod bitno 8)))))
)
;-------------------------------------------------------------
; Rn direct
;-------------------------------------------------------------
(define-derived-operand
(name bit16-Rn-direct)
(comment "m16c Rn direct bit")
(attrs (machine 16))
(mode BI)
(args (Bitno16R Bit16Rn))
(syntax "$Bitno16R,$Bit16Rn")
(base-ifield f-12-4)
(encoding (+ (f-12-2 0) Bit16Rn Bitno16R))
(ifield-assertion (eq f-12-2 0))
(getter (get-register-bit Bit16Rn Bitno16R))
(setter (set-register-bit Bit16Rn Bitno16R newval))
)
(define-pmacro (bit32-Rn-direct-operand group base)
(begin
(define-derived-operand
(name (.sym bit32-Rn-direct- group))
(comment "m32c Rn direct bit")
(attrs (machine 32))
(mode BI)
(args ((.sym Bitno32 group) (.sym Bit32Rn group)))
(syntax (.str "$Bitno32" group ",$Bit32Rn" group))
(base-ifield (.sym f- base -6))
(encoding (+ ((.sym f- base -3) 4) (.sym Bit32Rn group) (.sym Bitno32 group)))
(ifield-assertion (eq (.sym f- base -3) 4))
(getter (get-register-bit (.sym Bit32Rn group) (.sym Bitno32 group)))
(setter (set-register-bit (.sym Bit32Rn group) (.sym Bitno32 group) newval))
)
)
)
(bit32-Rn-direct-operand Unprefixed 4)
(bit32-Rn-direct-operand Prefixed 12)
;-------------------------------------------------------------
; An direct
;-------------------------------------------------------------
(define-derived-operand
(name bit16-An-direct)
(comment "m16c An direct bit")
(attrs (machine 16))
(mode BI)
(args (Bitno16R Bit16An))
(syntax "$Bitno16R,$Bit16An")
(base-ifield f-12-4)
(encoding (+ (f-12-2 1) (f-14-1 0) Bit16An Bitno16R))
(ifield-assertion (andif (eq f-12-2 1) (eq f-14-1 0)))
(getter (get-register-bit Bit16An Bitno16R))
(setter (set-register-bit Bit16An Bitno16R newval))
)
(define-pmacro (bit32-An-direct-operand group base1 base2)
(begin
(define-derived-operand
(name (.sym bit32-An-direct- group))
(comment "m32c An direct bit")
(attrs (machine 32))
(mode BI)
(args ((.sym Bitno32 group) (.sym Bit32An group)))
(syntax (.str "$Bitno32" group ",$Bit32An" group))
(base-ifield (.sym f- base1 -6))
(encoding (+ ((.sym f- base1 -3) 0) ((.sym f- base2 -1) 1) (.sym Bit32An group) (.sym Bitno32 group)))
(ifield-assertion (andif (eq (.sym f- base1 -3) 0) (eq (.sym f- base2 -1) 1)))
(getter (get-register-bit (.sym Bit32An group) (.sym Bitno32 group)))
(setter (set-register-bit (.sym Bit32An group) (.sym Bitno32 group) newval))
)
)
)
(bit32-An-direct-operand Unprefixed 4 8)
(bit32-An-direct-operand Prefixed 12 16)
;-------------------------------------------------------------
; An indirect
;-------------------------------------------------------------
(define-derived-operand
(name bit16-An-indirect)
(comment "m16c An indirect bit")
(attrs (machine 16))
(mode BI)
(args (Bit16An))
(syntax "[$Bit16An]")
(base-ifield f-12-4)
(encoding (+ (f-12-2 1) (f-14-1 1) Bit16An))
(ifield-assertion (andif (eq f-12-2 1) (eq f-14-1 1)))
(getter (get-memory-bit 16 0 Bit16An))
(setter (set-memory-bit 16 0 Bit16An newval))
)
(define-pmacro (bit32-An-indirect-operand group base1 base2)
(begin
(define-derived-operand
(name (.sym bit32-An-indirect- group))
(comment "m32c An indirect destination ")
(attrs (machine 32))
(mode BI)
(args ((.sym Bitno32 group) (.sym Bit32An group)))
(syntax (.str "$Bitno32" group ",[$Bit32An" group "]"))
(base-ifield (.sym f- base1 -6))
(encoding (+ ((.sym f- base1 -3) 0) ((.sym f- base2 -1) 0) (.sym Bit32An group) (.sym Bitno32 group)))
(ifield-assertion (andif (eq (.sym f- base1 -3) 0) (eq (.sym f- base2 -1) 0)))
(getter (get-memory-bit 32 (.sym Bit32An group) (.sym Bitno32 group)))
(setter (set-memory-bit 32 (.sym Bit32An group) (.sym Bitno32 group) newval))
)
)
)
(bit32-An-indirect-operand Unprefixed 4 8)
(bit32-An-indirect-operand Prefixed 12 16)
;-------------------------------------------------------------
; dsp:d[r] relative
;-------------------------------------------------------------
(define-pmacro (bit16-relative-operand offset)
(begin
(define-derived-operand
(name (.sym bit16- offset -8-SB-relative))
(comment (.str "m16c dsp:8[sb] relative bit " xmode))
(attrs (machine 16))
(mode BI)
(args ((.sym BitBase16- offset -u8)))
(syntax (.str "${BitBase16-" offset "-u8}[sb]"))
(base-ifield f-12-4)
(encoding (+ (f-12-4 #xA) (.sym BitBase16- offset -u8)))
(ifield-assertion (eq f-12-4 #xA))
(getter (get-memory-bit 16 (reg h-sb) (.sym BitBase16- offset -u8)))
(setter (set-memory-bit 16 (reg h-sb) (.sym BitBase16- offset -u8) newval))
)
(define-derived-operand
(name (.sym bit16- offset -16-SB-relative))
(comment (.str "m16c dsp:16[sb] relative bit " xmode))
(attrs (machine 16))
(mode BI)
(args ((.sym BitBase16- offset -u16)))
(syntax (.str "${BitBase16-" offset "-u16}[sb]"))
(base-ifield f-12-4)
(encoding (+ (f-12-4 #xE) (.sym BitBase16- offset -u16)))
(ifield-assertion (eq f-12-4 #xE))
(getter (get-memory-bit 16 (reg h-sb) (.sym BitBase16- offset -u16)))
(setter (set-memory-bit 16 (reg h-sb) (.sym BitBase16- offset -u16) newval))
)
(define-derived-operand
(name (.sym bit16- offset -8-FB-relative))
(comment (.str "m16c dsp:8[fb] relative bit " xmode))
(attrs (machine 16))
(mode BI)
(args ((.sym BitBase16- offset -s8)))
(syntax (.str "${BitBase16-" offset "-s8}[fb]"))
(base-ifield f-12-4)
(encoding (+ (f-12-4 #xB) (.sym BitBase16- offset -s8)))
(ifield-assertion (eq f-12-4 #xB))
(getter (get-memory-bit 16 (reg h-fb) (.sym BitBase16- offset -s8)))
(setter (set-memory-bit 16 (reg h-fb) (.sym BitBase16- offset -s8) newval))
)
(define-derived-operand
(name (.sym bit16- offset -8-An-relative))
(comment (.str "m16c dsp:8[An] relative bit " xmode))
(attrs (machine 16))
(mode BI)
(args (Bit16An (.sym Dsp- offset -u8)))
(syntax (.str "${Dsp-" offset "-u8}[$Bit16An]"))
(base-ifield f-12-4)
(encoding (+ (f-12-2 2) (f-14-1 0) (.sym Dsp- offset -u8) Bit16An))
(ifield-assertion (andif (eq f-12-2 2) (eq f-14-1 0)))
(getter (get-memory-bit 16 (.sym Dsp- offset -u8) Bit16An))
(setter (set-memory-bit 16 (.sym Dsp- offset -u8) Bit16An newval))
)
(define-derived-operand
(name (.sym bit16- offset -16-An-relative))
(comment (.str "m16c dsp:16[An] relative bit " xmode))
(attrs (machine 16))
(mode BI)
(args (Bit16An (.sym Dsp- offset -u16)))
(syntax (.str "${Dsp-" offset "-u16}[$Bit16An]"))
(base-ifield f-12-4)
(encoding (+ (f-12-2 3) (f-14-1 0) (.sym Dsp- offset -u16) Bit16An))
(ifield-assertion (andif (eq f-12-2 3) (eq f-14-1 0)))
(getter (get-memory-bit 16 (.sym Dsp- offset -u16) Bit16An))
(setter (set-memory-bit 16 (.sym Dsp- offset -u16) Bit16An newval))
)
)
)
(bit16-relative-operand 16)
(define-pmacro (bit32-relative-operand offset group base1 base2)
(begin
(define-derived-operand
(name (.sym bit32- offset -11-SB-relative- group))
(comment "m32c bit,base:11[sb] relative bit")
(attrs (machine 32))
(mode BI)
(args ((.sym BitBase32- offset -u11- group)))
(syntax (.str "${BitBase32-" offset "-u11-" group "}[sb]"))
(base-ifield (.sym f- base1 -12))
(encoding (+ ((.sym f- base1 -3) 1) ((.sym f- base2 -2) 2) (.sym BitBase32- offset -u11- group)))
(ifield-assertion (andif (eq (.sym f- base1 -3) 1) (eq (.sym f- base2 -2) 2)))
(getter (get-memory-bit 32 (reg h-sb) (.sym BitBase32- offset -u11- group)))
(setter (set-memory-bit 32 (reg h-sb) (.sym BitBase32- offset -u11- group) newval))
)
(define-derived-operand
(name (.sym bit32- offset -19-SB-relative- group))
(comment "m32c bit,base:19[sb] relative bit")
(attrs (machine 32))
(mode BI)
(args ((.sym BitBase32- offset -u19- group)))
(syntax (.str "${BitBase32-" offset "-u19-" group "}[sb]"))
(base-ifield (.sym f- base1 -12))
(encoding (+ ((.sym f- base1 -3) 2) ((.sym f- base2 -2) 2) (.sym BitBase32- offset -u19- group)))
(ifield-assertion (andif (eq (.sym f- base1 -3) 2) (eq (.sym f- base2 -2) 2)))
(getter (get-memory-bit 32 (reg h-sb) (.sym BitBase32- offset -u19- group)))
(setter (set-memory-bit 32 (reg h-sb) (.sym BitBase32- offset -u19- group) newval))
)
(define-derived-operand
(name (.sym bit32- offset -11-FB-relative- group))
(comment "m32c bit,base:11[fb] relative bit")
(attrs (machine 32))
(mode BI)
(args ((.sym BitBase32- offset -s11- group)))
(syntax (.str "${BitBase32-" offset "-s11-" group "}[fb]"))
(base-ifield (.sym f- base1 -12))
(encoding (+ ((.sym f- base1 -3) 1) ((.sym f- base2 -2) 3) (.sym BitBase32- offset -s11- group)))
(ifield-assertion (andif (eq (.sym f- base1 -3) 1) (eq (.sym f- base2 -2) 3)))
(getter (get-memory-bit 32 (reg h-fb) (.sym BitBase32- offset -s11- group)))
(setter (set-memory-bit 32 (reg h-fb) (.sym BitBase32- offset -s11- group) newval))
)
(define-derived-operand
(name (.sym bit32- offset -19-FB-relative- group))
(comment "m32c bit,base:19[fb] relative bit")
(attrs (machine 32))
(mode BI)
(args ((.sym BitBase32- offset -s19- group)))
(syntax (.str "${BitBase32-" offset "-s19-" group "}[fb]"))
(base-ifield (.sym f- base1 -12))
(encoding (+ ((.sym f- base1 -3) 2) ((.sym f- base2 -2) 3) (.sym BitBase32- offset -s19- group)))
(ifield-assertion (andif (eq (.sym f- base1 -3) 2) (eq (.sym f- base2 -2) 3)))
(getter (get-memory-bit 32 (reg h-fb) (.sym BitBase32- offset -s19- group)))
(setter (set-memory-bit 32 (reg h-fb) (.sym BitBase32- offset -s19- group) newval))
)
(define-derived-operand
(name (.sym bit32- offset -11-An-relative- group))
(comment "m32c bit,base:11[An] relative bit")
(attrs (machine 32))
(mode BI)
(args ((.sym BitBase32- offset -u11- group) (.sym Bit32An group)))
(syntax (.str "${BitBase32-" offset "-u11-" group "}[$Bit32An" group "]"))
(base-ifield (.sym f- base1 -12))
(encoding (+ ((.sym f- base1 -3) 1) ((.sym f- base2 -1) 0) (.sym BitBase32- offset -u11- group) (.sym Bit32An group)))
(ifield-assertion (andif (eq (.sym f- base1 -3) 1) (eq (.sym f- base2 -1) 0)))
(getter (get-memory-bit 32 (.sym Bit32An group) (.sym BitBase32- offset -u11- group)))
(setter (set-memory-bit 32 (.sym Bit32An group) (.sym BitBase32- offset -u11- group) newval))
)
(define-derived-operand
(name (.sym bit32- offset -19-An-relative- group))
(comment "m32c bit,base:19[An] relative bit")
(attrs (machine 32))
(mode BI)
(args ((.sym BitBase32- offset -u19- group) (.sym Bit32An group)))
(syntax (.str "${BitBase32-" offset "-u19-" group "}[$Bit32An" group "]"))
(base-ifield (.sym f- base1 -12))
(encoding (+ ((.sym f- base1 -3) 2) ((.sym f- base2 -1) 0) (.sym BitBase32- offset -u19- group) (.sym Bit32An group)))
(ifield-assertion (andif (eq (.sym f- base1 -3) 2) (eq (.sym f- base2 -1) 0)))
(getter (get-memory-bit 32 (.sym Bit32An group) (.sym BitBase32- offset -u19- group)))
(setter (set-memory-bit 32 (.sym Bit32An group) (.sym BitBase32- offset -u19- group) newval))
)
(define-derived-operand
(name (.sym bit32- offset -27-An-relative- group))
(comment "m32c bit,base:27[An] relative bit")
(attrs (machine 32))
(mode BI)
(args ((.sym BitBase32- offset -u27- group) (.sym Bit32An group)))
(syntax (.str "${BitBase32-" offset "-u27-" group "}[$Bit32An" group "]"))
(base-ifield (.sym f- base1 -12))
(encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -1) 0) (.sym BitBase32- offset -u27- group) (.sym Bit32An group)))
(ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -1) 0)))
(getter (get-memory-bit 32 (.sym Bit32An group) (.sym BitBase32- offset -u27- group)))
(setter (set-memory-bit 32 (.sym Bit32An group) (.sym BitBase32- offset -u27- group) newval))
)
)
)
(bit32-relative-operand 16 Unprefixed 4 8)
(bit32-relative-operand 24 Prefixed 12 16)
(define-derived-operand
(name bit16-11-SB-relative-S)
(comment "m16c bit,base:11[sb] relative bit")
(attrs (machine 16))
(mode BI)
(args (BitBase16-8-u11-S))
(syntax "${BitBase16-8-u11-S}[sb]")
(base-ifield (.sym f-5-3))
(encoding (+ BitBase16-8-u11-S))
; (ifield-assertion (#t))
(getter (get-memory-bit 16 (reg h-sb) BitBase16-8-u11-S))
(setter (set-memory-bit 16 (reg h-sb) BitBase16-8-u11-S newval))
)
(define-derived-operand
(name Rn16-push-S-derived)
(comment "m16c r0[lh] for push,pop short version")
(attrs (machine 16))
(mode QI)
(args (Rn16-push-S))
(syntax "${Rn16-push-S}")
(base-ifield (.sym f-4-1))
(encoding (+ Rn16-push-S))
; (ifield-assertion (#t))
(getter (trunc QI Rn16-push-S))
(setter (set Rn16-push-S newval))
)
(define-derived-operand
(name An16-push-S-derived)
(comment "m16c r0[lh] for push,pop short version")
(attrs (machine 16))
(mode HI)
(args (An16-push-S))
(syntax "${An16-push-S}")
(base-ifield (.sym f-4-1))
(encoding (+ An16-push-S))
; (ifield-assertion (#t))
(getter (trunc QI An16-push-S))
(setter (set An16-push-S newval))
)
;-------------------------------------------------------------
; Absolute address
;-------------------------------------------------------------
(define-pmacro (bit16-absolute offset)
(begin
(define-derived-operand
(name (.sym bit16- offset -16-absolute))
(comment "m16c absolute address")
(attrs (machine 16))
(mode BI)
(args ((.sym BitBase16- offset -u16)))
(syntax (.str "${BitBase16-" offset "-u16}"))
(base-ifield f-12-4)
(encoding (+ (f-12-4 #xF) (.sym BitBase16- offset -u16)))
(ifield-assertion (eq f-12-4 #xF))
(getter (get-memory-bit 16 0 (.sym BitBase16- offset -u16)))
(setter (set-memory-bit 16 0 (.sym BitBase16- offset -u16) newval))
)
)
)
(bit16-absolute 16)
(define-pmacro (bit32-absolute offset group base1 base2)
(begin
(define-derived-operand
(name (.sym bit32- offset -19-absolute- group))
(comment "m32c absolute address bit")
(attrs (machine 32))
(mode BI)
(args ((.sym BitBase32- offset -u19- group)))
(syntax (.str "${BitBase32-" offset "-u19-" group "}"))
(base-ifield (.sym f- base1 -12))
(encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -2) 3) (.sym BitBase32- offset -u19- group)))
(ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -2) 3)))
(getter (get-memory-bit 32 0 (.sym BitBase32- offset -u19- group)))
(setter (set-memory-bit 32 0 (.sym BitBase32- offset -u19- group) newval))
)
(define-derived-operand
(name (.sym bit32- offset -27-absolute- group))
(comment "m32c absolute address bit")
(attrs (machine 32))
(mode BI)
(args ((.sym BitBase32- offset -u27- group)))
(syntax (.str "${BitBase32-" offset "-u27-" group "}"))
(base-ifield (.sym f- base1 -12))
(encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -2) 2) (.sym BitBase32- offset -u27- group)))
(ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -2) 2)))
(getter (get-memory-bit 32 0 (.sym BitBase32- offset -u27- group)))
(setter (set-memory-bit 32 0 (.sym BitBase32- offset -u27- group) newval))
)
)
)
(bit32-absolute 16 Unprefixed 4 8)
(bit32-absolute 24 Prefixed 12 16)
;-------------------------------------------------------------
; Destination operands for short fomat insns
;-------------------------------------------------------------
(define-derived-operand
(name dst16-3-S-R0l-direct-QI)
(comment "m16c R0l direct QI")
(attrs (machine 16))
(mode QI)
(args (R0l))
(syntax "r0l")
(base-ifield f-5-3)
(encoding (+ (f-5-3 4)))
(ifield-assertion (eq f-5-3 4))
(getter (trunc QI R0l))
(setter (set R0l newval))
)
(define-derived-operand
(name dst16-3-S-R0h-direct-QI)
(comment "m16c R0h direct QI")
(attrs (machine 16))
(mode QI)
(args (R0h))
(syntax "r0h")
(base-ifield f-5-3)
(encoding (+ (f-5-3 3)))
(ifield-assertion (eq f-5-3 3))
(getter (trunc QI R0h))
(setter (set R0h newval))
)
(define-derived-operand
(name dst16-3-S-8-8-SB-relative-QI)
(comment "m16c SB relative QI")
(attrs (machine 16))
(mode QI)
(args (Dsp-8-u8))
(syntax "${Dsp-8-u8}[sb]")
(base-ifield f-5-3)
(encoding (+ (f-5-3 5) Dsp-8-u8))
(ifield-assertion (eq f-5-3 5))
(getter (mem16 QI (add Dsp-8-u8 (reg h-sb))))
(setter (set (mem16 QI (add Dsp-8-u8 (reg h-sb))) newval))
)
(define-derived-operand
(name dst16-3-S-8-8-FB-relative-QI)
(comment "m16c FB relative QI")
(attrs (machine 16))
(mode QI)
(args (Dsp-8-s8))
(syntax "${Dsp-8-s8}[fb]")
(base-ifield f-5-3)
(encoding (+ (f-5-3 6) Dsp-8-s8))
(ifield-assertion (eq f-5-3 6))
(getter (mem16 QI (add Dsp-8-s8 (reg h-fb))))
(setter (set (mem16 QI (add Dsp-8-s8 (reg h-fb))) newval))
)
(define-derived-operand
(name dst16-3-S-8-16-absolute-QI)
(comment "m16c absolute address QI")
(attrs (machine 16))
(mode QI)
(args (Dsp-8-u16))
(syntax "${Dsp-8-u16}")
(base-ifield f-5-3)
(encoding (+ (f-5-3 7) Dsp-8-u16))
(ifield-assertion (eq f-5-3 7))
(getter (mem16 QI Dsp-8-u16))
(setter (set (mem16 QI Dsp-8-u16) newval))
)
(define-derived-operand
(name dst16-3-S-16-8-SB-relative-QI)
(comment "m16c SB relative QI")
(attrs (machine 16))
(mode QI)
(args (Dsp-16-u8))
(syntax "${Dsp-16-u8}[sb]")
(base-ifield f-5-3)
(encoding (+ (f-5-3 5) Dsp-16-u8))
(ifield-assertion (eq f-5-3 5))
(getter (mem16 QI (add Dsp-16-u8 (reg h-sb))))
(setter (set (mem16 QI (add Dsp-16-u8 (reg h-sb))) newval))
)
(define-derived-operand
(name dst16-3-S-16-8-FB-relative-QI)
(comment "m16c FB relative QI")
(attrs (machine 16))
(mode QI)
(args (Dsp-16-s8))
(syntax "${Dsp-16-s8}[fb]")
(base-ifield f-5-3)
(encoding (+ (f-5-3 6) Dsp-16-s8))
(ifield-assertion (eq f-5-3 6))
(getter (mem16 QI (add Dsp-16-s8 (reg h-fb))))
(setter (set (mem16 QI (add Dsp-16-s8 (reg h-fb))) newval))
)
(define-derived-operand
(name dst16-3-S-16-16-absolute-QI)
(comment "m16c absolute address QI")
(attrs (machine 16))
(mode QI)
(args (Dsp-16-u16))
(syntax "${Dsp-16-u16}")
(base-ifield f-5-3)
(encoding (+ (f-5-3 7) Dsp-16-u16))
(ifield-assertion (eq f-5-3 7))
(getter (mem16 QI Dsp-16-u16))
(setter (set (mem16 QI Dsp-16-u16) newval))
)
(define-derived-operand
(name srcdst16-r0l-r0h-S-derived)
(comment "m16c r0l/r0h operand for short format insns")
(attrs (machine 16))
(mode SI)
(args (SrcDst16-r0l-r0h-S-normal))
(syntax "${SrcDst16-r0l-r0h-S-normal}")
(base-ifield f-6-3)
(encoding (+ (f-6-2 0) SrcDst16-r0l-r0h-S-normal))
(ifield-assertion (eq f-6-2 0))
(getter (trunc SI SrcDst16-r0l-r0h-S-normal))
(setter ()) ; no setter
)
(define-derived-operand
(name dst32-2-S-R0l-direct-QI)
(comment "m32c R0l direct QI")
(attrs (machine 32))
(mode QI)
(args (R0l))
(syntax "r0l")
(base-ifield f-2-2)
(encoding (+ (f-2-2 0)))
(ifield-assertion (eq f-2-2 0))
(getter (trunc QI R0l))
(setter (set R0l newval))
)
(define-derived-operand
(name dst32-2-S-R0-direct-HI)
(comment "m32c R0 direct HI")
(attrs (machine 32))
(mode HI)
(args (R0))
(syntax "r0")
(base-ifield f-2-2)
(encoding (+ (f-2-2 0)))
(ifield-assertion (eq f-2-2 0))
(getter (trunc HI R0))
(setter (set R0 newval))
)
(define-derived-operand
(name dst32-1-S-A0-direct-HI)
(comment "m32c A0 direct HI")
(attrs (machine 32))
(mode HI)
(args (A0))
(syntax "a0")
(base-ifield f-7-1)
(encoding (+ (f-7-1 0)))
(ifield-assertion (eq f-7-1 0))
(getter (trunc HI A0))
(setter (set A0 newval))
)
(define-derived-operand
(name dst32-1-S-A1-direct-HI)
(comment "m32c A1 direct HI")
(attrs (machine 32))
(mode HI)
(args (A1))
(syntax "a1")
(base-ifield f-7-1)
(encoding (+ (f-7-1 1)))
(ifield-assertion (eq f-7-1 1))
(getter (trunc HI A1))
(setter (set A1 newval))
)
(define-pmacro (dst32-2-S-operands xmode)
(begin
(define-derived-operand
(name (.sym dst32-2-S-8-SB-relative- xmode))
(comment "m32c SB relative for short binary insns")
(attrs (machine 32))
(mode xmode)
(args (Dsp-8-u8))
(syntax "${Dsp-8-u8}[sb]")
(base-ifield f-2-2)
(encoding (+ (f-2-2 2) Dsp-8-u8))
(ifield-assertion (eq f-2-2 2))
(getter (c-call xmode (.str "operand_getter_" xmode) sb Dsp-8-u8))
(setter (c-call DFLT (.str "operand_setter_" xmode) newval sb Dsp-8-u8))
; (getter (mem32 xmode (add Dsp-8-u8 (reg h-sb))))
; (setter (set (mem32 xmode (add Dsp-8-u8 (reg h-sb))) newval))
)
(define-derived-operand
(name (.sym dst32-2-S-8-FB-relative- xmode))
(comment "m32c FB relative for short binary insns")
(attrs (machine 32))
(mode xmode)
(args (Dsp-8-s8))
(syntax "${Dsp-8-s8}[fb]")
(base-ifield f-2-2)
(encoding (+ (f-2-2 3) Dsp-8-s8))
(ifield-assertion (eq f-2-2 3))
(getter (c-call xmode (.str "operand_getter_" xmode) fb Dsp-8-s8))
(setter (c-call DFLT (.str "operand_setter_" xmode) newval fb Dsp-8-s8))
; (getter (mem32 xmode (add Dsp-8-s8 (reg h-fb))))
; (setter (set (mem32 xmode (add Dsp-8-s8 (reg h-fb))) newval))
)
(define-derived-operand
(name (.sym dst32-2-S-16-absolute- xmode))
(comment "m32c absolute address for short binary insns")
(attrs (machine 32))
(mode xmode)
(args (Dsp-8-u16))
(syntax "${Dsp-8-u16}")
(base-ifield f-2-2)
(encoding (+ (f-2-2 1) Dsp-8-u16))
(ifield-assertion (eq f-2-2 1))
(getter (c-call xmode (.str "operand_getter_" xmode) (const 0) Dsp-8-u16))
(setter (c-call DFLT (.str "operand_setter_" xmode) newval (const 0) Dsp-8-u16))
; (getter (mem32 xmode Dsp-8-u16))
; (setter (set (mem32 xmode Dsp-8-u16) newval))
)
; (define-derived-operand
; (name (.sym dst32-2-S-8-SB-relative-indirect- xmode))
; (comment "m32c SB relative for short binary insns")
; (attrs (machine 32))
; (mode xmode)
; (args (Dsp-16-u8))
; (syntax "[${Dsp-16-u8}[sb]]")
; (base-ifield f-10-2)
; (encoding (+ (f-10-2 2) Dsp-16-u8))
; (ifield-assertion (eq f-10-2 2))
; (getter (mem32 xmode (indirect-addr (add Dsp-16-u8 (reg h-sb)))))
; (setter (set (mem32 xmode (indirect-addr (add Dsp-16-u8 (reg h-sb)))) newval))
; )
; (define-derived-operand
; (name (.sym dst32-2-S-8-FB-relative-indirect- xmode))
; (comment "m32c FB relative for short binary insns")
; (attrs (machine 32))
; (mode xmode)
; (args (Dsp-16-s8))
; (syntax "[${Dsp-16-s8}[fb]]")
; (base-ifield f-10-2)
; (encoding (+ (f-10-2 3) Dsp-16-s8))
; (ifield-assertion (eq f-10-2 3))
; (getter (mem32 xmode (indirect-addr (add Dsp-16-s8 (reg h-fb)))))
; (setter (set (mem32 xmode (indirect-addr (add Dsp-16-s8 (reg h-fb)))) newval))
; )
; (define-derived-operand
; (name (.sym dst32-2-S-16-absolute-indirect- xmode))
; (comment "m32c absolute address for short binary insns")
; (attrs (machine 32))
; (mode xmode)
; (args (Dsp-16-u16))
; (syntax "[${Dsp-16-u16}]")
; (base-ifield f-10-2)
; (encoding (+ (f-10-2 1) Dsp-16-u16))
; (ifield-assertion (eq f-10-2 1))
; (getter (mem32 xmode (indirect-addr Dsp-16-u16)))
; (setter (set (mem32 xmode (indirect-addr Dsp-16-u16)) newval))
; )
)
)
(dst32-2-S-operands QI)
(dst32-2-S-operands HI)
(dst32-2-S-operands SI)
;=============================================================
; Anyof operands
;-------------------------------------------------------------
; Source operands with no additional fields
;-------------------------------------------------------------
(define-pmacro (src16-basic-operand xmode)
(begin
(define-anyof-operand
(name (.sym src16-basic- xmode))
(comment (.str "m16c source operand of size " xmode " with no additional fields"))
(attrs (machine 16))
(mode xmode)
(choices
(.sym src16-Rn-direct- xmode)
(.sym src16-An-direct- xmode)
(.sym src16-An-indirect- xmode)
)
)
)
)
(src16-basic-operand QI)
(src16-basic-operand HI)
(define-pmacro (src32-basic-operand xmode)
(begin
(define-anyof-operand
(name (.sym src32-basic-Unprefixed- xmode))
(comment (.str "m32c destination operand of size " xmode " with no additional fields"))
(attrs (machine 32))
(mode xmode)
(choices
(.sym src32-Rn-direct-Unprefixed- xmode)
(.sym src32-An-direct-Unprefixed- xmode)
(.sym src32-An-indirect-Unprefixed- xmode)
)
)
(define-anyof-operand
(name (.sym src32-basic-Prefixed- xmode))
(comment (.str "m32c destination operand of size " xmode " with no additional fields"))
(attrs (machine 32))
(mode xmode)
(choices
(.sym src32-Rn-direct-Prefixed- xmode)
(.sym src32-An-direct-Prefixed- xmode)
(.sym src32-An-indirect-Prefixed- xmode)
)
)
; (define-anyof-operand
; (name (.sym src32-basic-indirect- xmode))
; (comment (.str "m32c destination operand of size " xmode " indirect with no additional fields"))
; (attrs (machine 32))
; (mode xmode)
; (choices
; (.sym src32-An-indirect-indirect- xmode)
; )
; )
)
)
(src32-basic-operand QI)
(src32-basic-operand HI)
(src32-basic-operand SI)
(define-anyof-operand
(name src32-basic-ExtPrefixed-QI)
(comment "m32c source operand of size QI with no additional fields")
(attrs (machine 32))
(mode QI)
(choices
src32-Rn-direct-Prefixed-QI
src32-An-indirect-Prefixed-QI
)
)
;-------------------------------------------------------------
; Source operands with additional fields at offset 16 bits
;-------------------------------------------------------------
(define-pmacro (src16-16-operand xmode)
(begin
(define-anyof-operand
(name (.sym src16-16-8- xmode))
(comment (.str "m16c source operand of size " xmode " with additional 8 bit fields at offset 16"))
(attrs (machine 16))
(mode xmode)
(choices
(.sym src16-16-8-An-relative- xmode)
(.sym src16-16-8-SB-relative- xmode)
(.sym src16-16-8-FB-relative- xmode)
)
)
(define-anyof-operand
(name (.sym src16-16-16- xmode))
(comment (.str "m16c source operand of size " xmode " with additional 16 bit fields at offset 16"))
(attrs (machine 16))
(mode xmode)
(choices
(.sym src16-16-16-An-relative- xmode)
(.sym src16-16-16-SB-relative- xmode)
(.sym src16-16-16-absolute- xmode)
)
)
)
)
(src16-16-operand QI)
(src16-16-operand HI)
(define-pmacro (src32-16-operand xmode)
(begin
(define-anyof-operand
(name (.sym src32-16-8-Unprefixed- xmode))
(comment (.str "m32c source operand of size " xmode " with additional 8 bit fields at offset 16"))
(attrs (machine 32))
(mode xmode)
(choices
(.sym src32-16-8-An-relative-Unprefixed- xmode)
(.sym src32-16-8-SB-relative-Unprefixed- xmode)
(.sym src32-16-8-FB-relative-Unprefixed- xmode)
)
)
(define-anyof-operand
(name (.sym src32-16-16-Unprefixed- xmode))
(comment (.str "m32c source operand of size " xmode " with additional 16 bit fields at offset 16"))
(attrs (machine 32))
(mode xmode)
(choices
(.sym src32-16-16-An-relative-Unprefixed- xmode)
(.sym src32-16-16-SB-relative-Unprefixed- xmode)
(.sym src32-16-16-FB-relative-Unprefixed- xmode)
(.sym src32-16-16-absolute-Unprefixed- xmode)
)
)
(define-anyof-operand
(name (.sym src32-16-24-Unprefixed- xmode))
(comment (.str "m32c source operand of size " xmode " with additional 24 bit fields at offset 16"))
(attrs (machine 32))
(mode xmode)
(choices
(.sym src32-16-24-An-relative-Unprefixed- xmode)
(.sym src32-16-24-absolute-Unprefixed- xmode)
)
)
)
)
(src32-16-operand QI)
(src32-16-operand HI)
(src32-16-operand SI)
;-------------------------------------------------------------
; Source operands with additional fields at offset 24 bits
;-------------------------------------------------------------
(define-pmacro (src-24-operand group xmode)
(begin
(define-anyof-operand
(name (.sym src32-24-8- group - xmode))
(comment (.str "m32c source operand of size " xmode " with additional 8 bit fields at offset 24"))
(attrs (machine 32))
(mode xmode)
(choices
(.sym src32-24-8-An-relative- group - xmode)
(.sym src32-24-8-SB-relative- group - xmode)
(.sym src32-24-8-FB-relative- group - xmode)
)
)
(define-anyof-operand
(name (.sym src32-24-16- group - xmode))
(comment (.str "m32c source operand of size " xmode " with additional 16 bit fields at offset 16"))
(attrs (machine 32))
(mode xmode)
(choices
(.sym src32-24-16-An-relative- group - xmode)
(.sym src32-24-16-SB-relative- group - xmode)
(.sym src32-24-16-FB-relative- group - xmode)
(.sym src32-24-16-absolute- group - xmode)
)
)
(define-anyof-operand
(name (.sym src32-24-24- group - xmode))
(comment (.str "m32c source operand of size " xmode " with additional 24 bit fields at offset 16"))
(attrs (machine 32))
(mode xmode)
(choices
(.sym src32-24-24-An-relative- group - xmode)
(.sym src32-24-24-absolute- group - xmode)
)
)
)
)
(src-24-operand Prefixed QI)
(src-24-operand Prefixed HI)
(src-24-operand Prefixed SI)
(define-pmacro (src-24-indirect-operand xmode)
(begin
; (define-anyof-operand
; (name (.sym src32-24-8-indirect- xmode))
; (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24"))
; (attrs (machine 32))
; (mode xmode)
; (choices
; (.sym src32-24-8-An-relative-indirect- xmode)
; (.sym src32-24-8-SB-relative-indirect- xmode)
; (.sym src32-24-8-FB-relative-indirect- xmode)
; )
; )
; (define-anyof-operand
; (name (.sym src32-24-16-indirect- xmode))
; (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24"))
; (attrs (machine 32))
; (mode xmode)
; (choices
; (.sym src32-24-16-An-relative-indirect- xmode)
; (.sym src32-24-16-SB-relative-indirect- xmode)
; (.sym src32-24-16-FB-relative-indirect- xmode)
; )
; )
; (define-anyof-operand
; (name (.sym src32-24-24-indirect- xmode))
; (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24"))
; (attrs (machine 32))
; (mode xmode)
; (choices
; (.sym src32-24-24-An-relative-indirect- xmode)
; )
; )
; (define-anyof-operand
; (name (.sym src32-24-16-absolute-indirect- xmode))
; (comment (.str "m32c source operand of size " xmode " 16 bit absolute indirect"))
; (attrs (machine 32))
; (mode xmode)
; (choices
; (.sym src32-24-16-absolute-indirect-derived- xmode)
; )
; )
; (define-anyof-operand
; (name (.sym src32-24-24-absolute-indirect- xmode))
; (comment (.str "m32c source operand of size " xmode " 24 bit absolute indirect"))
; (attrs (machine 32))
; (mode xmode)
; (choices
; (.sym src32-24-24-absolute-indirect-derived- xmode)
; )
; )
)
)
; (src-24-indirect-operand QI)
; (src-24-indirect-operand HI)
; (src-24-indirect-operand SI)
;-------------------------------------------------------------
; Destination operands with no additional fields
;-------------------------------------------------------------
(define-pmacro (dst16-basic-operand xmode)
(begin
(define-anyof-operand
(name (.sym dst16-basic- xmode))
(comment (.str "m16c destination operand of size " xmode " with no additional fields"))
(attrs (machine 16))
(mode xmode)
(choices
(.sym dst16-Rn-direct- xmode)
(.sym dst16-An-direct- xmode)
(.sym dst16-An-indirect- xmode)
)
)
)
)
(dst16-basic-operand QI)
(dst16-basic-operand HI)
(dst16-basic-operand SI)
(define-pmacro (dst32-basic-operand xmode)
(begin
(define-anyof-operand
(name (.sym dst32-basic-Unprefixed- xmode))
(comment (.str "m32c destination operand of size " xmode " with no additional fields"))
(attrs (machine 32))
(mode xmode)
(choices
(.sym dst32-Rn-direct-Unprefixed- xmode)
(.sym dst32-An-direct-Unprefixed- xmode)
(.sym dst32-An-indirect-Unprefixed- xmode)
)
)
(define-anyof-operand
(name (.sym dst32-basic-Prefixed- xmode))
(comment (.str "m32c destination operand of size " xmode " with no additional fields"))
(attrs (machine 32))
(mode xmode)
(choices
(.sym dst32-Rn-direct-Prefixed- xmode)
(.sym dst32-An-direct-Prefixed- xmode)
(.sym dst32-An-indirect-Prefixed- xmode)
)
)
)
)
(dst32-basic-operand QI)
(dst32-basic-operand HI)
(dst32-basic-operand SI)
;-------------------------------------------------------------
; Destination operands with possible additional fields at offset 16 bits
;-------------------------------------------------------------
(define-pmacro (dst16-16-operand xmode)
(begin
(define-anyof-operand
(name (.sym dst16-16- xmode))
(comment (.str "m16c destination operand of size " xmode " with additional fields at offset 16"))
(attrs (machine 16))
(mode xmode)
(choices
(.sym dst16-Rn-direct- xmode)
(.sym dst16-An-direct- xmode)
(.sym dst16-An-indirect- xmode)
(.sym dst16-16-8-An-relative- xmode)
(.sym dst16-16-16-An-relative- xmode)
(.sym dst16-16-8-SB-relative- xmode)
(.sym dst16-16-16-SB-relative- xmode)
(.sym dst16-16-8-FB-relative- xmode)
(.sym dst16-16-16-absolute- xmode)
)
)
(define-anyof-operand
(name (.sym dst16-16-8- xmode))
(comment (.str "m16c destination operand of size " xmode " with additional fields at offset 16"))
(attrs (machine 16))
(mode xmode)
(choices
(.sym dst16-16-8-An-relative- xmode)
(.sym dst16-16-8-SB-relative- xmode)
(.sym dst16-16-8-FB-relative- xmode)
)
)
(define-anyof-operand
(name (.sym dst16-16-16- xmode))
(comment (.str "m16c destination operand of size " xmode " with additional fields at offset 16"))
(attrs (machine 16))
(mode xmode)
(choices
(.sym dst16-16-16-An-relative- xmode)
(.sym dst16-16-16-SB-relative- xmode)
(.sym dst16-16-16-absolute- xmode)
)
)
)
)
(dst16-16-operand QI)
(dst16-16-operand HI)
(dst16-16-operand SI)
(define-anyof-operand
(name dst16-16-Ext-QI)
(comment "m16c destination operand of size QI for 'ext' insns with additional fields at offset 16")
(attrs (machine 16))
(mode QI)
(choices
dst16-Rn-direct-Ext-QI
dst16-An-indirect-Ext-QI
dst16-16-8-An-relative-Ext-QI
dst16-16-16-An-relative-Ext-QI
dst16-16-8-SB-relative-Ext-QI
dst16-16-16-SB-relative-Ext-QI
dst16-16-8-FB-relative-Ext-QI
dst16-16-16-absolute-Ext-QI
)
)
(define-derived-operand
(name dst16-An-indirect-Mova-HI)
(comment "m16c addressof An indirect destination HI")
(attrs (ISA m16c))
(mode HI)
(args (Dst16An))
(syntax "[$Dst16An]")
(base-ifield f-12-4)
(encoding (+ (f-12-2 1) (f-14-1 1) Dst16An))
(ifield-assertion
(andif (eq f-12-2 1) (eq f-14-1 1)))
(getter Dst16An)
(setter (nop))
)
(define-derived-operand
(name dst16-16-8-An-relative-Mova-HI)
(comment
"m16c addressof dsp:8[An] relative destination HI")
(attrs (ISA m16c))
(mode HI)
(args (Dst16An Dsp-16-u8))
(syntax "${Dsp-16-u8}[$Dst16An]")
(base-ifield f-12-4)
(encoding
(+ (f-12-2 2) (f-14-1 0) Dsp-16-u8 Dst16An))
(ifield-assertion
(andif (eq f-12-2 2) (eq f-14-1 0)))
(getter (add Dsp-16-u8 Dst16An))
(setter (nop))
)
(define-derived-operand
(name dst16-16-16-An-relative-Mova-HI)
(comment
"m16c addressof dsp:16[An] relative destination HI")
(attrs (ISA m16c))
(mode HI)
(args (Dst16An Dsp-16-u16))
(syntax "${Dsp-16-u16}[$Dst16An]")
(base-ifield f-12-4)
(encoding
(+ (f-12-2 3) (f-14-1 0) Dsp-16-u16 Dst16An))
(ifield-assertion
(andif (eq f-12-2 3) (eq f-14-1 0)))
(getter (add Dsp-16-u16 Dst16An))
(setter (nop))
)
(define-derived-operand
(name dst16-16-8-SB-relative-Mova-HI)
(comment
"m16c addressof dsp:8[sb] relative destination HI")
(attrs (ISA m16c))
(mode HI)
(args (Dsp-16-u8))
(syntax "${Dsp-16-u8}[sb]")
(base-ifield f-12-4)
(encoding (+ (f-12-4 10) Dsp-16-u8))
(ifield-assertion (eq f-12-4 10))
(getter (add Dsp-16-u8 (reg h-sb)))
(setter (nop))
)
(define-derived-operand
(name dst16-16-16-SB-relative-Mova-HI)
(comment
"m16c addressof dsp:16[sb] relative destination HI")
(attrs (ISA m16c))
(mode HI)
(args (Dsp-16-u16))
(syntax "${Dsp-16-u16}[sb]")
(base-ifield f-12-4)
(encoding (+ (f-12-4 14) Dsp-16-u16))
(ifield-assertion (eq f-12-4 14))
(getter (add Dsp-16-u16 (reg h-sb)))
(setter (nop))
)
(define-derived-operand
(name dst16-16-8-FB-relative-Mova-HI)
(comment
"m16c addressof dsp:8[fb] relative destination HI")
(attrs (ISA m16c))
(mode HI)
(args (Dsp-16-s8))
(syntax "${Dsp-16-s8}[fb]")
(base-ifield f-12-4)
(encoding (+ (f-12-4 11) Dsp-16-s8))
(ifield-assertion (eq f-12-4 11))
(getter (add Dsp-16-s8 (reg h-fb)))
(setter (nop))
)
(define-derived-operand
(name dst16-16-16-absolute-Mova-HI)
(comment "m16c addressof absolute address HI")
(attrs (ISA m16c))
(mode HI)
(args (Dsp-16-u16))
(syntax "${Dsp-16-u16}")
(base-ifield f-12-4)
(encoding (+ (f-12-4 15) Dsp-16-u16))
(ifield-assertion (eq f-12-4 15))
(getter Dsp-16-u16)
(setter (nop))
)
(define-anyof-operand
(name dst16-16-Mova-HI)
(comment "m16c addressof destination operand of size HI with additional fields at offset 16")
(attrs (machine 16))
(mode HI)
(choices
dst16-An-indirect-Mova-HI
dst16-16-8-An-relative-Mova-HI
dst16-16-16-An-relative-Mova-HI
dst16-16-8-SB-relative-Mova-HI
dst16-16-16-SB-relative-Mova-HI
dst16-16-8-FB-relative-Mova-HI
dst16-16-16-absolute-Mova-HI
)
)
(define-derived-operand
(name dst32-An-indirect-Unprefixed-Mova-SI)
(comment "m32c addressof An indirect destination SI")
(attrs (ISA m32c))
(mode SI)
(args (Dst32AnUnprefixed))
(syntax "[$Dst32AnUnprefixed]")
(base-ifield f-4-6)
(encoding
(+ (f-4-3 0) (f-8-1 0) Dst32AnUnprefixed))
(ifield-assertion
(andif (eq f-4-3 0) (eq f-8-1 0)))
(getter Dst32AnUnprefixed)
(setter (nop))
)
(define-derived-operand
(name dst32-16-8-An-relative-Unprefixed-Mova-SI)
(comment "m32c addressof dsp:8[An] relative destination SI")
(attrs (ISA m32c))
(mode SI)
(args (Dst32AnUnprefixed Dsp-16-u8))
(syntax "${Dsp-16-u8}[$Dst32AnUnprefixed]")
(base-ifield f-4-6)
(encoding
(+ (f-4-3 1)
(f-8-1 0)
Dsp-16-u8
Dst32AnUnprefixed))
(ifield-assertion
(andif (eq f-4-3 1) (eq f-8-1 0)))
(getter (add Dsp-16-u8 Dst32AnUnprefixed))
(setter (nop))
)
(define-derived-operand
(name dst32-16-16-An-relative-Unprefixed-Mova-SI)
(comment
"m32c addressof dsp:16[An] relative destination SI")
(attrs (ISA m32c))
(mode SI)
(args (Dst32AnUnprefixed Dsp-16-u16))
(syntax "${Dsp-16-u16}[$Dst32AnUnprefixed]")
(base-ifield f-4-6)
(encoding
(+ (f-4-3 2)
(f-8-1 0)
Dsp-16-u16
Dst32AnUnprefixed))
(ifield-assertion
(andif (eq f-4-3 2) (eq f-8-1 0)))
(getter (add Dsp-16-u16 Dst32AnUnprefixed))
(setter (nop))
)
(define-derived-operand
(name dst32-16-24-An-relative-Unprefixed-Mova-SI)
(comment "addressof m32c dsp:16[An] relative destination SI")
(attrs (ISA m32c))
(mode SI)
(args (Dst32AnUnprefixed Dsp-16-u24))
(syntax "${Dsp-16-u24}[$Dst32AnUnprefixed]")
(base-ifield f-4-6)
(encoding
(+ (f-4-3 3)
(f-8-1 0)
Dsp-16-u24
Dst32AnUnprefixed))
(ifield-assertion
(andif (eq f-4-3 3) (eq f-8-1 0)))
(getter (add Dsp-16-u24 Dst32AnUnprefixed))
(setter (nop))
)
(define-derived-operand
(name dst32-16-8-SB-relative-Unprefixed-Mova-SI)
(comment "m32c addressof dsp:8[sb] relative destination SI")
(attrs (ISA m32c))
(mode SI)
(args (Dsp-16-u8))
(syntax "${Dsp-16-u8}[sb]")
(base-ifield f-4-6)
(encoding (+ (f-4-3 1) (f-8-2 2) Dsp-16-u8))
(ifield-assertion
(andif (eq f-4-3 1) (eq f-8-2 2)))
(getter (add Dsp-16-u8 (reg h-sb)))
(setter (nop))
)
(define-derived-operand
(name dst32-16-16-SB-relative-Unprefixed-Mova-SI)
(comment "m32c addressof dsp:16[sb] relative destination SI")
(attrs (ISA m32c))
(mode SI)
(args (Dsp-16-u16))
(syntax "${Dsp-16-u16}[sb]")
(base-ifield f-4-6)
(encoding (+ (f-4-3 2) (f-8-2 2) Dsp-16-u16))
(ifield-assertion
(andif (eq f-4-3 2) (eq f-8-2 2)))
(getter (add Dsp-16-u16 (reg h-sb)))
(setter (nop))
)
(define-derived-operand
(name dst32-16-8-FB-relative-Unprefixed-Mova-SI)
(comment "m32c addressof dsp:8[fb] relative destination SI")
(attrs (ISA m32c))
(mode SI)
(args (Dsp-16-s8))
(syntax "${Dsp-16-s8}[fb]")
(base-ifield f-4-6)
(encoding (+ (f-4-3 1) (f-8-2 3) Dsp-16-s8))
(ifield-assertion
(andif (eq f-4-3 1) (eq f-8-2 3)))
(getter (add Dsp-16-s8 (reg h-fb)))
(setter (nop))
)
(define-derived-operand
(name dst32-16-16-FB-relative-Unprefixed-Mova-SI)
(comment "m32c addressof dsp:16[fb] relative destination SI")
(attrs (ISA m32c))
(mode SI)
(args (Dsp-16-s16))
(syntax "${Dsp-16-s16}[fb]")
(base-ifield f-4-6)
(encoding (+ (f-4-3 2) (f-8-2 3) Dsp-16-s16))
(ifield-assertion
(andif (eq f-4-3 2) (eq f-8-2 3)))
(getter (add Dsp-16-s16 (reg h-fb)))
(setter (nop))
)
(define-derived-operand
(name dst32-16-16-absolute-Unprefixed-Mova-SI)
(comment "m32c addressof absolute address SI") (attrs (ISA m32c))
(mode SI)
(args (Dsp-16-u16))
(syntax "${Dsp-16-u16}")
(base-ifield f-4-6)
(encoding (+ (f-4-3 3) (f-8-2 3) Dsp-16-u16))
(ifield-assertion
(andif (eq f-4-3 3) (eq f-8-2 3)))
(getter Dsp-16-u16)
(setter (nop))
)
(define-derived-operand
(name dst32-16-24-absolute-Unprefixed-Mova-SI)
(comment "m32c addressof absolute address SI") (attrs (ISA m32c))
(mode SI)
(args (Dsp-16-u24))
(syntax "${Dsp-16-u24}")
(base-ifield f-4-6)
(encoding (+ (f-4-3 3) (f-8-2 2) Dsp-16-u24))
(ifield-assertion
(andif (eq f-4-3 3) (eq f-8-2 2)))
(getter Dsp-16-u24)
(setter (nop))
)
(define-anyof-operand
(name dst32-16-Unprefixed-Mova-SI)
(comment
"m32c addressof destination operand of size SI with additional fields at offset 16")
(attrs (ISA m32c))
(mode SI)
(choices
dst32-An-indirect-Unprefixed-Mova-SI
dst32-16-8-An-relative-Unprefixed-Mova-SI
dst32-16-16-An-relative-Unprefixed-Mova-SI
dst32-16-24-An-relative-Unprefixed-Mova-SI
dst32-16-8-SB-relative-Unprefixed-Mova-SI
dst32-16-16-SB-relative-Unprefixed-Mova-SI
dst32-16-8-FB-relative-Unprefixed-Mova-SI
dst32-16-16-FB-relative-Unprefixed-Mova-SI
dst32-16-16-absolute-Unprefixed-Mova-SI
dst32-16-24-absolute-Unprefixed-Mova-SI))
(define-pmacro (dst32-16-operand xmode)
(begin
(define-anyof-operand
(name (.sym dst32-16-Unprefixed- xmode))
(comment (.str "m32c destination operand of size " xmode " with additional fields at offset 16"))
(attrs (machine 32))
(mode xmode)
(choices
(.sym dst32-Rn-direct-Unprefixed- xmode)
(.sym dst32-An-direct-Unprefixed- xmode)
(.sym dst32-An-indirect-Unprefixed- xmode)
(.sym dst32-16-8-An-relative-Unprefixed- xmode)
(.sym dst32-16-16-An-relative-Unprefixed- xmode)
(.sym dst32-16-24-An-relative-Unprefixed- xmode)
(.sym dst32-16-8-SB-relative-Unprefixed- xmode)
(.sym dst32-16-16-SB-relative-Unprefixed- xmode)
(.sym dst32-16-8-FB-relative-Unprefixed- xmode)
(.sym dst32-16-16-FB-relative-Unprefixed- xmode)
(.sym dst32-16-16-absolute-Unprefixed- xmode)
(.sym dst32-16-24-absolute-Unprefixed- xmode)
)
)
(define-anyof-operand
(name (.sym dst32-16-8-Unprefixed- xmode))
(comment (.str "m32c destination operand of size " xmode " with additional fields at offset 16"))
(attrs (machine 32))
(mode xmode)
(choices
(.sym dst32-16-8-An-relative-Unprefixed- xmode)
(.sym dst32-16-8-SB-relative-Unprefixed- xmode)
(.sym dst32-16-8-FB-relative-Unprefixed- xmode)
)
)
(define-anyof-operand
(name (.sym dst32-16-16-Unprefixed- xmode))
(comment (.str "m32c destination operand of size " xmode " with additional fields at offset 16"))
(attrs (machine 32))
(mode xmode)
(choices
(.sym dst32-16-16-An-relative-Unprefixed- xmode)
(.sym dst32-16-16-SB-relative-Unprefixed- xmode)
(.sym dst32-16-16-FB-relative-Unprefixed- xmode)
(.sym dst32-16-16-absolute-Unprefixed- xmode)
)
)
(define-anyof-operand
(name (.sym dst32-16-24-Unprefixed- xmode))
(comment (.str "m32c destination operand of size " xmode " with additional fields at offset 16"))
(attrs (machine 32))
(mode xmode)
(choices
(.sym dst32-16-24-An-relative-Unprefixed- xmode)
(.sym dst32-16-24-absolute-Unprefixed- xmode)
)
)
)
)
(dst32-16-operand QI)
(dst32-16-operand HI)
(dst32-16-operand SI)
(define-pmacro (dst32-16-Ext-operand smode dmode)
(begin
(define-anyof-operand
(name (.sym dst32-16-ExtUnprefixed- smode))
(comment (.str "m32c destination operand of size " smode " with additional fields at offset 16"))
(attrs (machine 32))
(mode dmode)
(choices
(.sym dst32-Rn-direct-ExtUnprefixed- smode)
(.sym dst32-An-direct-Unprefixed- dmode) ; ExtUnprefixed mode not required for this operand -- use the normal dmode version
(.sym dst32-An-indirect-ExtUnprefixed- smode)
(.sym dst32-16-8-An-relative-ExtUnprefixed- smode)
(.sym dst32-16-16-An-relative-ExtUnprefixed- smode)
(.sym dst32-16-24-An-relative-ExtUnprefixed- smode)
(.sym dst32-16-8-SB-relative-ExtUnprefixed- smode)
(.sym dst32-16-16-SB-relative-ExtUnprefixed- smode)
(.sym dst32-16-8-FB-relative-ExtUnprefixed- smode)
(.sym dst32-16-16-FB-relative-ExtUnprefixed- smode)
(.sym dst32-16-16-absolute-ExtUnprefixed- smode)
(.sym dst32-16-24-absolute-ExtUnprefixed- smode)
)
)
)
)
(dst32-16-Ext-operand QI HI)
(dst32-16-Ext-operand HI SI)
(define-anyof-operand
(name dst32-16-Unprefixed-Mulex-HI)
(comment "m32c destination operand of size HI with additional fields at offset 16")
(attrs (machine 32))
(mode HI)
(choices
dst32-R3-direct-Unprefixed-HI
dst32-An-direct-Unprefixed-HI
dst32-An-indirect-Unprefixed-HI
dst32-16-8-An-relative-Unprefixed-HI
dst32-16-16-An-relative-Unprefixed-HI
dst32-16-24-An-relative-Unprefixed-HI
dst32-16-8-SB-relative-Unprefixed-HI
dst32-16-16-SB-relative-Unprefixed-HI
dst32-16-8-FB-relative-Unprefixed-HI
dst32-16-16-FB-relative-Unprefixed-HI
dst32-16-16-absolute-Unprefixed-HI
dst32-16-24-absolute-Unprefixed-HI
)
)
;-------------------------------------------------------------
; Destination operands with possible additional fields at offset 24 bits
;-------------------------------------------------------------
(define-pmacro (dst16-24-operand xmode)
(begin
(define-anyof-operand
(name (.sym dst16-24- xmode))
(comment (.str "m16c destination operand of size " xmode " with additional fields at offset 24"))
(attrs (machine 16))
(mode xmode)
(choices
(.sym dst16-Rn-direct- xmode)
(.sym dst16-An-direct- xmode)
(.sym dst16-An-indirect- xmode)
(.sym dst16-24-8-An-relative- xmode)
(.sym dst16-24-16-An-relative- xmode)
(.sym dst16-24-8-SB-relative- xmode)
(.sym dst16-24-16-SB-relative- xmode)
(.sym dst16-24-8-FB-relative- xmode)
(.sym dst16-24-16-absolute- xmode)
)
)
)
)
(dst16-24-operand QI)
(dst16-24-operand HI)
(define-pmacro (dst32-24-operand xmode)
(begin
(define-anyof-operand
(name (.sym dst32-24-Unprefixed- xmode))
(comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24"))
(attrs (machine 32))
(mode xmode)
(choices
(.sym dst32-Rn-direct-Unprefixed- xmode)
(.sym dst32-An-direct-Unprefixed- xmode)
(.sym dst32-An-indirect-Unprefixed- xmode)
(.sym dst32-24-8-An-relative-Unprefixed- xmode)
(.sym dst32-24-16-An-relative-Unprefixed- xmode)
(.sym dst32-24-24-An-relative-Unprefixed- xmode)
(.sym dst32-24-8-SB-relative-Unprefixed- xmode)
(.sym dst32-24-16-SB-relative-Unprefixed- xmode)
(.sym dst32-24-8-FB-relative-Unprefixed- xmode)
(.sym dst32-24-16-FB-relative-Unprefixed- xmode)
(.sym dst32-24-16-absolute-Unprefixed- xmode)
(.sym dst32-24-24-absolute-Unprefixed- xmode)
)
)
(define-anyof-operand
(name (.sym dst32-24-Prefixed- xmode))
(comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24"))
(attrs (machine 32))
(mode xmode)
(choices
(.sym dst32-Rn-direct-Prefixed- xmode)
(.sym dst32-An-direct-Prefixed- xmode)
(.sym dst32-An-indirect-Prefixed- xmode)
(.sym dst32-24-8-An-relative-Prefixed- xmode)
(.sym dst32-24-16-An-relative-Prefixed- xmode)
(.sym dst32-24-24-An-relative-Prefixed- xmode)
(.sym dst32-24-8-SB-relative-Prefixed- xmode)
(.sym dst32-24-16-SB-relative-Prefixed- xmode)
(.sym dst32-24-8-FB-relative-Prefixed- xmode)
(.sym dst32-24-16-FB-relative-Prefixed- xmode)
(.sym dst32-24-16-absolute-Prefixed- xmode)
(.sym dst32-24-24-absolute-Prefixed- xmode)
)
)
(define-anyof-operand
(name (.sym dst32-24-8-Prefixed- xmode))
(comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24"))
(attrs (machine 32))
(mode xmode)
(choices
(.sym dst32-24-8-An-relative-Prefixed- xmode)
(.sym dst32-24-8-SB-relative-Prefixed- xmode)
(.sym dst32-24-8-FB-relative-Prefixed- xmode)
)
)
(define-anyof-operand
(name (.sym dst32-24-16-Prefixed- xmode))
(comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24"))
(attrs (machine 32))
(mode xmode)
(choices
(.sym dst32-24-16-An-relative-Prefixed- xmode)
(.sym dst32-24-16-SB-relative-Prefixed- xmode)
(.sym dst32-24-16-FB-relative-Prefixed- xmode)
(.sym dst32-24-16-absolute-Prefixed- xmode)
)
)
(define-anyof-operand
(name (.sym dst32-24-24-Prefixed- xmode))
(comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24"))
(attrs (machine 32))
(mode xmode)
(choices
(.sym dst32-24-24-An-relative-Prefixed- xmode)
(.sym dst32-24-24-absolute-Prefixed- xmode)
)
)
; (define-anyof-operand
; (name (.sym dst32-24-indirect- xmode))
; (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24"))
; (attrs (machine 32))
; (mode xmode)
; (choices
; (.sym dst32-An-indirect-indirect- xmode)
; (.sym dst32-24-8-An-relative-indirect- xmode)
; (.sym dst32-24-16-An-relative-indirect- xmode)
; (.sym dst32-24-24-An-relative-indirect- xmode)
; (.sym dst32-24-8-SB-relative-indirect- xmode)
; (.sym dst32-24-16-SB-relative-indirect- xmode)
; (.sym dst32-24-8-FB-relative-indirect- xmode)
; (.sym dst32-24-16-FB-relative-indirect- xmode)
; )
; )
; (define-anyof-operand
; (name (.sym dst32-basic-indirect- xmode))
; (comment (.str "m32c destination operand of size " xmode " with no additional fields"))
; (attrs (machine 32))
; (mode xmode)
; (choices
; (.sym dst32-An-indirect-indirect- xmode)
; )
; )
; (define-anyof-operand
; (name (.sym dst32-24-8-indirect- xmode))
; (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24"))
; (attrs (machine 32))
; (mode xmode)
; (choices
; (.sym dst32-24-8-An-relative-indirect- xmode)
; (.sym dst32-24-8-SB-relative-indirect- xmode)
; (.sym dst32-24-8-FB-relative-indirect- xmode)
; )
; )
; (define-anyof-operand
; (name (.sym dst32-24-16-indirect- xmode))
; (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24"))
; (attrs (machine 32))
; (mode xmode)
; (choices
; (.sym dst32-24-16-An-relative-indirect- xmode)
; (.sym dst32-24-16-SB-relative-indirect- xmode)
; (.sym dst32-24-16-FB-relative-indirect- xmode)
; )
; )
; (define-anyof-operand
; (name (.sym dst32-24-24-indirect- xmode))
; (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 24"))
; (attrs (machine 32))
; (mode xmode)
; (choices
; (.sym dst32-24-24-An-relative-indirect- xmode)
; )
; )
; (define-anyof-operand
; (name (.sym dst32-24-absolute-indirect- xmode))
; (comment (.str "m32c destination operand of size " xmode " absolute indirect"))
; (attrs (machine 32))
; (mode xmode)
; (choices
; (.sym dst32-24-16-absolute-indirect-derived- xmode)
; (.sym dst32-24-24-absolute-indirect-derived- xmode)
; )
; )
; (define-anyof-operand
; (name (.sym dst32-24-16-absolute-indirect- xmode))
; (comment (.str "m32c destination operand of size " xmode " absolute indirect"))
; (attrs (machine 32))
; (mode xmode)
; (choices
; (.sym dst32-24-16-absolute-indirect-derived- xmode)
; )
; )
; (define-anyof-operand
; (name (.sym dst32-24-24-absolute-indirect- xmode))
; (comment (.str "m32c destination operand of size " xmode " absolute indirect"))
; (attrs (machine 32))
; (mode xmode)
; (choices
; (.sym dst32-24-24-absolute-indirect-derived- xmode)
; )
; )
)
)
(dst32-24-operand QI)
(dst32-24-operand HI)
(dst32-24-operand SI)
;-------------------------------------------------------------
; Destination operands with possible additional fields at offset 32 bits
;-------------------------------------------------------------
(define-pmacro (dst16-32-operand xmode)
(begin
(define-anyof-operand
(name (.sym dst16-32- xmode))
(comment (.str "m16c destination operand of size " xmode " with additional fields at offset 32"))
(attrs (machine 16))
(mode xmode)
(choices
(.sym dst16-Rn-direct- xmode)
(.sym dst16-An-direct- xmode)
(.sym dst16-An-indirect- xmode)
(.sym dst16-32-8-An-relative- xmode)
(.sym dst16-32-16-An-relative- xmode)
(.sym dst16-32-8-SB-relative- xmode)
(.sym dst16-32-16-SB-relative- xmode)
(.sym dst16-32-8-FB-relative- xmode)
(.sym dst16-32-16-absolute- xmode)
)
)
)
)
(dst16-32-operand QI)
(dst16-32-operand HI)
; This macro actually handles operands at offset 32, 40 and 48 bits
(define-pmacro (dst32-32plus-operand offset xmode)
(begin
(define-anyof-operand
(name (.sym dst32- offset -Unprefixed- xmode))
(comment (.str "m32c destination operand of size " xmode " with additional fields at offset 32"))
(attrs (machine 32))
(mode xmode)
(choices
(.sym dst32-Rn-direct-Unprefixed- xmode)
(.sym dst32-An-direct-Unprefixed- xmode)
(.sym dst32-An-indirect-Unprefixed- xmode)
(.sym dst32- offset -8-An-relative-Unprefixed- xmode)
(.sym dst32- offset -16-An-relative-Unprefixed- xmode)
(.sym dst32- offset -24-An-relative-Unprefixed- xmode)
(.sym dst32- offset -8-SB-relative-Unprefixed- xmode)
(.sym dst32- offset -16-SB-relative-Unprefixed- xmode)
(.sym dst32- offset -8-FB-relative-Unprefixed- xmode)
(.sym dst32- offset -16-FB-relative-Unprefixed- xmode)
(.sym dst32- offset -16-absolute-Unprefixed- xmode)
(.sym dst32- offset -24-absolute-Unprefixed- xmode)
)
)
(define-anyof-operand
(name (.sym dst32- offset -Prefixed- xmode))
(comment (.str "m32c destination operand of size " xmode " with additional fields at offset 32"))
(attrs (machine 32))
(mode xmode)
(choices
(.sym dst32-Rn-direct-Prefixed- xmode)
(.sym dst32-An-direct-Prefixed- xmode)
(.sym dst32-An-indirect-Prefixed- xmode)
(.sym dst32- offset -8-An-relative-Prefixed- xmode)
(.sym dst32- offset -16-An-relative-Prefixed- xmode)
(.sym dst32- offset -24-An-relative-Prefixed- xmode)
(.sym dst32- offset -8-SB-relative-Prefixed- xmode)
(.sym dst32- offset -16-SB-relative-Prefixed- xmode)
(.sym dst32- offset -8-FB-relative-Prefixed- xmode)
(.sym dst32- offset -16-FB-relative-Prefixed- xmode)
(.sym dst32- offset -16-absolute-Prefixed- xmode)
(.sym dst32- offset -24-absolute-Prefixed- xmode)
)
)
; (define-anyof-operand
; (name (.sym dst32- offset -indirect- xmode))
; (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 32"))
; (attrs (machine 32))
; (mode xmode)
; (choices
; (.sym dst32-An-indirect-indirect- xmode)
; (.sym dst32- offset -8-An-relative-indirect- xmode)
; (.sym dst32- offset -16-An-relative-indirect- xmode)
; (.sym dst32- offset -24-An-relative-indirect- xmode)
; (.sym dst32- offset -8-SB-relative-indirect- xmode)
; (.sym dst32- offset -16-SB-relative-indirect- xmode)
; (.sym dst32- offset -8-FB-relative-indirect- xmode)
; (.sym dst32- offset -16-FB-relative-indirect- xmode)
; )
; )
; (define-anyof-operand
; (name (.sym dst32- offset -absolute-indirect- xmode))
; (comment (.str "m32c destination operand of size " xmode " absolute indirect"))
; (attrs (machine 32))
; (mode xmode)
; (choices
; (.sym dst32- offset -16-absolute-indirect-derived- xmode)
; (.sym dst32- offset -24-absolute-indirect-derived- xmode)
; )
; )
)
)
(dst32-32plus-operand 32 QI)
(dst32-32plus-operand 32 HI)
(dst32-32plus-operand 32 SI)
(dst32-32plus-operand 40 QI)
(dst32-32plus-operand 40 HI)
(dst32-32plus-operand 40 SI)
;-------------------------------------------------------------
; Destination operands with possible additional fields at offset 48 bits
;-------------------------------------------------------------
(define-pmacro (dst32-48-operand offset xmode)
(begin
(define-anyof-operand
(name (.sym dst32- offset -Prefixed- xmode))
(comment (.str "m32c destination operand of size " xmode " with additional fields at offset 32"))
(attrs (machine 32))
(mode xmode)
(choices
(.sym dst32-Rn-direct-Prefixed- xmode)
(.sym dst32-An-direct-Prefixed- xmode)
(.sym dst32-An-indirect-Prefixed- xmode)
(.sym dst32- offset -8-An-relative-Prefixed- xmode)
(.sym dst32- offset -16-An-relative-Prefixed- xmode)
(.sym dst32- offset -24-An-relative-Prefixed- xmode)
(.sym dst32- offset -8-SB-relative-Prefixed- xmode)
(.sym dst32- offset -16-SB-relative-Prefixed- xmode)
(.sym dst32- offset -8-FB-relative-Prefixed- xmode)
(.sym dst32- offset -16-FB-relative-Prefixed- xmode)
(.sym dst32- offset -16-absolute-Prefixed- xmode)
(.sym dst32- offset -24-absolute-Prefixed- xmode)
)
)
; (define-anyof-operand
; (name (.sym dst32- offset -indirect- xmode))
; (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 32"))
; (attrs (machine 32))
; (mode xmode)
; (choices
; (.sym dst32-An-indirect-indirect- xmode)
; (.sym dst32- offset -8-An-relative-indirect- xmode)
; (.sym dst32- offset -16-An-relative-indirect- xmode)
; (.sym dst32- offset -24-An-relative-indirect- xmode)
; (.sym dst32- offset -8-SB-relative-indirect- xmode)
; (.sym dst32- offset -16-SB-relative-indirect- xmode)
; (.sym dst32- offset -8-FB-relative-indirect- xmode)
; (.sym dst32- offset -16-FB-relative-indirect- xmode)
; )
; )
; (define-anyof-operand
; (name (.sym dst32- offset -absolute-indirect- xmode))
; (comment (.str "m32c destination operand of size " xmode " absolute indirect"))
; (attrs (machine 32))
; (mode xmode)
; (choices
; (.sym dst32- offset -16-absolute-indirect-derived- xmode)
; (.sym dst32- offset -24-absolute-indirect-derived- xmode)
; )
; )
)
)
(dst32-48-operand 48 QI)
(dst32-48-operand 48 HI)
(dst32-48-operand 48 SI)
;-------------------------------------------------------------
; Bit operands for m16c
;-------------------------------------------------------------
(define-pmacro (bit16-operand offset)
(begin
(define-anyof-operand
(name (.sym bit16- offset))
(comment (.str "m16c bit operand with possible additional fields at offset 24"))
(attrs (machine 16))
(mode BI)
(choices
bit16-Rn-direct
bit16-An-direct
bit16-An-indirect
(.sym bit16- offset -8-An-relative)
(.sym bit16- offset -16-An-relative)
(.sym bit16- offset -8-SB-relative)
(.sym bit16- offset -16-SB-relative)
(.sym bit16- offset -8-FB-relative)
(.sym bit16- offset -16-absolute)
)
)
(define-anyof-operand
(name (.sym bit16- offset -basic))
(comment (.str "m16c bit operand with no additional fields"))
(attrs (machine 16))
(mode BI)
(choices
bit16-An-indirect
)
)
(define-anyof-operand
(name (.sym bit16- offset -8))
(comment (.str "m16c bit operand with possible additional fields at offset 24"))
(attrs (machine 16))
(mode BI)
(choices
bit16-Rn-direct
bit16-An-direct
(.sym bit16- offset -8-An-relative)
(.sym bit16- offset -8-SB-relative)
(.sym bit16- offset -8-FB-relative)
)
)
(define-anyof-operand
(name (.sym bit16- offset -16))
(comment (.str "m16c bit operand with possible additional fields at offset 24"))
(attrs (machine 16))
(mode BI)
(choices
(.sym bit16- offset -16-An-relative)
(.sym bit16- offset -16-SB-relative)
(.sym bit16- offset -16-absolute)
)
)
)
)
(bit16-operand 16)
;-------------------------------------------------------------
; Bit operands for m32c
;-------------------------------------------------------------
(define-pmacro (bit32-operand offset group)
(begin
(define-anyof-operand
(name (.sym bit32- offset - group))
(comment (.str "m32c bit operand with possible additional fields at offset 24"))
(attrs (machine 32))
(mode BI)
(choices
(.sym bit32-Rn-direct- group)
(.sym bit32-An-direct- group)
(.sym bit32-An-indirect- group)
(.sym bit32- offset -11-An-relative- group)
(.sym bit32- offset -19-An-relative- group)
(.sym bit32- offset -27-An-relative- group)
(.sym bit32- offset -11-SB-relative- group)
(.sym bit32- offset -19-SB-relative- group)
(.sym bit32- offset -11-FB-relative- group)
(.sym bit32- offset -19-FB-relative- group)
(.sym bit32- offset -19-absolute- group)
(.sym bit32- offset -27-absolute- group)
)
)
)
)
(bit32-operand 16 Unprefixed)
(bit32-operand 24 Prefixed)
(define-anyof-operand
(name bit32-basic-Unprefixed)
(comment "m32c bit operand with no additional fields")
(attrs (machine 32))
(mode BI)
(choices
bit32-Rn-direct-Unprefixed
bit32-An-direct-Unprefixed
bit32-An-indirect-Unprefixed
)
)
(define-anyof-operand
(name bit32-16-8-Unprefixed)
(comment "m32c bit operand with 8 bit additional fields")
(attrs (machine 32))
(mode BI)
(choices
bit32-16-11-An-relative-Unprefixed
bit32-16-11-SB-relative-Unprefixed
bit32-16-11-FB-relative-Unprefixed
)
)
(define-anyof-operand
(name bit32-16-16-Unprefixed)
(comment "m32c bit operand with 16 bit additional fields")
(attrs (machine 32))
(mode BI)
(choices
bit32-16-19-An-relative-Unprefixed
bit32-16-19-SB-relative-Unprefixed
bit32-16-19-FB-relative-Unprefixed
bit32-16-19-absolute-Unprefixed
)
)
(define-anyof-operand
(name bit32-16-24-Unprefixed)
(comment "m32c bit operand with 24 bit additional fields")
(attrs (machine 32))
(mode BI)
(choices
bit32-16-27-An-relative-Unprefixed
bit32-16-27-absolute-Unprefixed
)
)
;-------------------------------------------------------------
; Operands for short format binary insns
;-------------------------------------------------------------
(define-anyof-operand
(name src16-2-S)
(comment "m16c source operand of size QI for short format insns")
(attrs (machine 16))
(mode QI)
(choices
src16-2-S-8-SB-relative-QI
src16-2-S-8-FB-relative-QI
src16-2-S-16-absolute-QI
)
)
(define-anyof-operand
(name src32-2-S-QI)
(comment "m32c source operand of size QI for short format insns")
(attrs (machine 32))
(mode QI)
(choices
src32-2-S-8-SB-relative-QI
src32-2-S-8-FB-relative-QI
src32-2-S-16-absolute-QI
)
)
(define-anyof-operand
(name src32-2-S-HI)
(comment "m32c source operand of size QI for short format insns")
(attrs (machine 32))
(mode HI)
(choices
src32-2-S-8-SB-relative-HI
src32-2-S-8-FB-relative-HI
src32-2-S-16-absolute-HI
)
)
(define-anyof-operand
(name Dst16-3-S-8)
(comment "m16c destination operand of size QI for short format insns")
(attrs (machine 16))
(mode QI)
(choices
dst16-3-S-R0l-direct-QI
dst16-3-S-R0h-direct-QI
dst16-3-S-8-8-SB-relative-QI
dst16-3-S-8-8-FB-relative-QI
dst16-3-S-8-16-absolute-QI
)
)
(define-anyof-operand
(name Dst16-3-S-16)
(comment "m16c destination operand of size QI for short format insns")
(attrs (machine 16))
(mode QI)
(choices
dst16-3-S-R0l-direct-QI
dst16-3-S-R0h-direct-QI
dst16-3-S-16-8-SB-relative-QI
dst16-3-S-16-8-FB-relative-QI
dst16-3-S-16-16-absolute-QI
)
)
(define-anyof-operand
(name srcdst16-r0l-r0h-S)
(comment "m16c r0l/r0h operand of size QI for short format insns")
(attrs (machine 16))
(mode SI)
(choices
srcdst16-r0l-r0h-S-derived
)
)
(define-anyof-operand
(name dst32-2-S-basic-QI)
(comment "m32c r0l operand of size QI for short format binary insns")
(attrs (machine 32))
(mode QI)
(choices
dst32-2-S-R0l-direct-QI
)
)
(define-anyof-operand
(name dst32-2-S-basic-HI)
(comment "m32c r0 operand of size HI for short format binary insns")
(attrs (machine 32))
(mode HI)
(choices
dst32-2-S-R0-direct-HI
)
)
(define-pmacro (dst32-2-S-operands xmode)
(begin
(define-anyof-operand
(name (.sym dst32-2-S-8- xmode))
(comment "m32c operand of size " xmode " for short format binary insns")
(attrs (machine 32))
(mode xmode)
(choices
(.sym dst32-2-S-8-SB-relative- xmode)
(.sym dst32-2-S-8-FB-relative- xmode)
)
)
(define-anyof-operand
(name (.sym dst32-2-S-16- xmode))
(comment "m32c operand of size " xmode " for short format binary insns")
(attrs (machine 32))
(mode xmode)
(choices
(.sym dst32-2-S-16-absolute- xmode)
)
)
; (define-anyof-operand
; (name (.sym dst32-2-S-8-indirect- xmode))
; (comment "m32c operand of size " xmode " for short format binary insns")
; (attrs (machine 32))
; (mode xmode)
; (choices
; (.sym dst32-2-S-8-SB-relative-indirect- xmode)
; (.sym dst32-2-S-8-FB-relative-indirect- xmode)
; )
; )
; (define-anyof-operand
; (name (.sym dst32-2-S-absolute-indirect- xmode))
; (comment "m32c operand of size " xmode " for short format binary insns")
; (attrs (machine 32))
; (mode xmode)
; (choices
; (.sym dst32-2-S-16-absolute-indirect- xmode)
; )
; )
)
)
(dst32-2-S-operands QI)
(dst32-2-S-operands HI)
(dst32-2-S-operands SI)
(define-anyof-operand
(name dst32-an-S)
(comment "m32c An operand for short format binary insns")
(attrs (machine 32))
(mode HI)
(choices
dst32-1-S-A0-direct-HI
dst32-1-S-A1-direct-HI
)
)
(define-anyof-operand
(name bit16-11-S)
(comment "m16c bit operand for short format insns")
(attrs (machine 16))
(mode BI)
(choices
bit16-11-SB-relative-S
)
)
(define-anyof-operand
(name Rn16-push-S-anyof)
(comment "m16c bit operand for short format insns")
(attrs (machine 16))
(mode QI)
(choices
Rn16-push-S-derived
)
)
(define-anyof-operand
(name An16-push-S-anyof)
(comment "m16c bit operand for short format insns")
(attrs (machine 16))
(mode HI)
(choices
An16-push-S-derived
)
)
;=============================================================
; Common macros for instruction definitions
;
(define-pmacro (set-z x)
(sequence ()
(set zbit (zflag x)))
)
(define-pmacro (set-s x)
(sequence ()
(set sbit (nflag x)))
)
(define-pmacro (set-z-and-s x)
(sequence ()
(set-z x)
(set-s x))
)
;=============================================================
; Unary insn macros
;-------------------------------------------------------------
(define-pmacro (unary-insn-defn-g mach group mode wstr op encoding sem opg)
(dni (.sym op mach wstr - group)
(.str op wstr opg " dst" mach "-" group "-" mode)
((machine mach) RL_1ADDR)
(.str op wstr opg " ${dst" mach "-" group "-" mode "}")
encoding
(sem mode (.sym dst mach - group - mode))
())
)
(define-pmacro (unary-insn-defn mach group mode wstr op encoding sem)
(unary-insn-defn-g mach group mode wstr op encoding sem "")
)
(define-pmacro (unary16-defn-g mode wstr wbit op opc1 opc2 opc3 sem opg)
(unary-insn-defn-g 16 16 mode wstr op
(+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16- mode))
sem opg)
)
(define-pmacro (unary16-defn mode wstr wbit op opc1 opc2 opc3 sem)
(unary-16-defn-g mode wstr wbit op opc1 opc2 opc3 sem "")
)
(define-pmacro (unary32-defn-g mode wstr wbit op opc1 opc2 opc3 sem opg)
(begin
; Multi insns are tried for assembly in the reverse order in which they appear here, so
; define the absolute-indirect insns first in order to prevent them from being selected
; when the mode is register-indirect
; (unary-insn-defn 32 24-absolute-indirect mode wstr op
; (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-15-1 wbit) (.sym dst32-24-absolute-indirect- mode) (f-18-2 opc2) (f-20-4 opc3))
; sem)
(unary-insn-defn-g 32 16-Unprefixed mode wstr op
(+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3))
sem opg)
; (unary-insn-defn 32 24-indirect mode wstr op
; (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-15-1 wbit) (.sym dst32-24-indirect- mode) (f-18-2 opc2) (f-20-4 opc3))
; sem)
)
)
(define-pmacro (unary32-defn mode wstr wbit op opc1 opc2 opc3 sem)
(unary32-defn-g mode wstr wbit op opc1 opc2 opc3 sem "")
)
(define-pmacro (unary-insn-mach-g mach op opc1 opc2 opc3 sem opg)
(begin
(.apply (.sym unary mach -defn-g) (QI .b 0 op opc1 opc2 opc3 sem opg))
(.apply (.sym unary mach -defn-g) (HI .w 1 op opc1 opc2 opc3 sem opg))
)
)
(define-pmacro (unary-insn-mach mach op opc1 opc2 opc3 sem)
(unary-insn-mach-g mach op opc1 opc2 opc3 sem "")
)
(define-pmacro (unary-insn op opc16-1 opc16-2 opc16-3 opc32-1 opc32-2 opc32-3 sem)
(begin
(unary-insn-mach-g 16 op opc16-1 opc16-2 opc16-3 sem "")
(unary-insn-mach-g 32 op opc32-1 opc32-2 opc32-3 sem "")
)
)
(define-pmacro (unary-insn-g op opc16-1 opc16-2 opc16-3 opc32-1 opc32-2 opc32-3 sem)
(begin
(unary-insn-mach-g 16 op opc16-1 opc16-2 opc16-3 sem "$G")
(unary-insn-mach-g 32 op opc32-1 opc32-2 opc32-3 sem "$G")
)
)
;-------------------------------------------------------------
; Sign/zero extension macros
;-------------------------------------------------------------
(define-pmacro (ext-insn-defn mach group smode dmode wstr op encoding sem)
(dni (.sym op mach wstr - group)
(.str op wstr " dst" mach "-" group "-" smode)
((machine mach))
(.str op wstr " ${dst" mach "-" group "-" smode "}")
encoding
(sem smode dmode (.sym dst mach - group - smode) (.sym dst mach - group - smode))
())
)
(define-pmacro (ext16-defn smode dmode wstr wbit op opc1 opc2 opc3 sem)
(ext-insn-defn 16 16-Ext smode dmode wstr op
(+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-Ext- smode))
sem)
)
(define-pmacro (ext32-defn smode dmode wstr wbit op opc1 opc2 opc3 sem)
(ext-insn-defn 32 16-ExtUnprefixed smode dmode wstr op
(+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst32-16-ExtUnprefixed- smode))
sem)
)
(define-pmacro (ext32-binary-insn src-group dst-group op wstr encoding sem)
(dni (.sym op 32 wstr - src-group - dst-group)
(.str op 32 wstr " src32-" src-group "-QI,dst32-" dst-group "-HI")
((machine 32))
(.str op wstr " ${src32-" src-group "-QI},${dst32-" dst-group "-HI}")
encoding
(sem QI HI (.sym src32- src-group -QI) (.sym dst32 - dst-group -HI))
())
)
(define-pmacro (ext32-binary-defn op wstr opc1 opc2 sem)
(begin
(ext32-binary-insn basic-ExtPrefixed 24-Prefixed op wstr
(+ (f-0-4 0) (f-4-4 1) (f-8-1 opc1) (f-15-1 0) src32-basic-ExtPrefixed-QI dst32-24-Prefixed-HI (f-20-4 opc2))
sem)
(ext32-binary-insn 24-24-Prefixed 48-Prefixed op wstr
(+ (f-0-4 0) (f-4-4 1) (f-8-1 opc1) (f-15-1 0) src32-24-24-Prefixed-QI dst32-48-Prefixed-HI (f-20-4 opc2))
sem)
(ext32-binary-insn 24-16-Prefixed 40-Prefixed op wstr
(+ (f-0-4 0) (f-4-4 1) (f-8-1 opc1) (f-15-1 0) src32-24-16-Prefixed-QI dst32-40-Prefixed-HI (f-20-4 opc2))
sem)
(ext32-binary-insn 24-8-Prefixed 32-Prefixed op wstr
(+ (f-0-4 0) (f-4-4 1) (f-8-1 opc1) (f-15-1 0) src32-24-8-Prefixed-QI dst32-32-Prefixed-HI (f-20-4 opc2))
sem)
)
)
;=============================================================
; Binary Arithmetic macros
;
;-------------------------------------------------------------
;<arith>.size:S src2,r0[l] -- for m32c
;-------------------------------------------------------------
(define-pmacro (binary-arith32-S-src2 op xmode wstr wbit opc1 opc2 sem)
(dni (.sym op 32 wstr .S-src2-r0- xmode)
(.str op 32 wstr ":S src2,r0[l]")
((machine 32))
(.str op wstr"$S ${src32-2-S-" xmode "},${Dst32R0" xmode "-S}")
(+ opc1 opc2 (.sym src32-2-S- xmode) (f-7-1 wbit))
(sem xmode (.sym src32-2-S- xmode) (.sym Dst32R0 xmode -S))
())
)
;-------------------------------------------------------------
;<arith>.b:S src2,r0l/r0h -- for m16c
;-------------------------------------------------------------
(define-pmacro (binary-arith16-b-S-src2 op opc1 opc2 sem)
(begin
(dni (.sym op 16 .b.S-src2)
(.str op ".b:S src2,r0[lh]")
((machine 16))
(.str op ".b$S ${src16-2-S},${Dst16RnQI-S}")
(+ opc1 opc2 Dst16RnQI-S src16-2-S)
(sem QI src16-2-S Dst16RnQI-S)
())
(dni (.sym op 16 .b.S-r0l-r0h)
(.str op ".b:S r0l/r0h")
((machine 16))
(.str op ".b$S ${srcdst16-r0l-r0h-S}")
(+ opc1 opc2 srcdst16-r0l-r0h-S)
(if (eq srcdst16-r0l-r0h-S 0)
(sem QI R0h R0l)
(sem QI R0l R0h))
())
)
)
;-------------------------------------------------------------
;<arith>.b:S #imm8,dst3 -- for m16c
;-------------------------------------------------------------
(define-pmacro (binary-arith16-b-S-imm8-dst3 op sz opc1 opc2 sem)
(dni (.sym op 16 .b.S-imm8-dst3)
(.str op sz ":S imm8,dst3")
((machine 16))
(.str op sz "$S #${Imm-8-QI},${Dst16-3-S-16}")
(+ opc1 opc2 Dst16-3-S-16 Imm-8-QI)
(sem QI Imm-8-QI Dst16-3-S-16)
())
)
;-------------------------------------------------------------
;<arith>.size:Q #imm4,sp -- for m16c
;-------------------------------------------------------------
(define-pmacro (binary-arith16-Q-sp op opc1 opc2 opc3 sem)
(dni (.sym op 16 -wQ-sp)
(.str op ".w:q #imm4,sp")
((machine 16))
(.str op ".w$Q #${Imm-12-s4},sp")
(+ opc1 opc2 opc3 Imm-12-s4)
(sem QI Imm-12-s4 sp)
())
)
;-------------------------------------------------------------
;<arith>.size:G #imm,sp -- for m16c
;-------------------------------------------------------------
(define-pmacro (binary-arith16-G-sp-defn mode wstr wbit op opc1 opc2 opc3 opc4 sem)
(dni (.sym op 16 wstr - G-sp)
(.str op wstr " imm-sp " mode)
((machine 16))
(.str op wstr "$G #${Imm-16-" mode "},sp")
(+ opc1 opc2 (f-7-1 wbit) opc3 opc4 (.sym Imm-16- mode))
(sem mode (.sym Imm-16- mode) sp)
())
)
(define-pmacro (binary-arith16-G-sp op opc1 opc2 opc3 opc4 sem)
(begin
(binary-arith16-G-sp-defn QI .b 0 op opc1 opc2 opc3 opc4 sem)
(binary-arith16-G-sp-defn HI .w 1 op opc1 opc2 opc3 opc4 sem)
)
)
;-------------------------------------------------------------
;<arith>.size:G #imm,dst -- for m16c and m32c
;-------------------------------------------------------------
(define-pmacro (binary-arith-imm-dst-defn mach src dstgroup dmode wstr op suffix encoding sem)
(dni (.sym op mach wstr - imm-G - dstgroup)
(.str op wstr " " mach "-imm-G-" dstgroup "-" dmode)
((machine mach) RL_1ADDR)
(.str op wstr "$"suffix " #${" src "},${dst" mach "-" dstgroup "-" dmode "}")
encoding
(sem dmode src (.sym dst mach - dstgroup - dmode))
())
)
; m16c variants
(define-pmacro (binary-arith16-imm-dst-defn smode dmode wstr wbit op suffix opc1 opc2 opc3 sem)
(begin
(binary-arith-imm-dst-defn 16 (.sym Imm-32- smode) 16-16 dmode wstr op suffix
(+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-16- dmode) (.sym Imm-32- smode))
sem)
(binary-arith-imm-dst-defn 16 (.sym Imm-24- smode) 16-8 dmode wstr op suffix
(+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-8- dmode) (.sym Imm-24- smode))
sem)
(binary-arith-imm-dst-defn 16 (.sym Imm-16- smode) basic dmode wstr op suffix
(+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-basic- dmode) (.sym Imm-16- smode))
sem)
)
)
; m32c Unprefixed variants
(define-pmacro (binary-arith32-imm-dst-Unprefixed smode dmode wstr wbit op suffix opc1 opc2 opc3 sem)
(begin
(binary-arith-imm-dst-defn 32 (.sym Imm-40- smode) 16-24-Unprefixed dmode wstr op suffix
(+ (f-0-4 opc1) (f-10-2 opc2) (f-7-1 wbit) (f-12-4 opc3) (.sym dst32-16-24-Unprefixed- dmode) (.sym Imm-40- smode))
sem)
(binary-arith-imm-dst-defn 32 (.sym Imm-32- smode) 16-16-Unprefixed dmode wstr op suffix
(+ (f-0-4 opc1) (f-10-2 opc2) (f-7-1 wbit) (f-12-4 opc3) (.sym dst32-16-16-Unprefixed- dmode) (.sym Imm-32- smode))
sem)
(binary-arith-imm-dst-defn 32 (.sym Imm-24- smode) 16-8-Unprefixed dmode wstr op suffix
(+ (f-0-4 opc1) (f-10-2 opc2) (f-7-1 wbit) (f-12-4 opc3) (.sym dst32-16-8-Unprefixed- dmode) (.sym Imm-24- smode))
sem)
(binary-arith-imm-dst-defn 32 (.sym Imm-16- smode) basic-Unprefixed dmode wstr op suffix
(+ (f-0-4 opc1) (f-10-2 opc2) (f-7-1 wbit) (f-12-4 opc3) (.sym dst32-basic-Unprefixed- dmode) (.sym Imm-16- smode))
sem)
)
)
; m32c Prefixed variants
(define-pmacro (binary-arith32-imm-dst-Prefixed smode dmode wstr wbit op suffix opc1 opc2 opc3 sem)
(begin
(binary-arith-imm-dst-defn 32 (.sym Imm-48- smode) 24-24-Prefixed dmode wstr op suffix
(+ (f-0-4 0) (f-4-4 1) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) (.sym dst32-24-24-Prefixed- dmode) (.sym Imm-48- smode))
sem)
(binary-arith-imm-dst-defn 32 (.sym Imm-40- smode) 24-16-Prefixed dmode wstr op suffix
(+ (f-0-4 0) (f-4-4 1) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) (.sym dst32-24-16-Prefixed- dmode) (.sym Imm-40- smode))
sem)
(binary-arith-imm-dst-defn 32 (.sym Imm-32- smode) 24-8-Prefixed dmode wstr op suffix
(+ (f-0-4 0) (f-4-4 1) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) (.sym dst32-24-8-Prefixed- dmode) (.sym Imm-32- smode))
sem)
(binary-arith-imm-dst-defn 32 (.sym Imm-24- smode) basic-Prefixed dmode wstr op suffix
(+ (f-0-4 0) (f-4-4 1) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) (.sym dst32-basic-Prefixed- dmode) (.sym Imm-24- smode))
sem)
)
)
; All m32c variants
(define-pmacro (binary-arith32-imm-dst-defn smode dmode wstr wbit op suffix opc1 opc2 opc3 sem)
(begin
; Multi insns are tried for assembly in the reverse order in which they appear here, so
; define the absolute-indirect insns first in order to prevent them from being selected
; when the mode is register-indirect
; (binary-arith-imm-dst-defn 32 (.sym Imm-48- smode) 24-24-absolute-indirect dmode wstr op suffix
; (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) (.sym dst32-24-24-absolute-indirect- dmode) (.sym Imm-48- smode))
; sem)
; (binary-arith-imm-dst-defn 32 (.sym Imm-40- smode) 24-16-absolute-indirect dmode wstr op suffix
; (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) (.sym dst32-24-16-absolute-indirect- dmode) (.sym Imm-40- smode))
; sem)
; Unprefixed modes next
(binary-arith32-imm-dst-Unprefixed smode dmode wstr wbit op suffix opc1 opc2 opc3 sem)
; Remaining indirect modes
; (binary-arith-imm-dst-defn 32 (.sym Imm-24- smode) basic-indirect dmode wstr op suffix
; (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) (.sym dst32-basic-indirect- dmode) (.sym Imm-24- smode))
; sem)
; (binary-arith-imm-dst-defn 32 (.sym Imm-48- smode) 24-24-indirect dmode wstr op suffix
; (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) (.sym dst32-24-24-indirect- dmode) (.sym Imm-48- smode))
; sem)
; (binary-arith-imm-dst-defn 32 (.sym Imm-40- smode) 24-16-indirect dmode wstr op suffix
; (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) (.sym dst32-24-16-indirect- dmode) (.sym Imm-40- smode))
; sem)
; (binary-arith-imm-dst-defn 32 (.sym Imm-32- smode) 24-8-indirect dmode wstr op suffix
; (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3) (.sym dst32-24-8-indirect- dmode) (.sym Imm-32- smode))
; sem)
)
)
(define-pmacro (binary-arith-imm-dst-mach mach op suffix opc1 opc2 opc3 sem)
(begin
(.apply (.sym binary-arith mach -imm-dst-defn) (QI QI .b 0 op suffix opc1 opc2 opc3 sem))
(.apply (.sym binary-arith mach -imm-dst-defn) (HI HI .w 1 op suffix opc1 opc2 opc3 sem))
)
)
(define-pmacro (binary-arith-imm-dst op suffix opc16-1 opc16-2 opc16-3 opc32-1 opc32-2 opc32-3 sem)
(begin
(binary-arith-imm-dst-mach 16 op suffix opc16-1 opc16-2 opc16-3 sem)
(binary-arith-imm-dst-mach 32 op suffix opc32-1 opc32-2 opc32-3 sem)
)
)
;-------------------------------------------------------------
;<arith>.size:Q #imm4,dst -- for m16c and m32c
;-------------------------------------------------------------
(define-pmacro (binary-arith-imm4-dst-defn mach src dstgroup mode wstr op encoding sem)
(dni (.sym op mach wstr - imm4-Q - dstgroup)
(.str op wstr " " mach "-imm4-Q-" dstgroup "-" mode)
((machine mach) RL_1ADDR)
(.str op wstr "$Q #${" src "},${dst" mach "-" dstgroup "-" mode "}")
encoding
(sem mode src (.sym dst mach - dstgroup - mode))
())
)
; m16c variants
(define-pmacro (binary-arith16-imm4-dst-defn mode wstr wbit1 wbit2 op opc1 opc2 sem)
(binary-arith-imm4-dst-defn 16 Imm-8-s4 16 mode wstr op
(+ opc1 opc2 (f-7-1 wbit2) Imm-8-s4 (.sym dst16-16- mode))
sem)
)
(define-pmacro (binary-arith16-shimm4-dst-defn mode wstr wbit1 wbit2 op opc1 opc2 sem)
(binary-arith-imm4-dst-defn 16 Imm-sh-8-s4 16 mode wstr op
(+ opc1 opc2 (f-7-1 wbit2) Imm-sh-8-s4 (.sym dst16-16- mode))
sem)
)
; m32c variants
(define-pmacro (binary-arith32-imm4-dst-defn mode wstr wbit1 wbit2 op opc1 opc2 sem)
(begin
; Multi insns are tried for assembly in the reverse order in which they appear here, so
; define the absolute-indirect insns first in order to prevent them from being selected
; when the mode is register-indirect
; (binary-arith-imm4-dst-defn 32 Imm-20-s4 24-absolute-indirect mode wstr op
; (+ (f-0-4 0) (f-4-4 9) (f-8-3 opc1) (f-11-1 wbit1) (f-15-1 wbit2) (.sym dst32-24-absolute-indirect- mode) (f-18-2 opc2) Imm-20-s4)
; sem)
(binary-arith-imm4-dst-defn 32 Imm-12-s4 16-Unprefixed mode wstr op
(+ (f-0-3 opc1) (f-3-1 wbit1) (f-7-1 wbit2) (.sym dst32-16-Unprefixed- mode) (f-10-2 opc2) Imm-12-s4)
sem)
; (binary-arith-imm4-dst-defn 32 Imm-20-s4 24-indirect mode wstr op
; (+ (f-0-4 0) (f-4-4 9) (f-8-3 opc1) (f-11-1 wbit1) (f-15-1 wbit2) (.sym dst32-24-indirect- mode) (f-18-2 opc2) Imm-20-s4)
; sem)
)
)
(define-pmacro (binary-arith32-shimm4-dst-defn mode wstr wbit1 wbit2 op opc1 opc2 sem)
(begin
; Multi insns are tried for assembly in the reverse order in which they appear here, so
; define the absolute-indirect insns first in order to prevent them from being selected
; when the mode is register-indirect
; (binary-arith-imm4-dst-defn 32 Imm-sh-20-s4 24-absolute-indirect mode wstr op
; (+ (f-0-4 0) (f-4-4 9) (f-8-3 opc1) (f-11-1 wbit1) (f-15-1 wbit2) (.sym dst32-24-absolute-indirect- mode) (f-18-2 opc2) Imm-sh-20-s4)
; sem)
(binary-arith-imm4-dst-defn 32 Imm-sh-12-s4 16-Unprefixed mode wstr op
(+ (f-0-3 opc1) (f-3-1 wbit1) (f-7-1 wbit2) (.sym dst32-16-Unprefixed- mode) (f-10-2 opc2) Imm-sh-12-s4)
sem)
; (binary-arith-imm4-dst-defn 32 Imm-sh-20-s4 24-indirect mode wstr op
; (+ (f-0-4 0) (f-4-4 9) (f-8-3 opc1) (f-11-1 wbit1) (f-15-1 wbit2) (.sym dst32-24-indirect- mode) (f-18-2 opc2) Imm-sh-20-s4)
; sem)
)
)
(define-pmacro (binary-arith-imm4-dst-mach mach op opc1 opc2 sem)
(begin
(.apply (.sym binary-arith mach -imm4-dst-defn) (QI .b 0 0 op opc1 opc2 sem))
(.apply (.sym binary-arith mach -imm4-dst-defn) (HI .w 0 1 op opc1 opc2 sem))
)
)
(define-pmacro (binary-arith-imm4-dst op opc16-1 opc16-2 opc32-1 opc32-2 sem)
(begin
(binary-arith-imm4-dst-mach 16 op opc16-1 opc16-2 sem)
(binary-arith-imm4-dst-mach 32 op opc32-1 opc32-2 sem)
)
)
;-------------------------------------------------------------
;<arith>.size:G src,dst -- for m16c and m32c
;-------------------------------------------------------------
(define-pmacro (binary-arith-src-dst-defn mach srcgroup dstgroup smode dmode wstr op suffix encoding sem)
(dni (.sym op mach wstr - srcgroup - dstgroup)
(.str op wstr " dst" mach "-" srcgroup "-" dstgroup "-" dmode)
((machine mach) RL_2ADDR)
(.str op wstr "$" suffix " ${src" mach "-" srcgroup "-" smode "},${dst" mach "-" dstgroup "-" dmode "}")
encoding
(sem dmode (.sym src mach - srcgroup - smode) (.sym dst mach - dstgroup - dmode))
())
)
; m16c variants
(define-pmacro (binary-arith16-src-dst-defn smode dmode wstr wbit op suffix opc1 opc2 sem)
(begin
(binary-arith-src-dst-defn 16 basic 16 smode dmode wstr op suffix
(+ opc1 opc2 (f-7-1 wbit) (.sym src16-basic- smode) (.sym dst16-16- dmode))
sem)
(binary-arith-src-dst-defn 16 16-16 32 smode dmode wstr op suffix
(+ opc1 opc2 (f-7-1 wbit) (.sym src16-16-16- smode) (.sym dst16-32- dmode))
sem)
(binary-arith-src-dst-defn 16 16-8 24 smode dmode wstr op suffix
(+ opc1 opc2 (f-7-1 wbit) (.sym src16-16-8- smode) (.sym dst16-24- dmode))
sem)
)
)
; m32c Prefixed variants
(define-pmacro (binary-arith32-src-dst-Prefixed smode dmode wstr wbit op suffix opc1 opc2 sem)
(begin
(binary-arith-src-dst-defn 32 basic-Prefixed 24-Prefixed smode dmode wstr op suffix
(+ (f-0-4 0) (f-4-4 1) (f-8-1 opc1) (f-15-1 wbit) (.sym src32-basic-Prefixed- smode) (.sym dst32-24-Prefixed- dmode) (f-20-4 opc2))
sem)
(binary-arith-src-dst-defn 32 24-24-Prefixed 48-Prefixed smode dmode wstr op suffix
(+ (f-0-4 0) (f-4-4 1) (f-8-1 opc1) (f-15-1 wbit) (.sym src32-24-24-Prefixed- smode) (.sym dst32-48-Prefixed- dmode) (f-20-4 opc2))
sem)
(binary-arith-src-dst-defn 32 24-16-Prefixed 40-Prefixed smode dmode wstr op suffix
(+ (f-0-4 0) (f-4-4 1) (f-8-1 opc1) (f-15-1 wbit) (.sym src32-24-16-Prefixed- smode) (.sym dst32-40-Prefixed- dmode) (f-20-4 opc2))
sem)
(binary-arith-src-dst-defn 32 24-8-Prefixed 32-Prefixed smode dmode wstr op suffix
(+ (f-0-4 0) (f-4-4 1) (f-8-1 opc1) (f-15-1 wbit) (.sym src32-24-8-Prefixed- smode) (.sym dst32-32-Prefixed- dmode) (f-20-4 opc2))
sem)
)
)
; all m32c variants
(define-pmacro (binary-arith32-src-dst-defn smode dmode wstr wbit op suffix opc1 opc2 sem)
(begin
; Multi insns are tried for assembly in the reverse order in which they appear here, so
; define the absolute-indirect insns first in order to prevent them from being selected
; when the mode is register-indirect
; (binary-arith-src-dst-defn 32 24-24-absolute-indirect 48-absolute-indirect smode dmode wstr op suffix
; (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit)
; (.sym src32-24-24-absolute-indirect- smode) (.sym dst32-48-absolute-indirect- dmode) (f-20-4 opc2))
; sem)
; (binary-arith-src-dst-defn 32 24-16-absolute-indirect 40-absolute-indirect smode dmode wstr op suffix
; (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit)
; (.sym src32-24-16-absolute-indirect- smode) (.sym dst32-40-absolute-indirect- dmode) (f-20-4 opc2))
; sem)
; (binary-arith-src-dst-defn 32 24-24-absolute-indirect 48-Prefixed smode dmode wstr op suffix
; (+ (f-0-4 4) (f-4-4 1) (f-8-1 opc1) (f-15-1 wbit)
; (.sym src32-24-24-absolute-indirect- smode) (.sym dst32-48-Prefixed- dmode) (f-20-4 opc2))
; sem)
; (binary-arith-src-dst-defn 32 24-16-absolute-indirect 40-Prefixed smode dmode wstr op suffix
; (+ (f-0-4 4) (f-4-4 1) (f-8-1 opc1) (f-15-1 wbit)
; (.sym src32-24-16-absolute-indirect- smode) (.sym dst32-40-Prefixed- dmode) (f-20-4 opc2))
; sem)
; (binary-arith-src-dst-defn 32 24-24-absolute-indirect 48-indirect smode dmode wstr op suffix
; (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit)
; (.sym src32-24-24-absolute-indirect- smode) (.sym dst32-48-indirect- dmode) (f-20-4 opc2))
; sem)
; (binary-arith-src-dst-defn 32 24-16-absolute-indirect 40-indirect smode dmode wstr op suffix
; (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit)
; (.sym src32-24-16-absolute-indirect- smode) (.sym dst32-40-indirect- dmode) (f-20-4 opc2))
; sem)
; (binary-arith-src-dst-defn 32 basic-Prefixed 24-absolute-indirect smode dmode wstr op suffix
; (+ (f-0-4 0) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit)
; (.sym src32-basic-Prefixed- smode) (.sym dst32-24-absolute-indirect- dmode) (f-20-4 opc2))
; sem)
; (binary-arith-src-dst-defn 32 24-24-Prefixed 48-absolute-indirect smode dmode wstr op suffix
; (+ (f-0-4 0) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit)
; (.sym src32-24-24-Prefixed- smode) (.sym dst32-48-absolute-indirect- dmode) (f-20-4 opc2))
; sem)
; (binary-arith-src-dst-defn 32 24-16-Prefixed 40-absolute-indirect smode dmode wstr op suffix
; (+ (f-0-4 0) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit)
; (.sym src32-24-16-Prefixed- smode) (.sym dst32-40-absolute-indirect- dmode) (f-20-4 opc2))
; sem)
; (binary-arith-src-dst-defn 32 24-8-Prefixed 32-absolute-indirect smode dmode wstr op suffix
; (+ (f-0-4 0) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit)
; (.sym src32-24-8-Prefixed- smode) (.sym dst32-32-absolute-indirect- dmode) (f-20-4 opc2))
; sem)
; (binary-arith-src-dst-defn 32 basic-indirect 24-absolute-indirect smode dmode wstr op suffix
; (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit)
; (.sym src32-basic-indirect- smode) (.sym dst32-24-absolute-indirect- dmode) (f-20-4 opc2))
; sem)
; (binary-arith-src-dst-defn 32 24-24-indirect 48-absolute-indirect smode dmode wstr op suffix
; (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit)
; (.sym src32-24-24-indirect- smode) (.sym dst32-48-absolute-indirect- dmode) (f-20-4 opc2))
; sem)
; (binary-arith-src-dst-defn 32 24-16-indirect 40-absolute-indirect smode dmode wstr op suffix
; (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit)
; (.sym src32-24-16-indirect- smode) (.sym dst32-40-absolute-indirect- dmode) (f-20-4 opc2))
; sem)
; (binary-arith-src-dst-defn 32 24-8-indirect 32-absolute-indirect smode dmode wstr op suffix
; (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit)
; (.sym src32-24-8-indirect- smode) (.sym dst32-32-absolute-indirect- dmode) (f-20-4 opc2))
; sem)
(binary-arith-src-dst-defn 32 basic-Unprefixed 16-Unprefixed smode dmode wstr op suffix
(+ (f-0-1 opc1) (f-7-1 wbit) (.sym src32-basic-Unprefixed- smode) (.sym dst32-16-Unprefixed- dmode) (f-12-4 opc2))
sem)
(binary-arith-src-dst-defn 32 16-24-Unprefixed 40-Unprefixed smode dmode wstr op suffix
(+ (f-0-1 opc1) (f-7-1 wbit) (.sym src32-16-24-Unprefixed- smode) (.sym dst32-40-Unprefixed- dmode) (f-12-4 opc2))
sem)
(binary-arith-src-dst-defn 32 16-16-Unprefixed 32-Unprefixed smode dmode wstr op suffix
(+ (f-0-1 opc1) (f-7-1 wbit) (.sym src32-16-16-Unprefixed- smode) (.sym dst32-32-Unprefixed- dmode) (f-12-4 opc2))
sem)
(binary-arith-src-dst-defn 32 16-8-Unprefixed 24-Unprefixed smode dmode wstr op suffix
(+ (f-0-1 opc1) (f-7-1 wbit) (.sym src32-16-8-Unprefixed- smode) (.sym dst32-24-Unprefixed- dmode) (f-12-4 opc2))
sem)
; (binary-arith-src-dst-defn 32 basic-indirect 24-Prefixed smode dmode wstr op suffix
; (+ (f-0-4 4) (f-4-4 1) (f-8-1 opc1) (f-15-1 wbit)
; (.sym src32-basic-indirect- smode) (.sym dst32-24-Prefixed- dmode) (f-20-4 opc2))
; sem)
; (binary-arith-src-dst-defn 32 24-24-indirect 48-Prefixed smode dmode wstr op suffix
; (+ (f-0-4 4) (f-4-4 1) (f-8-1 opc1) (f-15-1 wbit)
; (.sym src32-24-24-indirect- smode) (.sym dst32-48-Prefixed- dmode) (f-20-4 opc2))
; sem)
; (binary-arith-src-dst-defn 32 24-16-indirect 40-Prefixed smode dmode wstr op suffix
; (+ (f-0-4 4) (f-4-4 1) (f-8-1 opc1) (f-15-1 wbit)
; (.sym src32-24-16-indirect- smode) (.sym dst32-40-Prefixed- dmode) (f-20-4 opc2))
; sem)
; (binary-arith-src-dst-defn 32 24-8-indirect 32-Prefixed smode dmode wstr op suffix
; (+ (f-0-4 4) (f-4-4 1) (f-8-1 opc1) (f-15-1 wbit)
; (.sym src32-24-8-indirect- smode) (.sym dst32-32-Prefixed- dmode) (f-20-4 opc2))
; sem)
; (binary-arith-src-dst-defn 32 basic-Prefixed 24-indirect smode dmode wstr op suffix
; (+ (f-0-4 0) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit)
; (.sym src32-basic-Prefixed- smode) (.sym dst32-24-indirect- dmode) (f-20-4 opc2))
; sem)
; (binary-arith-src-dst-defn 32 24-24-Prefixed 48-indirect smode dmode wstr op suffix
; (+ (f-0-4 0) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit)
; (.sym src32-24-24-Prefixed- smode) (.sym dst32-48-indirect- dmode) (f-20-4 opc2))
; sem)
; (binary-arith-src-dst-defn 32 24-16-Prefixed 40-indirect smode dmode wstr op suffix
; (+ (f-0-4 0) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit)
; (.sym src32-24-16-Prefixed- smode) (.sym dst32-40-indirect- dmode) (f-20-4 opc2))
; sem)
; (binary-arith-src-dst-defn 32 24-8-Prefixed 32-indirect smode dmode wstr op suffix
; (+ (f-0-4 0) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit)
; (.sym src32-24-8-Prefixed- smode) (.sym dst32-32-indirect- dmode) (f-20-4 opc2))
; sem)
; (binary-arith-src-dst-defn 32 basic-indirect 24-indirect smode dmode wstr op suffix
; (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit)
; (.sym src32-basic-indirect- smode) (.sym dst32-24-indirect- dmode) (f-20-4 opc2))
; sem)
; (binary-arith-src-dst-defn 32 24-24-indirect 48-indirect smode dmode wstr op suffix
; (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit)
; (.sym src32-24-24-indirect- smode) (.sym dst32-48-indirect- dmode) (f-20-4 opc2))
; sem)
; (binary-arith-src-dst-defn 32 24-16-indirect 40-indirect smode dmode wstr op suffix
; (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit)
; (.sym src32-24-16-indirect- smode) (.sym dst32-40-indirect- dmode) (f-20-4 opc2))
; sem)
; (binary-arith-src-dst-defn 32 24-8-indirect 32-indirect smode dmode wstr op suffix
; (+ (f-0-4 4) (f-4-4 9) (f-8-1 opc1) (f-15-1 wbit)
; (.sym src32-24-8-indirect- smode) (.sym dst32-32-indirect- dmode) (f-20-4 opc2))
; sem)
)
)
(define-pmacro (binary-arith-src-dst-mach mach op suffix opc1 opc2 sem)
(begin
(.apply (.sym binary-arith mach -src-dst-defn) (QI QI .b 0 op suffix opc1 opc2 sem))
(.apply (.sym binary-arith mach -src-dst-defn) (HI HI .w 1 op suffix opc1 opc2 sem))
)
)
(define-pmacro (binary-arith-src-dst op suffix opc16-1 opc16-2 opc32-1 opc32-2 sem)
(begin
(binary-arith-src-dst-mach 16 op suffix opc16-1 opc16-2 sem)
(binary-arith-src-dst-mach 32 op suffix opc32-1 opc32-2 sem)
)
)
;-------------------------------------------------------------
;<arith>.size:S #imm,dst -- for m32c
;-------------------------------------------------------------
(define-pmacro (binary-arith32-s-imm-dst-defn src dstgroup mode wstr op encoding sem)
(dni (.sym op 32 wstr - imm-S - dstgroup)
(.str op wstr " 32-imm-S-" dstgroup "-" mode)
((machine 32))
(.str op wstr "$S #${" src "},${dst32-" dstgroup "-" mode "}")
encoding
(sem mode src (.sym dst32- dstgroup - mode))
())
)
(define-pmacro (binary-arith32-z-imm-dst-defn src dstgroup mode wstr op encoding sem)
(dni (.sym op 32 wstr - imm-Z - dstgroup)
(.str op wstr " 32-imm-Z-" dstgroup "-" mode)
((machine 32))
(.str op wstr "$Z #0,${dst32-" dstgroup "-" mode "}")
encoding
(sem mode (const 0) (.sym dst32- dstgroup - mode))
())
)
(define-pmacro (binary-arith32-s-imm-dst mode wstr wbit op opc1 opc2 sem)
(begin
; (binary-arith32-s-imm-dst-defn (.sym Imm-32- mode) 2-S-absolute-indirect mode wstr op
; (+ (f-0-4 0) (f-4-4 9) (f-8-2 opc1) (.sym dst32-2-S-absolute-indirect- mode) (f-12-3 opc2) (f-15-1 wbit) (.sym Imm-32- mode))
; sem)
(binary-arith32-s-imm-dst-defn (.sym Imm-8- mode) 2-S-basic mode wstr op
(+ (f-0-2 opc1) (.sym dst32-2-S-basic- mode) (f-4-3 opc2) (f-7-1 wbit) (.sym Imm-8- mode))
sem)
(binary-arith32-s-imm-dst-defn (.sym Imm-24- mode) 2-S-16 mode wstr op
(+ (f-0-2 opc1) (.sym dst32-2-S-16- mode) (f-4-3 opc2) (f-7-1 wbit) (.sym Imm-24- mode))
sem)
(binary-arith32-s-imm-dst-defn (.sym Imm-16- mode) 2-S-8 mode wstr op
(+ (f-0-2 opc1) (.sym dst32-2-S-8- mode) (f-4-3 opc2) (f-7-1 wbit) (.sym Imm-16- mode))
sem)
; (binary-arith32-s-imm-dst-defn (.sym Imm-24- mode) 2-S-8-indirect mode wstr op
; (+ (f-0-4 0) (f-4-4 9) (f-8-2 opc1) (.sym dst32-2-S-8-indirect- mode) (f-12-3 opc2) (f-15-1 wbit) (.sym Imm-24- mode))
; sem)
)
)
(define-pmacro (binary-arith32-z-imm-dst mode wstr wbit op opc1 opc2 sem)
(begin
; (binary-arith32-z-imm-dst-defn (.sym Imm-32- mode) 2-S-absolute-indirect mode wstr op
; (+ (f-0-4 0) (f-4-4 9) (f-8-2 opc1) (.sym dst32-2-S-absolute-indirect- mode) (f-12-3 opc2) (f-15-1 wbit) (.sym Imm-32- mode))
; sem)
(binary-arith32-z-imm-dst-defn (.sym Imm-8- mode) 2-S-basic mode wstr op
(+ (f-0-2 opc1) (.sym dst32-2-S-basic- mode) (f-4-3 opc2) (f-7-1 wbit))
sem)
(binary-arith32-z-imm-dst-defn (.sym Imm-24- mode) 2-S-16 mode wstr op
(+ (f-0-2 opc1) (.sym dst32-2-S-16- mode) (f-4-3 opc2) (f-7-1 wbit))
sem)
(binary-arith32-z-imm-dst-defn (.sym Imm-16- mode) 2-S-8 mode wstr op
(+ (f-0-2 opc1) (.sym dst32-2-S-8- mode) (f-4-3 opc2) (f-7-1 wbit))
sem)
; (binary-arith32-z-imm-dst-defn (.sym Imm-24- mode) 2-S-8-indirect mode wstr op
; (+ (f-0-4 0) (f-4-4 9) (f-8-2 opc1) (.sym dst32-2-S-8-indirect- mode) (f-12-3 opc2) (f-15-1 wbit) (.sym Imm-24- mode))
; sem)
)
)
;-------------------------------------------------------------
;<arith>.L:S #imm1,An -- for m32c
;-------------------------------------------------------------
(define-pmacro (binary-arith32-l-s-imm1-an op opc1 opc2 sem)
(begin
(dni (.sym op 32.l-s-imm1-S-an)
(.str op ".l 32-imm1-S-an")
((machine 32))
(.str op ".l$S #${Imm1-S},${dst32-an-S}")
(+ opc1 Imm1-S opc2 dst32-an-S)
(sem SI Imm1-S dst32-an-S)
())
)
)
;-------------------------------------------------------------
;<arith>.L:Q #imm3,sp -- for m32c
;-------------------------------------------------------------
(define-pmacro (binary-arith32-l-q-imm3-sp op opc1 opc2 sem)
(begin
(dni (.sym op 32.l-imm3-Q)
(.str op ".l 32-imm3-Q")
((machine 32))
(.str op ".l$Q #${Imm3-S},sp")
(+ opc1 Imm3-S opc2)
(sem SI Imm3-S sp)
())
)
)
;-------------------------------------------------------------
;<arith>.L:S #imm8,sp -- for m32c
;-------------------------------------------------------------
(define-pmacro (binary-arith32-l-s-imm8-sp op opc1 opc2 opc3 opc4 sem)
(begin
(dni (.sym op 32.l-imm8-S)
(.str op ".l 32-imm8-S")
((machine 32))
(.str op ".l$S #${Imm-16-QI},sp")
(+ opc1 opc2 opc3 opc4 Imm-16-QI)
(sem SI Imm-16-QI sp)
())
)
)
;-------------------------------------------------------------
;<arith>.L:G #imm16,sp -- for m32c
;-------------------------------------------------------------
(define-pmacro (binary-arith32-l-g-imm16-sp op opc1 opc2 opc3 opc4 sem)
(begin
(dni (.sym op 32.l-imm16-G)
(.str op ".l 32-imm16-G")
((machine 32))
(.str op ".l$G #${Imm-16-HI},sp")
(+ opc1 opc2 opc3 opc4 Imm-16-HI)
(sem SI Imm-16-HI sp)
())
)
)
;-------------------------------------------------------------
;<arith>jnz.size #imm4,dst,label -- for m16c and m32c
;-------------------------------------------------------------
(define-pmacro (arith-jnz-imm4-dst-defn mach src dstgroup label mode wstr op encoding sem)
(dni (.sym op mach wstr - imm4 - dstgroup)
(.str op wstr " " mach "-imm4-" dstgroup "-" label "-" mode)
((machine mach))
(.str op wstr " #${" src "},${dst" mach "-" dstgroup "-" mode "},${" label "}")
encoding
(sem mode src (.sym dst mach - dstgroup - mode) label)
())
)
; m16c variants
(define-pmacro (arith-jnz16-imm4-dst-defn mode wstr wbit op i4n opc1 opc2 sem)
(begin
(arith-jnz-imm4-dst-defn 16 (.sym Imm-8- i4n) basic Lab-16-8 mode wstr op
(+ opc1 opc2 (f-7-1 wbit) (.sym Imm-8- i4n) (.sym dst16-basic- mode) Lab-16-8)
sem)
(arith-jnz-imm4-dst-defn 16 (.sym Imm-8- i4n) 16-16 Lab-32-8 mode wstr op
(+ opc1 opc2 (f-7-1 wbit) (.sym Imm-8- i4n) (.sym dst16-16-16- mode) Lab-16-8)
sem)
(arith-jnz-imm4-dst-defn 16 (.sym Imm-8- i4n) 16-8 Lab-24-8 mode wstr op
(+ opc1 opc2 (f-7-1 wbit) (.sym Imm-8- i4n) (.sym dst16-16-8- mode) Lab-16-8)
sem)
)
)
; m32c variants
(define-pmacro (arith-jnz32-imm4-dst-defn mode wstr wbit op i4n opc1 opc2 sem)
(begin
(arith-jnz-imm4-dst-defn 32 (.sym Imm-12- i4n) basic-Unprefixed Lab-16-8 mode wstr op
(+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-basic-Unprefixed- mode) (f-10-2 opc2) (.sym Imm-12- i4n) Lab-16-8)
sem)
(arith-jnz-imm4-dst-defn 32 (.sym Imm-12- i4n) 16-24-Unprefixed Lab-40-8 mode wstr op
(+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-24-Unprefixed- mode) (f-10-2 opc2) (.sym Imm-12- i4n) Lab-40-8)
sem)
(arith-jnz-imm4-dst-defn 32 (.sym Imm-12- i4n) 16-16-Unprefixed Lab-32-8 mode wstr op
(+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-16-Unprefixed- mode) (f-10-2 opc2) (.sym Imm-12- i4n) Lab-32-8)
sem)
(arith-jnz-imm4-dst-defn 32 (.sym Imm-12- i4n) 16-8-Unprefixed Lab-24-8 mode wstr op
(+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-8-Unprefixed- mode) (f-10-2 opc2) (.sym Imm-12- i4n) Lab-24-8)
sem)
)
)
(define-pmacro (arith-jnz-imm4-dst-mach mach op i4n opc1 opc2 sem)
(begin
(.apply (.sym arith-jnz mach -imm4-dst-defn) (QI .b 0 op i4n opc1 opc2 sem))
(.apply (.sym arith-jnz mach -imm4-dst-defn) (HI .w 1 op i4n opc1 opc2 sem))
)
)
(define-pmacro (arith-jnz-imm4-dst op i4n opc16-1 opc16-2 opc32-1 opc32-2 sem)
(begin
(arith-jnz-imm4-dst-mach 16 op i4n opc16-1 opc16-2 sem)
(arith-jnz-imm4-dst-mach 32 op i4n opc32-1 opc32-2 sem)
)
)
;-------------------------------------------------------------
;mov.size dsp8[sp],dst -- for m16c and m32c
;-------------------------------------------------------------
(define-pmacro (mov-dspsp-dst-defn mach dstgroup dsp mode wstr op encoding sem)
(dni (.sym op mach wstr -dspsp-dst- dstgroup)
(.str op wstr " " mach "-dsp[sp]-" dstgroup "-" dsp "-" mode)
((machine mach))
(.str op wstr "$G ${" dsp "}[sp],${dst" mach "-" dstgroup "-" mode "}")
encoding
(sem mach mode dsp (.sym dst mach - dstgroup - mode))
())
)
(define-pmacro (mov-src-dspsp-defn mach dstgroup dsp mode wstr op encoding sem)
(dni (.sym op mach wstr -dst-dspsp- dstgroup)
(.str op wstr " " mach "-dsp[sp]-" dstgroup "-" dsp "-" mode)
((machine mach))
(.str op wstr "$G ${dst" mach "-" dstgroup "-" mode "},${" dsp "}[sp]")
encoding
(sem mach mode (.sym dst mach - dstgroup - mode) dsp)
())
)
; m16c variants
(define-pmacro (mov16-dspsp-dst-defn mode wstr wbit op opc1 opc2 opc3 sem)
(begin
(mov-dspsp-dst-defn 16 basic Dsp-16-s8 mode wstr op
(+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-basic- mode) Dsp-16-s8)
sem)
(mov-dspsp-dst-defn 16 16-16 Dsp-32-s8 mode wstr op
(+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-16- mode) Dsp-32-s8)
sem)
(mov-dspsp-dst-defn 16 16-8 Dsp-24-s8 mode wstr op
(+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-8- mode) Dsp-24-s8)
sem)
)
)
(define-pmacro (mov16-src-dspsp-defn mode wstr wbit op opc1 opc2 opc3 sem)
(begin
(mov-src-dspsp-defn 16 basic Dsp-16-s8 mode wstr op
(+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-basic- mode) Dsp-16-s8)
sem)
(mov-src-dspsp-defn 16 16-16 Dsp-32-s8 mode wstr op
(+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-16- mode) Dsp-32-s8)
sem)
(mov-src-dspsp-defn 16 16-8 Dsp-24-s8 mode wstr op
(+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-8- mode) Dsp-24-s8)
sem)
)
)
; m32c variants
(define-pmacro (mov32-dspsp-dst-defn mode wstr wbit op opc1 opc2 opc3 sem)
(begin
(mov-dspsp-dst-defn 32 basic-Unprefixed Dsp-16-s8 mode wstr op
(+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-basic-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-16-s8)
sem)
(mov-dspsp-dst-defn 32 16-24-Unprefixed Dsp-40-s8 mode wstr op
(+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-24-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-40-s8)
sem)
(mov-dspsp-dst-defn 32 16-16-Unprefixed Dsp-32-s8 mode wstr op
(+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-16-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-32-s8)
sem)
(mov-dspsp-dst-defn 32 16-8-Unprefixed Dsp-24-s8 mode wstr op
(+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-8-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-24-s8)
sem)
)
)
(define-pmacro (mov32-src-dspsp-defn mode wstr wbit op opc1 opc2 opc3 sem)
(begin
(mov-src-dspsp-defn 32 basic-Unprefixed Dsp-16-s8 mode wstr op
(+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-basic-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-16-s8)
sem)
(mov-src-dspsp-defn 32 16-24-Unprefixed Dsp-40-s8 mode wstr op
(+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-24-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-40-s8)
sem)
(mov-src-dspsp-defn 32 16-16-Unprefixed Dsp-32-s8 mode wstr op
(+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-16-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-32-s8)
sem)
(mov-src-dspsp-defn 32 16-8-Unprefixed Dsp-24-s8 mode wstr op
(+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-8-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-24-s8)
sem)
)
)
(define-pmacro (mov-src-dspsp-mach mach op opc1 opc2 opc3 sem)
(begin
(.apply (.sym mov mach -src-dspsp-defn) (QI .b 0 op opc1 opc2 opc3 sem))
(.apply (.sym mov mach -src-dspsp-defn) (HI .w 1 op opc1 opc2 opc3 sem))
)
)
(define-pmacro (mov-dspsp-dst-mach mach op opc1 opc2 opc3 sem)
(begin
(.apply (.sym mov mach -dspsp-dst-defn) (QI .b 0 op opc1 opc2 opc3 sem))
(.apply (.sym mov mach -dspsp-dst-defn) (HI .w 1 op opc1 opc2 opc3 sem))
)
)
(define-pmacro (mov-dspsp-dst op opc16-1 opc16-2 opc16-3 opc32-1 opc32-2 opc32-3 sem)
(begin
(mov-dspsp-dst-mach 16 op opc16-1 opc16-2 opc16-3 sem)
(mov-dspsp-dst-mach 32 op opc32-1 opc32-2 opc32-3 sem)
)
)
(define-pmacro (mov-src-dspsp op opc16-1 opc16-2 opc16-3 opc32-1 opc32-2 opc32-3 sem)
(begin
(mov-src-dspsp-mach 16 op opc16-1 opc16-2 opc16-3 sem)
(mov-src-dspsp-mach 32 op opc32-1 opc32-2 opc32-3 sem)
)
)
;-------------------------------------------------------------
; lde dsp24,dst -- for m16c
;-------------------------------------------------------------
(define-pmacro (lde-dst-dsp mode wstr wbit dstgroup srcdisp)
(begin
(dni (.sym lde wstr - dstgroup -u20)
(.str "lde" wstr "-" dstgroup "-u20")
((machine 16))
(.str "lde" wstr " ${" srcdisp "},${dst16-" dstgroup "-" mode "}")
(+ (f-0-4 #x7) (f-4-3 #x2) (f-7-1 wbit) (f-8-4 #x8)
(.sym dst16- dstgroup - mode) srcdisp)
(nop)
())
(dni (.sym lde wstr - dstgroup -u20a0)
(.str "lde" wstr "-" dstgroup "-u20a0")
((machine 16))
(.str "lde" wstr " ${" srcdisp "}[a0],${dst16-" dstgroup "-" mode "}")
(+ (f-0-4 #x7) (f-4-3 #x2) (f-7-1 wbit) (f-8-4 #x9)
(.sym dst16- dstgroup - mode) srcdisp)
(nop)
())
(dni (.sym lde wstr - dstgroup -a1a0)
(.str "lde" wstr "-" dstgroup "-a1a0")
((machine 16))
(.str "lde" wstr " [a1a0],${dst16-" dstgroup "-" mode "}")
(+ (f-0-4 #x7) (f-4-3 #x2) (f-7-1 wbit) (f-8-4 #xa)
(.sym dst16- dstgroup - mode))
(nop)
())
)
)
(define-pmacro (lde-dst mode wstr wbit)
(begin
; like: QI .b 0
(lde-dst-dsp mode wstr wbit basic Dsp-16-u20)
(lde-dst-dsp mode wstr wbit 16-8 Dsp-24-u20)
(lde-dst-dsp mode wstr wbit 16-16 Dsp-32-u20)
)
)
;-------------------------------------------------------------
; ste dst,dsp24 -- for m16c
;-------------------------------------------------------------
(define-pmacro (ste-dst-dsp mode wstr wbit dstgroup srcdisp)
(begin
(dni (.sym ste wstr - dstgroup -u20)
(.str "ste" wstr "-" dstgroup "-u20")
((machine 16))
(.str "ste" wstr " ${dst16-" dstgroup "-" mode "},${" srcdisp "}")
(+ (f-0-4 #x7) (f-4-3 #x2) (f-7-1 wbit) (f-8-4 #x0)
(.sym dst16- dstgroup - mode) srcdisp)
(nop)
())
(dni (.sym ste wstr - dstgroup -u20a0)
(.str "ste" wstr "-" dstgroup "-u20a0")
((machine 16))
(.str "ste" wstr " ${dst16-" dstgroup "-" mode "},${" srcdisp "}[a0]")
(+ (f-0-4 #x7) (f-4-3 #x2) (f-7-1 wbit) (f-8-4 #x1)
(.sym dst16- dstgroup - mode) srcdisp)
(nop)
())
(dni (.sym ste wstr - dstgroup -a1a0)
(.str "ste" wstr "-" dstgroup "-a1a0")
((machine 16))
(.str "ste" wstr " ${dst16-" dstgroup "-" mode "},[a1a0]")
(+ (f-0-4 #x7) (f-4-3 #x2) (f-7-1 wbit) (f-8-4 #x2)
(.sym dst16- dstgroup - mode))
(nop)
())
)
)
(define-pmacro (ste-dst mode wstr wbit)
(begin
; like: QI .b 0
(ste-dst-dsp mode wstr wbit basic Dsp-16-u20)
(ste-dst-dsp mode wstr wbit 16-8 Dsp-24-u20)
(ste-dst-dsp mode wstr wbit 16-16 Dsp-32-u20)
)
)
;=============================================================
; Division
;-------------------------------------------------------------
(define-pmacro (div-sem divop modop opmode reg src quot rem max min)
(sequence ()
(if (eq src 0)
(set obit (const BI 1))
(sequence ((opmode quot-result) (opmode rem-result))
(set quot-result (divop opmode (ext opmode reg) src))
(set rem-result (modop opmode (ext opmode reg) src))
(set obit (orif (gt opmode quot-result max)
(lt opmode quot-result min)))
(set quot quot-result)
(set rem rem-result))))
)
;<divop>.size #imm -- for m16c and m32c
(define-pmacro (div-imm-defn mach wstr op src encoding divop modop opmode reg quot rem max min sem)
(dni (.sym op mach wstr - src)
(.str op mach wstr "-" src)
((machine mach))
(.str op wstr " #${" src "}")
encoding
(sem divop modop opmode reg src quot rem max min)
())
)
(define-pmacro (div16-imm-defn smode wstr wbit op divop modop opmode reg quot rem max min opc1 opc2 opc3 opc4 sem)
(div-imm-defn 16 wstr op (.sym Imm-16 - smode)
(+ opc1 opc2 (f-7-1 wbit) opc3 opc4 (.sym Imm-16 - smode))
divop modop opmode reg quot rem max min
sem)
)
(define-pmacro (div32-imm-defn smode wstr wbit op divop modop opmode reg quot rem max min opc1 opc2 opc3 opc4 sem)
(div-imm-defn 32 wstr op (.sym Imm-16 - smode)
(+ (f-0-4 opc1) (f-4-4 opc2) (f-8-3 opc3) (f-11-1 wbit) (f-12-4 opc4) (.sym Imm-16 - smode))
divop modop opmode reg quot rem max min
sem)
)
(define-pmacro (div-imm-mach mach op divop modop opmode max-QI min-QI max-HI min-HI opc1 opc2 opc3 opc4 sem)
(begin
(.apply (.sym div mach -imm-defn) (QI .b 0 op divop modop opmode R0 R0l R0h max-QI min-QI opc1 opc2 opc3 opc4 sem))
(.apply (.sym div mach -imm-defn) (HI .w 1 op divop modop opmode R2R0 R0 R2 max-HI min-HI opc1 opc2 opc3 opc4 sem))
)
)
(define-pmacro (div-imm op divop modop opmode max-QI min-QI max-HI min-HI opc16-1 opc16-2 opc16-3 opc16-4 opc32-1 opc32-2 opc32-3 opc32-4 sem)
(begin
(div-imm-mach 16 op divop modop opmode max-QI min-QI max-HI min-HI opc16-1 opc16-2 opc16-3 opc16-4 sem)
(div-imm-mach 32 op divop modop opmode max-QI min-QI max-HI min-HI opc32-1 opc32-2 opc32-3 opc32-4 sem)
)
)
;<divop>.size src -- for m16c and m32c
(define-pmacro (div-src-defn mach wstr op src encoding divop modop opmode reg quot rem max min sem)
(dni (.sym op mach wstr - src)
(.str op mach wstr "-" src)
((machine mach))
(.str op wstr " ${" src "}")
encoding
(sem divop modop opmode reg src quot rem max min)
())
)
(define-pmacro (div16-src-defn smode wstr wbit op divop modop opmode reg quot rem max min opc1 opc2 opc3 sem)
(div-src-defn 16 wstr op (.sym dst16-16 - smode)
(+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16 - smode))
divop modop opmode reg quot rem max min
sem)
)
(define-pmacro (div32-src-defn smode wstr wbit op divop modop opmode reg quot rem max min opc1 opc2 opc3 sem)
(begin
; Multi insns are tried for assembly in the reverse order in which they appear here, so
; define the absolute-indirect insns first in order to prevent them from being selected
; when the mode is register-indirect
; (div-src-defn 32 wstr op (.sym dst32-24-absolute-indirect- smode)
; (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-15-1 wbit) (f-18-2 opc2) (f-20-4 opc3) (.sym dst32-24-absolute-indirect - smode))
; divop modop opmode reg quot rem max min
; sem)
(div-src-defn 32 wstr op (.sym dst32-16-Unprefixed- smode)
(+ (f-0-4 opc1) (f-7-1 wbit) (f-10-2 opc2) (f-12-4 opc3) (.sym dst32-16-Unprefixed- smode))
divop modop opmode reg quot rem max min
sem)
; (div-src-defn 32 wstr op (.sym dst32-24-indirect- smode)
; (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-15-1 wbit) (f-18-2 opc2) (f-20-4 opc3) (.sym dst32-24-indirect - smode))
; divop modop opmode reg quot rem max min
; sem)
)
)
(define-pmacro (div-src-mach mach op divop modop opmode max-QI min-QI max-HI min-HI opc1 opc2 opc3 sem)
(begin
(.apply (.sym div mach -src-defn) (QI .b 0 op divop modop opmode R0 R0l R0h max-QI min-QI opc1 opc2 opc3 sem))
(.apply (.sym div mach -src-defn) (HI .w 1 op divop modop opmode R2R0 R0 R2 max-HI min-HI opc1 opc2 opc3 sem))
)
)
(define-pmacro (div-src op divop modop opmode max-QI min-QI max-HI min-HI opc16-1 opc16-2 opc16-3 opc32-1 opc32-2 opc32-3 sem)
(begin
(div-src-mach 16 op divop modop opmode max-QI min-QI max-HI min-HI opc16-1 opc16-2 opc16-3 sem)
(div-src-mach 32 op divop modop opmode max-QI min-QI max-HI min-HI opc32-1 opc32-2 opc32-3 sem)
)
)
;=============================================================
; Bit manipulation
;
(define-pmacro (bit-insn-defn mach op suffix opnd encoding sem)
(dni (.sym op mach - suffix - opnd)
(.str op mach ":" suffix " " opnd)
((machine mach))
(.str op "$" suffix " ${" opnd "}")
encoding
(sem opnd)
())
)
(define-pmacro (bitsrc16-defn op opc1 opc2 opc3 sem)
(bit-insn-defn 16 op X bit16-16
(+ opc1 opc2 opc3 bit16-16)
sem)
)
(define-pmacro (bitsrc32-defn op opc1 opc2 opc3 sem)
(begin
(bit-insn-defn 32 op X bit32-24-Prefixed
(+ (f-0-4 0) (f-4-4 1) (f-8-4 opc1) bit32-24-Prefixed (f-15-1 opc2) (f-18-3 opc3))
sem)
)
)
(define-pmacro (bitsrc-insn op opc16-1 opc16-2 opc16-3 opc32-1 opc32-2 opc32-3 sem)
(begin
(bitsrc16-defn op opc16-1 opc16-2 opc16-3 sem)
(bitsrc32-defn op opc32-1 opc32-2 opc32-3 sem)
)
)
(define-pmacro (bitdst16-defn op opc1 opc2 opc3 opc4 opc5 opc6 sem)
(begin
(bit-insn-defn 16 op G bit16-16-basic (+ opc1 opc2 opc3 bit16-16-basic) sem)
(bit-insn-defn 16 op G bit16-16-16 (+ opc1 opc2 opc3 bit16-16-16) sem)
(bit-insn-defn 16 op S bit16-11-S (+ opc4 opc5 opc6 bit16-11-S) sem)
(bit-insn-defn 16 op G bit16-16-8 (+ opc1 opc2 opc3 bit16-16-8) sem)
)
)
(define-pmacro (bitdst32-defn op opc1 opc2 opc3 sem)
(begin
(bit-insn-defn 32 op X bit32-16-Unprefixed
(+ (f-0-4 opc1) bit32-16-Unprefixed (f-7-1 opc2) (f-10-3 opc3))
sem)
)
)
(define-pmacro (bitdstnos-insn op opc16-1 opc16-2 opc16-3 opc32-1 opc32-2 opc32-3 sem)
(begin
(bitsrc16-defn op opc16-1 opc16-2 opc16-3 sem)
(bitdst32-defn op opc32-1 opc32-2 opc32-3 sem)
)
)
(define-pmacro (bitdst-insn op opc16-1 opc16-2 opc16-3 opc16-4 opc16-5 opc16-6 opc32-1 opc32-2 opc32-3 sem)
(begin
(bitdst16-defn op opc16-1 opc16-2 opc16-3 opc16-4 opc16-5 opc16-6 sem)
(bitdst32-defn op opc32-1 opc32-2 opc32-3 sem)
)
)
;=============================================================
; Bit condition
;
(define-pmacro (bitcond-insn-defn mach op bit-opnd cond-opnd encoding sem)
(dni (.sym op mach - bit-opnd - cond-opnd)
(.str op mach " " bit-opnd " " cond-opnd)
((machine mach))
(.str op "${" cond-opnd "} ${" bit-opnd "}")
encoding
(sem mach bit-opnd cond-opnd)
())
)
(define-pmacro (bitcond16-defn op opc1 opc2 opc3 sem)
(begin
(bitcond-insn-defn 16 op bit16-16-basic cond16-16 (+ opc1 opc2 opc3 bit16-16-basic cond16-16) sem)
(bitcond-insn-defn 16 op bit16-16-16 cond16-32 (+ opc1 opc2 opc3 bit16-16-16 cond16-32) sem)
(bitcond-insn-defn 16 op bit16-16-8 cond16-24 (+ opc1 opc2 opc3 bit16-16-8 cond16-24) sem)
)
)
(define-pmacro (bitcond32-defn op opc1 opc2 opc3 sem)
(begin
(bitcond-insn-defn 32 op bit32-16-24-Unprefixed cond32-40
(+ (f-0-4 opc1) bit32-16-24-Unprefixed (f-7-1 opc2) (f-10-3 opc3) cond32-40)
sem)
(bitcond-insn-defn 32 op bit32-16-16-Unprefixed cond32-32
(+ (f-0-4 opc1) bit32-16-16-Unprefixed (f-7-1 opc2) (f-10-3 opc3) cond32-32)
sem)
(bitcond-insn-defn 32 op bit32-16-8-Unprefixed cond32-24
(+ (f-0-4 opc1) bit32-16-8-Unprefixed (f-7-1 opc2) (f-10-3 opc3) cond32-24)
sem)
(bitcond-insn-defn 32 op bit32-basic-Unprefixed cond32-16
(+ (f-0-4 opc1) bit32-basic-Unprefixed (f-7-1 opc2) (f-10-3 opc3) cond32-16)
sem)
)
)
(define-pmacro (bitcond-insn op opc16-1 opc16-2 opc16-3 opc32-1 opc32-2 opc32-3 sem)
(begin
(bitcond16-defn op opc16-1 opc16-2 opc16-3 sem)
(bitcond32-defn op opc32-1 opc32-2 opc32-3 sem)
)
)
;=============================================================
;<insn>.size #imm1,#imm2,dst -- for m32c
;
(define-pmacro (insn-imm1-imm2-dst-defn src1 src2 dstgroup xmode wstr op encoding sem)
(dni (.sym op 32 wstr - src1 - src2 - dstgroup)
(.str op 32 wstr "-" src1 "-" src2 "-" dstgroup "-" xmode)
((machine 32))
(.str op wstr " #${" src1 "},#${" src2 "},${dst32-" dstgroup "-" xmode "}")
encoding
(sem xmode src1 src2 (.sym dst32- dstgroup - xmode))
())
)
; m32c Prefixed variants
(define-pmacro (insn32-imm1-imm2-dst-Prefixed-defn xmode wstr wbit base1 base2 base3 base4 op opc1 opc2 opc3 sem)
(begin
(insn-imm1-imm2-dst-defn (.sym Imm-48- xmode) (.sym Imm- base4 - xmode) 24-24-Prefixed xmode wstr op
(+ (f-0-4 0) (f-4-4 1) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3)
(.sym dst32-24-24-Prefixed- xmode) (.sym Imm-48- xmode) (.sym Imm- base4 - xmode))
sem)
(insn-imm1-imm2-dst-defn (.sym Imm-40- xmode) (.sym Imm- base3 - xmode) 24-16-Prefixed xmode wstr op
(+ (f-0-4 0) (f-4-4 1) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3)
(.sym dst32-24-16-Prefixed- xmode) (.sym Imm-40- xmode) (.sym Imm- base3 - xmode))
sem)
(insn-imm1-imm2-dst-defn (.sym Imm-32- xmode) (.sym Imm- base2 - xmode) 24-8-Prefixed xmode wstr op
(+ (f-0-4 0) (f-4-4 1) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3)
(.sym dst32-24-8-Prefixed- xmode) (.sym Imm-32- xmode) (.sym Imm- base2 - xmode))
sem)
(insn-imm1-imm2-dst-defn (.sym Imm-24- xmode) (.sym Imm- base1 - xmode) basic-Prefixed xmode wstr op
(+ (f-0-4 0) (f-4-4 1) (f-8-4 opc1) (f-18-2 opc2) (f-15-1 wbit) (f-20-4 opc3)
(.sym dst32-basic-Prefixed- xmode) (.sym Imm-24- xmode) (.sym Imm- base1 - xmode))
sem)
)
)
; m32c Unprefixed variants
(define-pmacro (insn32-imm1-imm2-dst-Unprefixed-defn xmode wstr wbit base1 base2 base3 base4 op opc1 opc2 opc3 sem)
(begin
(insn-imm1-imm2-dst-defn (.sym Imm-40- xmode) (.sym Imm- base4 - xmode) 16-24-Unprefixed xmode wstr op
(+ (f-0-4 opc1) (f-10-2 opc2) (f-7-1 wbit) (f-12-4 opc3)
(.sym dst32-16-24-Unprefixed- xmode) (.sym Imm-40- xmode) (.sym Imm- base4 - xmode))
sem)
(insn-imm1-imm2-dst-defn (.sym Imm-32- xmode) (.sym Imm- base3 - xmode) 16-16-Unprefixed xmode wstr op
(+ (f-0-4 opc1) (f-10-2 opc2) (f-7-1 wbit) (f-12-4 opc3)
(.sym dst32-16-16-Unprefixed- xmode) (.sym Imm-32- xmode) (.sym Imm- base3 - xmode))
sem)
(insn-imm1-imm2-dst-defn (.sym Imm-24- xmode) (.sym Imm- base2 - xmode) 16-8-Unprefixed xmode wstr op
(+ (f-0-4 opc1) (f-10-2 opc2) (f-7-1 wbit) (f-12-4 opc3)
(.sym dst32-16-8-Unprefixed- xmode) (.sym Imm-24- xmode) (.sym Imm- base2 - xmode))
sem)
(insn-imm1-imm2-dst-defn (.sym Imm-16- xmode) (.sym Imm- base1 - xmode) basic-Unprefixed xmode wstr op
(+ (f-0-4 opc1) (f-10-2 opc2) (f-7-1 wbit) (f-12-4 opc3)
(.sym dst32-basic-Unprefixed- xmode) (.sym Imm-16- xmode) (.sym Imm- base1 - xmode))
sem)
)
)
(define-pmacro (insn-imm1-imm2-dst-Prefixed op opc32-1 opc32-2 opc32-3 sem)
(begin
(insn32-imm1-imm2-dst-Prefixed-defn QI .b 0 32 40 48 56 op opc32-1 opc32-2 opc32-3 sem)
(insn32-imm1-imm2-dst-Prefixed-defn HI .w 1 40 48 56 64 op opc32-1 opc32-2 opc32-3 sem)
)
)
(define-pmacro (insn-imm1-imm2-dst-Unprefixed op opc32-1 opc32-2 opc32-3 sem)
(begin
(insn32-imm1-imm2-dst-Unprefixed-defn QI .b 0 24 32 40 48 op opc32-1 opc32-2 opc32-3 sem)
(insn32-imm1-imm2-dst-Unprefixed-defn HI .w 1 32 40 48 56 op opc32-1 opc32-2 opc32-3 sem)
)
)
;=============================================================
; Insn definitions
;-------------------------------------------------------------
; abs - absolute
;-------------------------------------------------------------
(define-pmacro (abs-sem mode dst)
(sequence ((mode result))
(set result (abs mode dst))
(set obit (eq result dst))
(set-z-and-s result)
(set dst result))
)
(unary-insn abs (f-0-4 7) (f-4-3 3) (f-8-4 #xF) #xA #x1 #xF abs-sem)
;-------------------------------------------------------------
; adcf - addition carry flag
;-------------------------------------------------------------
(define-pmacro (adcf-sem mode dst)
(sequence ((mode result))
(set result (addc mode dst 0 cbit))
(set obit (add-oflag mode dst 0 cbit))
(set cbit (add-cflag mode dst 0 cbit))
(set-z-and-s result)
(set dst result))
)
(unary-insn adcf (f-0-4 7) (f-4-3 3) (f-8-4 #xE) #xB #x1 #xE adcf-sem)
;-------------------------------------------------------------
; add - binary addition
;-------------------------------------------------------------
(define-pmacro (add-sem mode src1 dst)
(sequence ((mode result))
(set result (add mode src1 dst))
(set obit (add-oflag mode src1 dst 0))
(set cbit (add-cflag mode src1 dst 0))
(set-z-and-s result)
(set dst result))
)
; add.L:G #imm32,dst (m32 #2)
(binary-arith32-imm-dst-defn SI SI .l 0 add G #x8 #x3 #x1 add-sem)
; add.size:G #imm,dst (m16 #1 m32 #1)
(binary-arith-imm-dst add G (f-0-4 7) (f-4-3 3) (f-8-4 4) #x8 #x2 #xE add-sem)
; add.size:Q #imm4,dst (m16 #2 m32 #3)
(binary-arith-imm4-dst add (f-0-4 #xC) (f-4-3 4) #x7 #x3 add-sem)
(binary-arith32-imm4-dst-defn SI .l 1 0 add #x7 #x3 add-sem)
; add.b:S #imm8,dst3 (m16 #3)
(binary-arith16-b-S-imm8-dst3 add ".b" (f-0-4 8) (f-4-1 0) add-sem)
; add.BW:Q #imm4,sp (m16 #7)
(binary-arith16-Q-sp add (f-0-4 7) (f-4-4 #xD) (f-8-4 #xB) add-sem)
(dnmi add16-bQ-sp "add16-bQ-sp" ()
"add.b:q #${Imm-12-s4},sp"
(emit add16-wQ-sp Imm-12-s4))
; add.BW:G #imm,sp (m16 #6)
(binary-arith16-G-sp add (f-0-4 7) (f-4-3 6) (f-8-4 #xE) (f-12-4 #xB) add-sem)
; add.BW:G src,dst (m16 #4 m32 #6)
(binary-arith-src-dst add G (f-0-4 #xA) (f-4-3 0) #x1 #x8 add-sem)
; add.B.S src2,r0l/r0h (m16 #5)
(binary-arith16-b-S-src2 add (f-0-4 2) (f-4-1 0) add-sem)
; add.L:G src,dst (m32 #7)
(binary-arith32-src-dst-defn SI SI .l 1 add G #x1 #x2 add-sem)
; add.L:S #imm{1,2},A0/A1 (m32 #5)
(binary-arith32-l-s-imm1-an add (f-0-2 2) (f-3-4 6) add-sem)
; add.L:Q #imm3,sp (m32 #9)
(binary-arith32-l-q-imm3-sp add (f-0-2 1) (f-4-3 1) add-sem)
; add.L:S #imm8,sp (m32 #10)
(binary-arith32-l-s-imm8-sp add (f-0-4 #xb) (f-4-4 6) (f-8-4 0) (f-12-4 3) add-sem)
; add.L:G #imm16,sp (m32 #8)
(binary-arith32-l-g-imm16-sp add (f-0-4 #xb) (f-4-4 6) (f-8-4 1) (f-12-4 3) add-sem)
; add.BW:S #imm,dst2 (m32 #4)
(binary-arith32-s-imm-dst QI .b 0 add #x0 #x3 add-sem)
(binary-arith32-s-imm-dst HI .w 1 add #x0 #x3 add-sem)
;-------------------------------------------------------------
; adc - binary add with carry
;-------------------------------------------------------------
(define-pmacro (addc-sem mode src dst)
(sequence ((mode result))
(set result (addc mode src dst cbit))
(set obit (add-oflag mode src dst cbit))
(set cbit (add-cflag mode src dst cbit))
(set-z-and-s result)
(set dst result))
)
; adc.size:G #imm,dst
(binary-arith16-imm-dst-defn QI QI .b 0 adc X (f-0-4 7) (f-4-3 3) (f-8-4 6) addc-sem)
(binary-arith16-imm-dst-defn HI HI .w 1 adc X (f-0-4 7) (f-4-3 3) (f-8-4 6) addc-sem)
(binary-arith32-imm-dst-Prefixed QI QI .b 0 adc X #x8 #x2 #xE addc-sem)
(binary-arith32-imm-dst-Prefixed HI HI .w 1 adc X #x8 #x2 #xE addc-sem)
; adc.BW:G src,dst
(binary-arith16-src-dst-defn QI QI .b 0 adc X (f-0-4 #xB) (f-4-3 0) addc-sem)
(binary-arith16-src-dst-defn HI HI .w 1 adc X (f-0-4 #xB) (f-4-3 0) addc-sem)
(binary-arith32-src-dst-Prefixed QI QI .b 0 adc X #x1 #x4 addc-sem)
(binary-arith32-src-dst-Prefixed HI HI .w 1 adc X #x1 #x4 addc-sem)
;-------------------------------------------------------------
; dadc - decimal add with carry
; dadd - decimal addition
;-------------------------------------------------------------
(define-pmacro (dadc-sem mode src dst)
(sequence ((mode result))
(set result (subc mode dst src (not cbit)))
(set cbit (sub-cflag mode dst src (not cbit)))
(set-z-and-s result)
(set dst result))
)
(define-pmacro (decimal-subtraction16-insn op opc1 opc2)
(begin
; op.b #imm8,r0l
(dni (.sym op 16.b-imm8)
(.str op ".b #imm8")
((machine 16))
(.str op ".b #${Imm-16-QI},r0l")
(+ (f-0-4 #x7) (f-4-4 #xC) (f-8-4 #xE) (f-12-4 opc1) Imm-16-QI)
((.sym op -sem) QI Imm-16-QI R0l)
())
; op.w #imm16,r0
(dni (.sym op 16.w-imm16)
(.str op ".b #imm16")
((machine 16))
(.str op ".w #${Imm-16-HI},r0")
(+ (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #xE) (f-12-4 opc1) Imm-16-HI)
((.sym op -sem) HI Imm-16-HI R0)
())
; op.b #r0h,r0l
(dni (.sym op 16.b-r0h-r0l)
(.str op ".b r0h,r0l")
((machine 16))
(.str op ".b r0h,r0l")
(+ (f-0-4 #x7) (f-4-4 #xC) (f-8-4 #xE) (f-12-4 opc2))
((.sym op -sem) QI R0h R0l)
())
; op.w #r1,r0
(dni (.sym op 16.w-r1-r0)
(.str op ".b r1,r0")
((machine 16))
(.str op ".w r1,r0")
(+ (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #xE) (f-12-4 opc2))
((.sym op -sem) HI R1 R0)
())
)
)
; dadc for m16c
(decimal-subtraction16-insn dadc #xE #x6 )
; dadc.size #imm,dst
(binary-arith32-imm-dst-Prefixed QI QI .b 0 dadc X #x8 #x0 #xE dadc-sem)
(binary-arith32-imm-dst-Prefixed HI HI .w 1 dadc X #x8 #x0 #xE dadc-sem)
; dadc.BW src,dst
(binary-arith32-src-dst-Prefixed QI QI .b 0 dadc X #x1 #x8 dadc-sem)
(binary-arith32-src-dst-Prefixed HI HI .w 1 dadc X #x1 #x8 dadc-sem)
(define-pmacro (dadd-sem mode src dst)
(sequence ((mode result))
(set result (subc mode dst src 0))
(set cbit (sub-cflag mode dst src 0))
(set-z-and-s result)
(set dst result))
)
; dadd for m16c
(decimal-subtraction16-insn dadd #xC #x4)
; dadd.size #imm,dst
(binary-arith32-imm-dst-Prefixed QI QI .b 0 dadd X #x8 #x1 #xE dadd-sem)
(binary-arith32-imm-dst-Prefixed HI HI .w 1 dadd X #x8 #x1 #xE dadd-sem)
; dadd.BW src,dst
(binary-arith32-src-dst-Prefixed QI QI .b 0 dadd X #x1 #x0 dadd-sem)
(binary-arith32-src-dst-Prefixed HI HI .w 1 dadd X #x1 #x0 dadd-sem)
;-------------------------------------------------------------;
; addx - Add extend sign with no carry
;-------------------------------------------------------------;
(define-pmacro (addx-sem mode src dst)
(sequence ((SI source) (SI result))
(set source (zext SI (trunc QI src)))
(set result (add SI source dst))
(set obit (add-oflag SI source dst 0))
(set cbit (add-cflag SI source dst 0))
(set-z-and-s result)
(set dst result))
)
; addx #imm,dst
(binary-arith32-imm-dst-defn QI SI "" 0 addx X #x8 #x1 #x1 addx-sem)
; addx src,dst
(binary-arith32-src-dst-defn QI SI "" 0 addx X #x1 #x2 addx-sem)
;-------------------------------------------------------------
; adjnz - Add/Sub and branch if not zero
;-------------------------------------------------------------
(define-pmacro (arith-jnz-sem mode src dst label)
(sequence ((mode result))
(set result (add mode src dst))
(set dst result)
(if (ne result 0)
(set pc label)))
)
; adjnz.size #imm4,dst,label
(arith-jnz-imm4-dst adjnz s4 (f-0-4 #xF) (f-4-3 4) #xf #x1 arith-jnz-sem)
;-------------------------------------------------------------
; and - binary and
;-------------------------------------------------------------
(define-pmacro (and-sem mode src1 dst)
(sequence ((mode result))
(set result (and mode src1 dst))
(set-z-and-s result)
(set dst result))
)
; and.size:G #imm,dst (m16 #1 m32 #1)
(binary-arith-imm-dst and G (f-0-4 7) (f-4-3 3) (f-8-4 2) #x8 #x3 #xF and-sem)
; and.b:S #imm8,dst3 (m16 #2)
(binary-arith16-b-S-imm8-dst3 and ".b" (f-0-4 9) (f-4-1 0) and-sem)
; and.BW:G src,dst (m16 #3 m32 #3)
(binary-arith-src-dst and G (f-0-4 #x9) (f-4-3 0) #x1 #xD and-sem)
; and.B.S src2,r0l/r0h (m16 #4)
(binary-arith16-b-S-src2 and (f-0-4 1) (f-4-1 0) and-sem)
; and.BW:S #imm,dst2 (m32 #2)
(binary-arith32-s-imm-dst QI .b 0 and #x1 #x6 and-sem)
(binary-arith32-s-imm-dst HI .w 1 and #x1 #x6 and-sem)
;-------------------------------------------------------------
; band - bit and
;-------------------------------------------------------------
(define-pmacro (band-sem src)
(set cbit (and src cbit))
)
(bitsrc-insn band (f-0-4 7) (f-4-4 #xE) (f-8-4 4) #xD #x0 #x1 band-sem)
;-------------------------------------------------------------
; bclr - bit clear
;-------------------------------------------------------------
(define-pmacro (bclr-sem dst)
(set dst 0)
)
(bitdst-insn bclr (f-0-4 7) (f-4-4 #xE) (f-8-4 8) (f-0-2 1) (f-2-2 0) (f-4-1 0) #xD #x0 #x6 bclr-sem)
;-------------------------------------------------------------
; bitindex - bit index
;-------------------------------------------------------------
(define-pmacro (bitindex-sem mode dst)
(set BitIndex dst)
)
(unary-insn-defn 32 16-Unprefixed QI .b bitindex
(+ (f-0-4 #xC) (f-7-1 0) dst32-16-Unprefixed-QI (f-10-2 #x2) (f-12-4 #xE))
bitindex-sem)
(unary-insn-defn 32 16-Unprefixed HI .w bitindex
(+ (f-0-4 #xC) (f-7-1 1) dst32-16-Unprefixed-HI (f-10-2 #x2) (f-12-4 #xE))
bitindex-sem)
;-------------------------------------------------------------
; bmCnd - bit move condition
;-------------------------------------------------------------
(define-pmacro (test-condition16 cond)
(case UQI cond
((#x00) (trunc BI cbit))
((#x01) (not (or cbit zbit)))
((#x02) (trunc BI zbit))
((#x03) (trunc BI sbit))
((#x04) (or zbit (xor sbit obit)))
((#x05) (trunc BI obit))
((#x06) (xor sbit obit))
((#xf8) (not cbit))
((#xf9) (or cbit zbit))
((#xfa) (not zbit))
((#xfb) (not sbit))
((#xfc) (not (or zbit (xor sbit obit))))
((#xfd) (not obit))
((#xfe) (not (xor sbit obit)))
(else (const BI 0))
)
)
(define-pmacro (test-condition32 cond)
(case UQI cond
((#x00) (not cbit))
((#x01) (or cbit zbit))
((#x02) (not zbit))
((#x03) (not sbit))
((#x04) (not obit))
((#x05) (not (or zbit (xor sbit obit))))
((#x06) (not (xor sbit obit)))
((#x08) (trunc BI cbit))
((#x09) (not (or cbit zbit)))
((#x0a) (trunc BI zbit))
((#x0b) (trunc BI sbit))
((#x0c) (trunc BI obit))
((#x0d) (or zbit (xor sbit obit)))
((#x0e) (xor sbit obit))
(else (const BI 0))
)
)
(define-pmacro (bitcond-sem mach op cond)
(if ((.sym test-condition mach) cond)
(set op 1)
(set op 0))
)
(bitcond-insn bm (f-0-4 7) (f-4-4 #xE) (f-8-4 2) #xD #x0 #x2 bitcond-sem)
(dni bm16-c
"bm16 C"
((machine 16))
"bm$cond16c c"
(+ (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #xD) cond16c)
(bitcond-sem 16 cbit cond16c)
())
(dni bm32-c
"bm32 C"
((machine 32))
"bm$cond32 c"
(+ (f-0-4 #xD) (f-4-4 #x9) (f-8-1 0) (f-10-3 5) cond32)
(bitcond-sem 32 cbit cond32)
())
;-------------------------------------------------------------
; bnand
;-------------------------------------------------------------
(define-pmacro (bnand-sem src)
(set cbit (and (inv src) cbit))
)
(bitsrc-insn bnand (f-0-4 7) (f-4-4 #xE) (f-8-4 5) #xD #x0 #x3 bnand-sem)
;-------------------------------------------------------------
; bnor
;-------------------------------------------------------------
(define-pmacro (bnor-sem src)
(set cbit (or (inv src) cbit))
)
(bitsrc-insn bnor (f-0-4 7) (f-4-4 #xE) (f-8-4 7) #xD #x0 #x6 bnor-sem)
;-------------------------------------------------------------
; bnot
;-------------------------------------------------------------
(define-pmacro (bnot-sem dst)
(set dst (inv dst))
)
(bitdst-insn bnot (f-0-4 7) (f-4-4 #xE) (f-8-4 #xA) (f-0-2 1) (f-2-2 1) (f-4-1 0) #xD #x0 #x3 bnot-sem)
;-------------------------------------------------------------
; bntst
;-------------------------------------------------------------
(define-pmacro (bntst-sem src)
(set cbit (inv src))
(set zbit (inv src))
)
(bitsrc-insn bntst (f-0-4 7) (f-4-4 #xE) (f-8-4 3) #xD #x0 #x0 bntst-sem)
;-------------------------------------------------------------
; bnxor
;-------------------------------------------------------------
(define-pmacro (bnxor-sem src)
(set cbit (xor (inv src) cbit))
)
(bitsrc-insn bnxor (f-0-4 7) (f-4-4 #xE) (f-8-4 #xD) #xD #x0 #x7 bnxor-sem)
;-------------------------------------------------------------
; bor
;-------------------------------------------------------------
(define-pmacro (bor-sem src)
(set cbit (or src cbit))
)
(bitsrc-insn bor (f-0-4 7) (f-4-4 #xE) (f-8-4 #x6) #xD #x0 #x4 bor-sem)
;-------------------------------------------------------------
; brk
;-------------------------------------------------------------
(dni brk16
"brk"
((machine 16))
"brk"
(+ (f-0-4 #x0) (f-4-4 #x0))
(nop)
())
(dni brk32
"brk"
((machine 32))
"brk"
(+ (f-0-4 #x0) (f-4-4 #x0))
(nop)
())
;-------------------------------------------------------------
; brk2
;-------------------------------------------------------------
(dni brk232
"brk2"
((machine 32))
"brk2"
(+ (f-0-4 #x0) (f-4-4 #x8))
(nop)
())
;-------------------------------------------------------------
; bset
;-------------------------------------------------------------
(define-pmacro (bset-sem dst)
(set dst 1)
)
(bitdst-insn bset (f-0-4 7) (f-4-4 #xE) (f-8-4 9) (f-0-2 1) (f-2-2 0) (f-4-1 1) #xD #x0 #x7 bset-sem)
;-------------------------------------------------------------
; btst
;-------------------------------------------------------------
(define-pmacro (btst-sem dst)
(set zbit (inv dst))
(set cbit dst)
)
(bitdst16-defn btst (f-0-4 7) (f-4-4 #xE) (f-8-4 #xB) (f-0-2 1) (f-2-2 1) (f-4-1 1) btst-sem)
(bit-insn-defn 32 btst G bit32-16-Unprefixed
(+ (f-0-4 #xD) bit32-16-Unprefixed (f-7-1 #x0) (f-10-3 #x0))
btst-sem)
(dni btst.s "btst:s" ((machine 32))
"btst:s ${Bit3-S},${Dsp-8-u16}"
(+ (f-0-2 #x0) (f-4-3 #x5) Bit3-S Dsp-8-u16)
() ())
;-------------------------------------------------------------
; btstc
;-------------------------------------------------------------
(define-pmacro (btstc-sem dst)
(set zbit (inv dst))
(set cbit dst)
(set dst (const 0))
)
(bitdstnos-insn btstc (f-0-4 7) (f-4-4 #xE) (f-8-4 #x0) #xD #x0 #x4 btstc-sem)
;-------------------------------------------------------------
; btsts
;-------------------------------------------------------------
(define-pmacro (btsts-sem dst)
(set zbit (inv dst))
(set cbit dst)
(set dst (const 0))
)
(bitdstnos-insn btsts (f-0-4 7) (f-4-4 #xE) (f-8-4 #x1) #xD #x0 #x5 btsts-sem)
;-------------------------------------------------------------
; bxor
;-------------------------------------------------------------
(define-pmacro (bxor-sem src)
(set cbit (xor src cbit))
)
(bitsrc-insn bxor (f-0-4 7) (f-4-4 #xE) (f-8-4 #xC) #xD #x0 #x5 bxor-sem)
;-------------------------------------------------------------
; clip
;-------------------------------------------------------------
(define-pmacro (clip-sem mode imm1 imm2 dest)
(sequence ()
(if (gt mode imm1 dest)
(set dest imm1))
(if (lt mode imm2 dest)
(set dest imm2)))
)
(insn-imm1-imm2-dst-Prefixed clip #x8 #x3 #xE clip-sem)
;-------------------------------------------------------------
; cmp - binary compare
;-------------------------------------------------------------
(define-pmacro (cmp-sem mode src1 dst)
(sequence ((mode result))
(set result (sub mode dst src1))
(set obit (sub-oflag mode dst src1 0))
(set cbit (not (sub-cflag mode dst src1 0)))
(set-z-and-s result))
)
; cmp.L:G #imm32,dst (m32 #2)
(binary-arith32-imm-dst-defn SI SI .l 0 cmp G #xA #x3 #x1 cmp-sem)
; cmp.size:G #imm,dst (m16 #1 m32 #1)
(binary-arith-imm-dst cmp G (f-0-4 7) (f-4-3 3) (f-8-4 8) #x9 #x2 #xE cmp-sem)
; cmp.size:Q #imm4,dst (m16 #2 m32 #3)
(binary-arith-imm4-dst cmp (f-0-4 #xD) (f-4-3 0) #x7 #x1 cmp-sem)
; cmp.b:S #imm8,dst3 (m16 #3)
(binary-arith16-b-S-imm8-dst3 cmp ".b" (f-0-4 #xE) (f-4-1 0) cmp-sem)
; cmp.BW:G src,dst (m16 #4 m32 #5)
(binary-arith-src-dst cmp G (f-0-4 #xC) (f-4-3 0) #x1 #x6 cmp-sem)
; cmp.B.S src2,r0l/r0h (m16 #5)
(binary-arith16-b-S-src2 cmp (f-0-4 3) (f-4-1 1) cmp-sem)
; cmp.L:G src,dst (m32 #6)
(binary-arith32-src-dst-defn SI SI .l 1 cmp G #x1 #x1 cmp-sem)
; cmp.BW:S #imm,dst2 (m32 #4)
(binary-arith32-s-imm-dst QI .b 0 cmp #x1 #x3 cmp-sem)
(binary-arith32-s-imm-dst HI .w 1 cmp #x1 #x3 cmp-sem)
; cmp.BW:s src2,r0[l] (m32 #7)
(binary-arith32-S-src2 cmp QI .b 0 (f-0-2 1) (f-4-3 0) cmp-sem)
(binary-arith32-S-src2 cmp HI .w 1 (f-0-2 1) (f-4-3 0) cmp-sem)
;-------------------------------------------------------------
; cmpx - binary compare extend sign
;-------------------------------------------------------------
(define-pmacro (cmpx-sem mode src1 dst)
(sequence ((mode result))
(set result (sub mode dst (ext mode src1)))
(set obit (sub-oflag mode dst (ext mode src1) 0))
(set cbit (sub-cflag mode dst (ext mode src1) 0))
(set-z-and-s result))
)
(binary-arith32-imm-dst-defn QI SI "" 0 cmpx X #xA #x1 #x1 cmpx-sem)
;-------------------------------------------------------------
; dec - decrement
;-------------------------------------------------------------
(define-pmacro (dec-sem mode dest)
(sequence ((mode result))
(set result (sub mode dest 1))
(set-z-and-s result)
(set dest result))
)
(dni dec16.b
"dec.b Dst16-3-S-8"
((machine 16))
"dec.b ${Dst16-3-S-8}"
(+ (f-0-4 #xA) (f-4-1 #x1) Dst16-3-S-8)
(dec-sem QI Dst16-3-S-8)
())
(dni dec16.w
"dec.w Dst16An-S"
((machine 16))
"dec.w ${Dst16An-S}"
(+ (f-0-4 #xF) (f-5-3 #x2) Dst16An-S)
(dec-sem HI Dst16An-S)
())
(unary32-defn QI .b 0 dec #xB #x0 #xE dec-sem)
(unary32-defn HI .w 1 dec #xB #x0 #xE dec-sem)
;-------------------------------------------------------------
; div - divide
; divu - divide unsigned
; divx - divide extension
;-------------------------------------------------------------
; div.BW #imm
(div-imm div div mod SI 127 -128 32767 -32768 (f-0-4 #x7) (f-4-3 6) (f-8-4 #xE) (f-12-4 #x1) #xB #x0 #x2 #x3 div-sem)
(div-imm divu udiv umod USI 255 0 65535 0 (f-0-4 #x7) (f-4-3 6) (f-8-4 #xE) (f-12-4 #x0) #xB #x0 #x0 #x3 div-sem)
(div-imm divx div mod SI 127 -128 32767 -32768 (f-0-4 #x7) (f-4-3 6) (f-8-4 #xE) (f-12-4 #x3) #xB #x2 #x2 #x3 div-sem)
; div.BW src
(div-src div div mod SI 127 -128 32767 -32768 (f-0-4 #x7) (f-4-3 3) (f-8-4 #xD) #x8 #x1 #xE div-sem)
(div-src divu udiv umod USI 255 0 65535 0 (f-0-4 #x7) (f-4-3 3) (f-8-4 #xC) #x8 #x0 #xE div-sem)
(div-src divx div mod SI 127 -128 32767 -32768 (f-0-4 #x7) (f-4-3 3) (f-8-4 #x9) #x9 #x1 #xE div-sem)
(div-src-defn 32 .l div dst32-24-Prefixed-SI
(+ (f-0-4 0) (f-4-4 1) (f-8-4 #xA) (f-15-1 1) (f-18-2 #x1) (f-20-4 #xf) dst32-24-Prefixed-SI)
div mod SI R2R0 R2R0 NoRemainder #x7fffffff (neg SI #x80000000)
div-sem)
(div-src-defn 32 .l divu dst32-24-Prefixed-SI
(+ (f-0-4 0) (f-4-4 1) (f-8-4 #xA) (f-15-1 1) (f-18-2 #x0) (f-20-4 #xf) dst32-24-Prefixed-SI)
udiv umod USI R2R0 R2R0 NoRemainder #x80000000 0
div-sem)
(div-src-defn 32 .l divx dst32-24-Prefixed-SI
(+ (f-0-4 0) (f-4-4 1) (f-8-4 #xA) (f-15-1 1) (f-18-2 #x2) (f-20-4 #xf) dst32-24-Prefixed-SI)
div mod SI R2R0 R2R0 NoRemainder #x7fffffff (neg SI #x80000000)
div-sem)
;-------------------------------------------------------------
; dsbb - decimal subtraction with borrow
; dsub - decimal subtraction
;-------------------------------------------------------------
(define-pmacro (dsbb-sem mode src dst)
(sequence ((mode result))
(set result (subc mode dst src (not cbit)))
(set cbit (sub-cflag mode dst src (not cbit)))
(set-z-and-s result)
(set dst result))
)
; dsbb for m16c
(decimal-subtraction16-insn dsbb #xF #x7)
; dsbb.size #imm,dst
(binary-arith32-imm-dst-Prefixed QI QI .b 0 dsbb X #x9 #x0 #xE dsbb-sem)
(binary-arith32-imm-dst-Prefixed HI HI .w 1 dsbb X #x9 #x0 #xE dsbb-sem)
; dsbb.BW src,dst
(binary-arith32-src-dst-Prefixed QI QI .b 0 dsbb X #x1 #xA dsbb-sem)
(binary-arith32-src-dst-Prefixed HI HI .w 1 dsbb X #x1 #xA dsbb-sem)
(define-pmacro (dsub-sem mode src dst)
(sequence ((mode result))
(set result (subc mode dst src 0))
(set cbit (sub-cflag mode dst src 0))
(set-z-and-s result)
(set dst result))
)
; dsub for m16c
(decimal-subtraction16-insn dsub #xD #x5)
; dsub.size #imm,dst
(binary-arith32-imm-dst-Prefixed QI QI .b 0 dsub X #x9 #x1 #xE dsub-sem)
(binary-arith32-imm-dst-Prefixed HI HI .w 1 dsub X #x9 #x1 #xE dsub-sem)
; dsub.BW src,dst
(binary-arith32-src-dst-Prefixed QI QI .b 0 dsub X #x1 #x2 dsub-sem)
(binary-arith32-src-dst-Prefixed HI HI .w 1 dsub X #x1 #x2 dsub-sem)
;-------------------------------------------------------------
; sub - binary subtraction
;-------------------------------------------------------------
(define-pmacro (sub-sem mode src1 dst)
(sequence ((mode result))
(set result (sub mode dst src1))
(set obit (sub-oflag mode dst src1 0))
(set cbit (sub-cflag mode dst src1 0))
(set dst result)
(set-z-and-s result)))
; sub.size:G #imm,dst (m16 #1 m32 #1)
(binary-arith-imm-dst sub G (f-0-4 7) (f-4-3 3) (f-8-4 5) #x8 #x3 #xE sub-sem)
; sub.b:S #imm8,dst3 (m16 #2)
(binary-arith16-b-S-imm8-dst3 sub ".b" (f-0-4 8) (f-4-1 1) sub-sem)
; sub.BW:G src,dst (m16 #3 m32 #4)
(binary-arith-src-dst sub G (f-0-4 #xA) (f-4-3 4) #x1 #xA sub-sem)
; sub.B.S src2,r0l/r0h (m16 #4)
(binary-arith16-b-S-src2 sub (f-0-4 2) (f-4-1 1) sub-sem)
; sub.L:G #imm32,dst (m32 #2)
(binary-arith32-imm-dst-defn SI SI .l 0 sub G #x9 #x3 #x1 sub-sem)
; sub.BW:S #imm,dst2 (m32 #3)
(binary-arith32-s-imm-dst QI .b 0 sub #x0 #x7 sub-sem)
(binary-arith32-s-imm-dst HI .w 1 sub #x0 #x7 sub-sem)
; sub.L:G src,dst (m32 #5)
(binary-arith32-src-dst-defn SI SI .l 1 sub G #x1 #x0 sub-sem)
;-------------------------------------------------------------
; enter - enter function
; exitd - exit and deallocate stack frame
;-------------------------------------------------------------
(define-pmacro (enter16-sem mach amt)
(sequence ()
(set (reg h-sp) (sub (reg h-sp) 2))
(set (mem16 HI (reg h-sp)) (reg h-fb))
(set (reg h-fb) (reg h-sp))
(set (reg h-sp) (sub (reg h-sp) amt))))
(define-pmacro (exit16-sem mach)
(sequence ((SI newpc))
(set (reg h-sp) (reg h-fb))
(set (reg h-fb) (mem16 HI (reg h-sp)))
(set (reg h-sp) (add (reg h-sp) 2))
(set newpc (mem16 HI (reg h-sp)))
(set (reg h-sp) (add (reg h-sp) 2))
(set newpc (or newpc (sll (mem16 QI (reg h-sp)) (const 16))))
(set (reg h-sp) (add (reg h-sp) 1))
(set pc newpc)))
(define-pmacro (enter32-sem mach amt)
(sequence ()
(set (reg h-sp) (sub (reg h-sp) 4))
(set (mem32 SI (reg h-sp)) (reg h-fb))
(set (reg h-fb) (reg h-sp))
(set (reg h-sp) (sub (reg h-sp) amt))))
(define-pmacro (exit32-sem mach)
(sequence ((SI newpc))
(set (reg h-sp) (reg h-fb))
(set (reg h-fb) (mem32 SI (reg h-sp)))
(set (reg h-sp) (add (reg h-sp) 4))
(set newpc (mem32 SI (reg h-sp)))
(set (reg h-sp) (add (reg h-sp) 4))
(set pc newpc)))
(dni enter16 "enter #Imm-16-QI" ((machine 16))
("enter #${Dsp-16-u8}")
(+ (f-0-4 7) (f-4-4 #xC) (f-8-4 #xF) (f-12-4 2) Dsp-16-u8)
(enter16-sem 16 Dsp-16-u8)
())
(dni exitd16 "exitd" ((machine 16))
("exitd")
(+ (f-0-4 7) (f-4-4 #xD) (f-8-4 #xF) (f-12-4 2))
(exit16-sem 16)
())
(dni enter32 "enter #Imm-8-QI" ((machine 32))
("enter #${Dsp-8-u8}")
(+ (f-0-4 #xE) (f-4-4 #xC) Dsp-8-u8)
(enter32-sem 32 Dsp-8-u8)
())
(dni exitd32 "exitd" ((machine 32))
("exitd")
(+ (f-0-4 #xF) (f-4-4 #xC))
(exit32-sem 32)
())
;-------------------------------------------------------------
; fclr - flag register clear
; fset - flag register set
;-------------------------------------------------------------
(define-pmacro (set-flags-sem flag)
(sequence ((SI tmp))
(case DFLT flag
((#x0) (set cbit 1))
((#x1) (set dbit 1))
((#x2) (set zbit 1))
((#x3) (set sbit 1))
((#x4) (set bbit 1))
((#x5) (set obit 1))
((#x6) (set ibit 1))
((#x7) (set ubit 1)))
)
)
(define-pmacro (clear-flags-sem flag)
(sequence ((SI tmp))
(case DFLT flag
((#x0) (set cbit 0))
((#x1) (set dbit 0))
((#x2) (set zbit 0))
((#x3) (set sbit 0))
((#x4) (set bbit 0))
((#x5) (set obit 0))
((#x6) (set ibit 0))
((#x7) (set ubit 0)))
)
)
(dni fclr16 "fclr flag" ((machine 16))
("fclr ${flags16}")
(+ (f-0-4 #xE) (f-4-4 #xB) (f-8-1 0) flags16 (f-12-4 5))
(clear-flags-sem flags16)
())
(dni fset16 "fset flag" ((machine 16))
("fset ${flags16}")
(+ (f-0-4 #xE) (f-4-4 #xB) (f-8-1 0) flags16 (f-12-4 4))
(set-flags-sem flags16)
())
(dni fclr "fclr" ((machine 32))
("fclr ${flags32}")
(+ (f-0-4 #xD) (f-4-4 3) (f-8-4 #xE) (f-12-1 1) flags32)
(clear-flags-sem flags32)
())
(dni fset "fset" ((machine 32))
("fset ${flags32}")
(+ (f-0-4 #xD) (f-4-4 1) (f-8-4 #xE) (f-12-1 1) flags32)
(set-flags-sem flags32)
())
;-------------------------------------------------------------
; inc - increment
;-------------------------------------------------------------
(define-pmacro (inc-sem mode dest)
(sequence ((mode result))
(set result (add mode dest 1))
(set-z-and-s result)
(set dest result))
)
(dni inc16.b
"inc.b Dst16-3-S-8"
((machine 16))
"inc.b ${Dst16-3-S-8}"
(+ (f-0-4 #xA) (f-4-1 #x0) Dst16-3-S-8)
(inc-sem QI Dst16-3-S-8)
())
(dni inc16.w
"inc.w Dst16An-S"
((machine 16))
"inc.w ${Dst16An-S}"
(+ (f-0-4 #xB) (f-5-3 #x2) Dst16An-S)
(inc-sem HI Dst16An-S)
())
(unary32-defn QI .b 0 inc #xA #x0 #xE inc-sem)
(unary32-defn HI .w 1 inc #xA #x0 #xE inc-sem)
;-------------------------------------------------------------
; freit - fast return from interrupt (m32)
; int - interrupt
; into - interrupt on overflow
;-------------------------------------------------------------
; ??? semantics
(dni freit32 "FREIT" ((machine 32))
("freit")
(+ (f-0-4 9) (f-4-4 #xF))
(nop)
())
(dni int16 "int Dsp-10-u6" ((machine 16))
("int #${Dsp-10-u6}")
(+ (f-0-4 #xE) (f-4-4 #xB) (f-8-2 3) Dsp-10-u6)
(c-call VOID "do_int" pc Dsp-10-u6)
())
(dni into16 "into" ((machine 16))
("into")
(+ (f-0-4 #xF) (f-4-4 6))
(nop)
())
(dni int32 "int Dsp-8-u6" ((machine 32))
("int #${Dsp-8-u6}")
(+ (f-0-4 #xB) (f-4-4 #xE) Dsp-8-u6 (f-14-2 0))
(c-call VOID "do_int" pc Dsp-8-u6)
())
(dni into32 "into" ((machine 32))
("into")
(+ (f-0-4 #xB) (f-4-4 #xF))
(nop)
())
;-------------------------------------------------------------
; index (m32c)
;-------------------------------------------------------------
; TODO add support to insns allowing index
(define-pmacro (indexb-sem mode d) (set SrcIndex d) (set DstIndex d))
(define-pmacro (indexbd-sem mode d) (set SrcIndex (const 0)) (set DstIndex d))
(define-pmacro (indexbs-sem mode d) (set SrcIndex d) (set DstIndex (const 0)))
(define-pmacro (indexw-sem mode d)
(set SrcIndex (sll d (const 2))) (set DstIndex (sll d (const 2))))
(define-pmacro (indexwd-sem mode d)
(set SrcIndex (const 0)) (set DstIndex (sll d (const 2))))
(define-pmacro (indexws-sem mode d)
(set SrcIndex (sll d (const 2))) (set DstIndex (const 0)))
(define-pmacro (indexl-sem mode d)
(set SrcIndex d) (set DstIndex (sll d (const 2))))
(define-pmacro (indexld-sem mode d)
(set SrcIndex (const 0)) (set DstIndex (sll d (const 2))))
(define-pmacro (indexls-sem mode d)
(set SrcIndex (sll d (const 2))) (set DstIndex (const 0)))
; Note that "wbit" not where the size bit goes here, hence, it's
; always 0 in these calls but op2 differs instead.
; indexb src (index byte)
(unary32-defn QI .b 0 indexb #x8 0 #x3 indexb-sem)
(unary32-defn HI .w 0 indexb #x8 1 #x3 indexb-sem)
; indexbd src (index byte dest)
(unary32-defn QI .b 0 indexbd #xA 0 3 indexbd-sem)
(unary32-defn HI .w 0 indexbd #xA 1 3 indexbd-sem)
; indexbs src (index byte src)
(unary32-defn QI .b 0 indexbs #xC 0 3 indexbs-sem)
(unary32-defn HI .w 0 indexbs #xC 1 3 indexbs-sem)
; indexl src (index long)
(unary32-defn QI .b 0 indexl 9 2 3 indexl-sem)
(unary32-defn HI .w 0 indexl 9 3 3 indexl-sem)
; indexld src (index long dest)
(unary32-defn QI .b 0 indexld #xB 2 3 indexld-sem)
(unary32-defn HI .w 0 indexld #xB 3 3 indexld-sem)
; indexls src (index long src)
(unary32-defn QI .b 0 indexls 9 0 3 indexls-sem)
(unary32-defn HI .w 0 indexls 9 1 3 indexls-sem)
; indexw src (index word)
(unary32-defn QI .b 0 indexw 8 2 3 indexw-sem)
(unary32-defn HI .w 0 indexw 8 3 3 indexw-sem)
; indexwd src (index word dest)
(unary32-defn QI .b 0 indexwd #xA 2 3 indexwd-sem)
(unary32-defn HI .w 0 indexwd #xA 3 3 indexwd-sem)
; indexws (index word src)
(unary32-defn QI .b 0 indexws #xC 2 3 indexws-sem)
(unary32-defn HI .w 0 indexws #xC 3 3 indexws-sem)
;-------------------------------------------------------------
; jcc - jump on condition
;-------------------------------------------------------------
(define-pmacro (jcnd32-sem cnd label)
(sequence ()
(case DFLT cnd
((#x00) (if (not cbit) (set pc label))) ;ltu nc
((#x01) (if (not (and cbit (not zbit))) (set pc label))) ;leu
((#x02) (if (not zbit) (set pc label))) ;ne nz
((#x03) (if (not sbit) (set pc label))) ;pz
((#x04) (if (not obit) (set pc label))) ;no
((#x05) (if (not (or zbit (xor sbit obit))) (set pc label))) ;gt
((#x06) (if (not (xor sbit obit)) (set pc label))) ;ge
((#x08) (if (trunc BI cbit) (set pc label))) ;geu c
((#x09) (if (and cbit (not zbit)) (set pc label))) ;gtu
((#x0a) (if (trunc BI zbit) (set pc label))) ;eq z
((#x0b) (if (trunc BI sbit) (set pc label))) ;n
((#x0c) (if (trunc BI obit) (set pc label))) ;o
((#x0d) (if (or zbit (xor sbit obit)) (set pc label))) ;le
((#x0e) (if (xor sbit obit) (set pc label))) ;lt
)
)
)
(define-pmacro (jcnd16-sem cnd label)
(sequence ()
(case DFLT cnd
((#x00) (if (trunc BI cbit) (set pc label))) ;geu c
((#x01) (if (and cbit (not zbit)) (set pc label))) ;gtu
((#x02) (if (trunc BI zbit) (set pc label))) ;eq z
((#x03) (if (trunc BI sbit) (set pc label))) ;n
((#x04) (if (not cbit) (set pc label))) ;ltu nc
((#x05) (if (not (and cbit (not zbit))) (set pc label))) ;leu
((#x06) (if (not zbit) (set pc label))) ;ne nz
((#x07) (if (not sbit) (set pc label))) ;pz
((#x08) (if (or zbit (xor sbit obit)) (set pc label))) ;le
((#x09) (if (trunc BI obit) (set pc label))) ;o
((#x0a) (if (not (xor sbit obit)) (set pc label))) ;ge
((#x0c) (if (not (or zbit (xor sbit obit))) (set pc label))) ;gt
((#x0d) (if (not obit) (set pc label))) ;no
((#x0e) (if (xor sbit obit) (set pc label))) ;lt
)
)
)
(dni jcnd16-5
"jCnd label"
(RL_JUMP RELAXABLE (machine 16))
"j$cond16j5 ${Lab-8-8}"
(+ (f-0-4 #x6) (f-4-1 1) cond16j5 Lab-8-8)
(jcnd16-sem cond16j5 Lab-8-8)
()
)
(dni jcnd16
"jCnd label"
(RL_JUMP RELAXABLE (machine 16))
"j$cond16j ${Lab-16-8}"
(+ (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #xC) cond16j Lab-16-8)
(jcnd16-sem cond16j Lab-16-8)
()
)
(dni jcnd32
"jCnd label"
(RL_JUMP RELAXABLE (machine 32))
"j$cond32j ${Lab-8-8}"
(+ (f-0-1 1) (f-4-3 5) cond32j Lab-8-8)
(jcnd32-sem cond32j Lab-8-8)
()
)
;-------------------------------------------------------------
; jmp - jump
;-------------------------------------------------------------
; jmp.s label3 (m16 #1)
(dni jmp16.s "jmp.s Lab-5-3" (RL_JUMP RELAXABLE (machine 16))
("jmp.s ${Lab-5-3}")
(+ (f-0-4 6) (f-4-1 0) Lab-5-3)
(sequence () (set pc Lab-5-3))
())
; jmp.b label8 (m16 #2)
(dni jmp16.b "jmp.b Lab-8-8" (RL_JUMP RELAXABLE (machine 16))
("jmp.b ${Lab-8-8}")
(+ (f-0-4 #xF) (f-4-4 #xE) Lab-8-8)
(sequence () (set pc Lab-8-8))
())
; jmp.w label16 (m16 #3)
(dni jmp16.w "jmp.w Lab-8-16" (RL_JUMP RELAXABLE (machine 16))
("jmp.w ${Lab-8-16}")
(+ (f-0-4 #xF) (f-4-4 4) Lab-8-16)
(sequence () (set pc Lab-8-16))
())
; jmp.a label24 (m16 #4)
(dni jmp16.a "jmp.a Lab-8-24" (RL_JUMP RELAXABLE (machine 16))
("jmp.a ${Lab-8-24}")
(+ (f-0-4 #xF) (f-4-4 #xC) Lab-8-24)
(sequence () (set pc Lab-8-24))
())
(define-pmacro (jmp16-sem mode dst)
(set pc (and dst #xfffff))
)
(define-pmacro (jmp32-sem mode dst)
(set pc dst)
)
; jmpi.w dst (m16 #1 m32 #2)
(unary-insn-defn 16 16 HI .w jmpi (+ (f-0-4 7) (f-4-4 #xD) (f-8-4 2) dst16-16-HI) jmp16-sem)
(unary-insn-defn 32 16-Unprefixed HI .w jmpi (+ (f-0-4 #xC) (f-7-1 1) dst32-16-Unprefixed-HI (f-10-2 #x0) (f-12-4 #xF)) jmp32-sem)
; jmpi.a dst (m16 #2 m32 #2)
(unary-insn-defn 16 16 SI .a jmpi (+ (f-0-4 7) (f-4-4 #xD) (f-8-4 0) dst16-16-SI) jmp16-sem)
(unary-insn-defn 32 16-Unprefixed SI .a jmpi (+ (f-0-4 #x8) (f-7-1 0) dst32-16-Unprefixed-SI (f-10-2 #x0) (f-12-4 1)) jmp32-sem)
; jmps imm8 (m16 #1)
(dni jmps16 "jmps Imm-8-QI" ((machine 16))
("jmps #${Imm-8-QI}")
(+ (f-0-4 #xE) (f-4-4 #xE) Imm-8-QI)
(sequence () (set pc Imm-8-QI))
())
; jmp.s label3 (m32 #1)
(dni jmp32.s
"jmp.s label"
(RL_JUMP RELAXABLE (machine 32))
"jmp.s ${Lab32-jmp-s}"
(+ (f-0-2 1) (f-4-3 5) Lab32-jmp-s)
(set pc Lab32-jmp-s)
()
)
; jmp.b label8 (m32 #2)
(dni jmp32.b "jmp.b Lab-8-8" (RL_JUMP RELAXABLE (machine 32))
("jmp.b ${Lab-8-8}")
(+ (f-0-4 #xB) (f-4-4 #xB) Lab-8-8)
(set pc Lab-8-8)
())
; jmp.w label16 (m32 #3)
(dni jmp32.w "jmp.w Lab-8-16" (RL_JUMP RELAXABLE (machine 32))
("jmp.w ${Lab-8-16}")
(+ (f-0-4 #xC) (f-4-4 #xE) Lab-8-16)
(set pc Lab-8-16)
())
; jmp.a label24 (m32 #4)
(dni jmp32.a "jmp.a Lab-8-24" (RL_JUMP RELAXABLE (machine 32))
("jmp.a ${Lab-8-24}")
(+ (f-0-4 #xC) (f-4-4 #xC) Lab-8-24)
(set pc Lab-8-24)
())
; jmp.s imm8 (m32 #1)
(dni jmps32 "jmps Imm-8-QI" (RL_JUMP (machine 32))
("jmps #${Imm-8-QI}")
(+ (f-0-4 #xD) (f-4-4 #xC) Imm-8-QI)
(set pc Imm-8-QI)
())
;-------------------------------------------------------------
; jsr jump subroutine
;-------------------------------------------------------------
(define-pmacro (jsr16-sem length dst)
(sequence ((SI tpc))
(set tpc (add pc length))
(set (reg h-sp) (sub (reg h-sp) 2))
(set (mem16 HI (reg h-sp)) (srl (and tpc #xffff00) 8))
(set (reg h-sp) (sub (reg h-sp) 1))
(set (mem16 QI (reg h-sp)) (and tpc #xff))
(set pc dst)
)
)
(define-pmacro (jsr32-sem length dst)
(sequence ((SI tpc))
(set tpc (add pc length))
(set (reg h-sp) (sub (reg h-sp) 2))
(set (mem32 HI (reg h-sp)) (srl (and tpc #xffff0000) 16))
(set (reg h-sp) (sub (reg h-sp) 2))
(set (mem32 HI (reg h-sp)) (and tpc #xffff))
(set pc dst)
)
)
; jsr.w label16 (m16 #1)
(dni jsr16.w "jsr.w Lab-8-16" (RL_JUMP RELAXABLE (machine 16))
("jsr.w ${Lab-8-16}")
(+ (f-0-4 #xF) (f-4-4 5) Lab-8-16)
(jsr16-sem 3 Lab-8-16)
())
; jsr.a label24 (m16 #2)
(dni jsr16.a "jsr.a Lab-8-24" (RL_JUMP RELAXABLE (machine 16))
("jsr.a ${Lab-8-24}")
(+ (f-0-4 #xF) (f-4-4 #xD) Lab-8-24)
(jsr16-sem 4 Lab-8-24)
())
(define-pmacro (jsri-defn mode op16 op16-1 op16-2 op16-3 op16-sem
op32 op32-1 op32-2 op32-3 op32-4 op32-sem len)
(begin
(dni (.sym jsri16 mode - op16)
(.str "jsri." mode " " op16)
(RL_1ADDR (machine 16))
(.str "jsri." mode " ${" op16 "}")
(+ op16-1 op16-2 op16-3 op16)
(op16-sem len op16)
())
(dni (.sym jsri32 mode - op32)
(.str "jsri." mode " " op32)
(RL_1ADDR (machine 32))
(.str "jsri." mode " ${" op32 "}")
(+ op32-1 op32-2 op32-3 op32-4 op32)
(op32-sem len op32)
())
)
)
; jsri.w dst (m16 #1 m32 #1))
(jsri-defn w dst16-16-8-HI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x3) jsr16-sem
dst32-16-8-Unprefixed-HI (f-0-4 #xC) (f-7-1 1) (f-10-2 #x1) (f-12-4 #xF) jsr32-sem 3)
(jsri-defn w dst16-16-16-HI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x3) jsr16-sem
dst32-16-16-Unprefixed-HI (f-0-4 #xC) (f-7-1 1) (f-10-2 #x1) (f-12-4 #xF) jsr32-sem 4)
(jsri-defn w dst16-basic-HI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x3) jsr16-sem
dst32-basic-Unprefixed-HI (f-0-4 #xC) (f-7-1 1) (f-10-2 #x1) (f-12-4 #xF) jsr32-sem 2)
(dni jsri32.w "jsr.w dst32-16-24-Unprefixed-HI" (RL_1ADDR (machine 32))
("jsri.w ${dst32-16-24-Unprefixed-HI}")
(+ (f-0-4 #xC) (f-7-1 1) dst32-16-24-Unprefixed-HI (f-10-2 #x1) (f-12-4 #xF))
(jsr32-sem 6 dst32-16-24-Unprefixed-HI)
())
; jsri.a (m16 #2 m32 #2)
(jsri-defn a dst16-16-8-SI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x1) jsr16-sem
dst32-16-8-Unprefixed-SI (f-0-4 #x9) (f-7-1 0) (f-10-2 #x0) (f-12-4 #x1) jsr32-sem 3)
(jsri-defn a dst16-16-16-SI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x1) jsr16-sem
dst32-16-16-Unprefixed-SI (f-0-4 #x9) (f-7-1 0) (f-10-2 #x0) (f-12-4 #x1) jsr32-sem 4)
(jsri-defn a dst16-basic-SI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x1) jsr16-sem
dst32-basic-Unprefixed-SI (f-0-4 #x9) (f-7-1 0) (f-10-2 #x0) (f-12-4 #x1) jsr32-sem 2)
(dni jsri32.a "jsr.w dst32-16-24-Unprefixed-HI" (RL_1ADDR (machine 32))
("jsri.w ${dst32-16-24-Unprefixed-SI}")
(+ (f-0-4 #x9) (f-7-1 0) dst32-16-24-Unprefixed-SI (f-10-2 #x0) (f-12-4 #x1))
(jsr32-sem 6 dst32-16-24-Unprefixed-SI)
())
; jsr.w label16 (m32 #1)
(dni jsr32.w "jsr.w label" (RL_JUMP RELAXABLE (machine 32))
("jsr.w ${Lab-8-16}")
(+ (f-0-4 #xC) (f-4-4 #xF) Lab-8-16)
(jsr32-sem 3 Lab-8-16)
())
; jsr.a label16 (m32 #2)
(dni jsr32.a "jsr.a label" (RL_JUMP (machine 32))
("jsr.a ${Lab-8-24}")
(+ (f-0-4 #xC) (f-4-4 #xD) Lab-8-24)
(jsr32-sem 4 Lab-8-24)
())
; jsrs imm8 (m16 #1)
(dni jsrs16 "jsrs Imm-8-QI" ((machine 16))
("jsrs #${Imm-8-QI}")
(+ (f-0-4 #xE) (f-4-4 #xF) Imm-8-QI)
(jsr16-sem 2 Imm-8-QI)
())
; jsrs imm8 (m32 #1)
(dni jsrs "jsrs #Imm-8-QI" ((machine 32))
("jsrs #${Imm-8-QI}")
(+ (f-0-4 #xD) (f-4-4 #xD) Imm-8-QI)
(jsr32-sem 2 Imm-8-QI)
())
;-------------------------------------------------------------
; ldc - load control register
; stc - store control register
;-------------------------------------------------------------
(define-pmacro (ldc32-cr1-sem src dst)
(sequence ()
(case DFLT dst
((#x0) (set (reg h-dct0) src))
((#x1) (set (reg h-dct1) src))
((#x2) (sequence ((HI tflag))
(set tflag src)
(if (and tflag #x1) (set cbit 1))
(if (and tflag #x2) (set dbit 1))
(if (and tflag #x4) (set zbit 1))
(if (and tflag #x8) (set sbit 1))
(if (and tflag #x10) (set bbit 1))
(if (and tflag #x20) (set obit 1))
(if (and tflag #x40) (set ibit 1))
(if (and tflag #x80) (set ubit 1))))
((#x3) (set (reg h-svf) src))
((#x4) (set (reg h-drc0) src))
((#x5) (set (reg h-drc1) src))
((#x6) (set (reg h-dmd0) src))
((#x7) (set (reg h-dmd1) src))
)
)
)
(define-pmacro (ldc32-cr2-sem src dst)
(sequence ()
(case DFLT dst
((#x0) (set (reg h-intb) src))
((#x1) (set (reg h-sp) src))
((#x2) (set (reg h-sb) src))
((#x3) (set (reg h-fb) src))
((#x4) (set (reg h-svp) src))
((#x5) (set (reg h-vct) src))
((#x7) (set (reg h-isp) src))
)
)
)
(define-pmacro (ldc32-cr3-sem src dst)
(sequence ()
(case DFLT dst
((#x2) (set (reg h-dma0) src))
((#x3) (set (reg h-dma1) src))
((#x4) (set (reg h-dra0) src))
((#x5) (set (reg h-dra1) src))
((#x6) (set (reg h-dsa0) src))
((#x7) (set (reg h-dsa1) src))
)
)
)
(define-pmacro (ldc16-sem src dst)
(sequence ()
(case DFLT dst
((#x1) (set (reg h-intb) src))
((#x2) (set (reg h-intb) (or (reg h-intb) (sll src (const 16)))))
((#x3) (sequence ((HI tflag))
(set tflag src)
(if (and tflag #x1) (set cbit 1))
(if (and tflag #x2) (set dbit 1))
(if (and tflag #x4) (set zbit 1))
(if (and tflag #x8) (set sbit 1))
(if (and tflag #x10) (set bbit 1))
(if (and tflag #x20) (set obit 1))
(if (and tflag #x40) (set ibit 1))
(if (and tflag #x80) (set ubit 1))))
((#x4) (set (reg h-isp) src))
((#x5) (set (reg h-sp) src))
((#x6) (set (reg h-sb) src))
((#x7) (set (reg h-fb) src))
)
)
)
(define-pmacro (stc32-cr1-sem src dst)
(sequence ()
(case DFLT src
((#x0) (set dst (reg h-dct0)))
((#x1) (set dst (reg h-dct1)))
((#x2) (sequence ((HI tflag))
(set tflag 0)
(if (eq cbit 1) (set tflag (or tflag #x1)))
(if (eq dbit 1) (set tflag (or tflag #x2)))
(if (eq zbit 1) (set tflag (or tflag #x4)))
(if (eq sbit 1) (set tflag (or tflag #x8)))
(if (eq bbit 1) (set tflag (or tflag #x10)))
(if (eq obit 1) (set tflag (or tflag #x20)))
(if (eq ibit 1) (set tflag (or tflag #x40)))
(if (eq ubit 1) (set tflag (or tflag #x80)))
(set dst tflag)))
((#x3) (set dst (reg h-svf)))
((#x4) (set dst (reg h-drc0)))
((#x5) (set dst (reg h-drc1)))
((#x6) (set dst (reg h-dmd0)))
((#x7) (set dst (reg h-dmd1)))
)
)
)
(define-pmacro (stc32-cr2-sem src dst)
(sequence ()
(case DFLT src
((#x0) (set dst (reg h-intb)))
((#x1) (set dst (reg h-sp)))
((#x2) (set dst (reg h-sb)))
((#x3) (set dst (reg h-fb)))
((#x4) (set dst (reg h-svp)))
((#x5) (set dst (reg h-vct)))
((#x7) (set dst (reg h-isp)))
)
)
)
(define-pmacro (stc32-cr3-sem src dst)
(sequence ()
(case DFLT src
((#x2) (set dst (reg h-dma0)))
((#x3) (set dst (reg h-dma1)))
((#x4) (set dst (reg h-dra0)))
((#x5) (set dst (reg h-dra1)))
((#x6) (set dst (reg h-dsa0)))
((#x7) (set dst (reg h-dsa1)))
)
)
)
(define-pmacro (stc16-sem src dst)
(sequence ()
(case DFLT src
((#x1) (set dst (and (reg h-intb) (const #xffff))))
((#x2) (set dst (srl (reg h-intb) (const 16))))
((#x3) (sequence ((HI tflag))
(set tflag 0)
(if (eq cbit 1) (set tflag (or tflag #x1)))
(if (eq dbit 1) (set tflag (or tflag #x2)))
(if (eq zbit 1) (set tflag (or tflag #x4)))
(if (eq sbit 1) (set tflag (or tflag #x8)))
(if (eq bbit 1) (set tflag (or tflag #x10)))
(if (eq obit 1) (set tflag (or tflag #x20)))
(if (eq ibit 1) (set tflag (or tflag #x40)))
(if (eq ubit 1) (set tflag (or tflag #x80)))
(set dst tflag)))
((#x4) (set dst (reg h-isp)))
((#x5) (set dst (reg h-sp)))
((#x6) (set dst (reg h-sb)))
((#x7) (set dst (reg h-fb)))
)
)
)
(dni ldc16.imm16 "ldc #imm,dst" ((machine 16))
("ldc #${Imm-16-HI},${cr16}")
(+ (f-0-4 #xE) (f-4-4 #xB) (f-8-1 0) (f-12-4 0) cr16 Imm-16-HI)
(ldc16-sem Imm-16-HI cr16)
())
(dni ldc16.dst "ldc src,dest" ((machine 16))
("ldc ${dst16-16-HI},${cr16}")
(+ (f-0-4 7) (f-4-4 #xA) (f-8-1 1) cr16 dst16-16-HI)
(ldc16-sem dst16-16-HI cr16)
())
; ldc src,dest (m32c #4)
(dni ldc32.src-cr1 "ldc src,dst" ((machine 32))
("ldc ${dst32-24-Prefixed-HI},${cr1-Prefixed-32}")
(+ (f-0-4 0) (f-4-4 1) (f-8-4 #xD) dst32-24-Prefixed-HI (f-15-1 1) (f-18-2 0) (f-20-1 1) cr1-Prefixed-32)
(ldc32-cr1-sem dst32-24-Prefixed-HI cr1-Prefixed-32)
())
; ldc src,dest (m32c #5)
(dni ldc32.src-cr2 "ldc src,dest" ((machine 32))
("ldc ${dst32-16-Unprefixed-SI},${cr2-32}")
(+ (f-0-4 #xD) dst32-16-Unprefixed-SI (f-7-1 1) (f-10-2 0) (f-12-1 0) cr2-32)
(ldc32-cr2-sem dst32-16-Unprefixed-SI cr2-32)
())
; ldc src,dest (m32c #6)
(dni ldc32.src-cr3 "ldc src,dst" ((machine 32))
("ldc ${dst32-24-Prefixed-SI},${cr3-Prefixed-32}")
(+ (f-0-4 0) (f-4-4 1) (f-8-4 #xD) dst32-24-Prefixed-SI (f-15-1 1) (f-18-2 0) (f-20-1 0) cr3-Prefixed-32)
(ldc32-cr3-sem dst32-24-Prefixed-SI cr3-Prefixed-32)
())
; ldc src,dest (m32c #1)
(dni ldc32.imm16-cr1 "ldc #imm,dst" ((machine 32))
("ldc #${Imm-16-HI},${cr1-Unprefixed-32}")
(+ (f-0-4 #xD) (f-4-4 5) (f-8-4 #xA) (f-12-1 1) cr1-Unprefixed-32 Imm-16-HI)
(ldc32-cr1-sem Imm-16-HI cr1-Unprefixed-32)
())
; ldc src,dest (m32c #2)
(dni ldc32.imm16-cr2 "ldc #imm,dst" ((machine 32))
("ldc #${Dsp-16-u24},${cr2-32}")
(+ (f-0-4 #xD) (f-4-4 5) (f-8-4 2) (f-12-1 1) cr2-32 Dsp-16-u24)
(ldc32-cr2-sem Dsp-16-u24 cr2-32)
())
; ldc src,dest (m32c #3)
(dni ldc32.imm16-cr3 "ldc #imm,dst" ((machine 32))
("ldc #${Dsp-16-u24},${cr3-Unprefixed-32}")
(+ (f-0-4 #xD) (f-4-4 5) (f-8-4 6) (f-12-1 1) cr3-Unprefixed-32 Dsp-16-u24)
(ldc32-cr3-sem Dsp-16-u24 cr3-Unprefixed-32)
())
(dni stc16.src "stc src,dest" ((machine 16))
("stc ${cr16},${dst16-16-HI}")
(+ (f-0-4 7) (f-4-4 #xB) (f-8-1 1) cr16 dst16-16-HI)
(stc16-sem cr16 dst16-16-HI )
())
(dni stc16.pc "stc pc,dest" ((machine 16))
("stc pc,${dst16-16-HI}")
(+ (f-0-4 7) (f-4-4 #xC) (f-8-4 #xC) dst16-16-HI)
(sequence () (set dst16-16-HI (reg h-pc)))
())
(dni stc32.src-cr1 "stc src,dst" ((machine 32))
("stc ${cr1-Prefixed-32},${dst32-24-Prefixed-HI}")
(+ (f-0-4 0) (f-4-4 1) (f-8-4 #xD) dst32-24-Prefixed-HI (f-15-1 1) (f-18-2 1) (f-20-1 1) cr1-Prefixed-32)
(stc32-cr1-sem cr1-Prefixed-32 dst32-24-Prefixed-HI )
())
(dni stc32.src-cr2 "stc src,dest" ((machine 32))
("stc ${cr2-32},${dst32-16-Unprefixed-SI}")
(+ (f-0-4 #xD) dst32-16-Unprefixed-SI (f-7-1 1) (f-10-2 0) (f-12-1 2) cr2-32)
(stc32-cr2-sem cr2-32 dst32-16-Unprefixed-SI )
())
(dni stc32.src-cr3 "stc src,dst" ((machine 32))
("stc ${cr3-Prefixed-32},${dst32-24-Prefixed-SI}")
(+ (f-0-4 0) (f-4-4 1) (f-8-4 #xD) dst32-24-Prefixed-SI (f-15-1 1) (f-18-2 1) (f-20-1 0) cr3-Prefixed-32)
(stc32-cr3-sem cr3-Prefixed-32 dst32-24-Prefixed-SI )
())
;-------------------------------------------------------------
; ldctx - load context
; stctx - store context
;-------------------------------------------------------------
; ??? semantics
(dni ldctx16 "ldctx abs16,abs24" ((machine 16))
("ldctx ${Dsp-16-u16},${Dsp-32-u24}")
(+ (f-0-4 #x7) (f-4-4 #xC) (f-8-4 #xF) (f-12-4 #x0) Dsp-16-u16 Dsp-32-u24)
(nop)
())
(dni ldctx32 "ldctx abs16,abs24" ((machine 32))
("ldctx ${Dsp-16-u16},${Dsp-32-u24}")
(+ (f-0-4 #xB) (f-4-4 #x6) (f-8-4 #xC) (f-12-4 #x3) Dsp-16-u16 Dsp-32-u24)
(nop)
())
(dni stctx16 "stctx abs16,abs24" ((machine 16))
("stctx ${Dsp-16-u16},${Dsp-32-u24}")
(+ (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #xF) (f-12-4 #x0) Dsp-16-u16 Dsp-32-u24)
(nop)
())
(dni stctx32 "stctx abs16,abs24" ((machine 32))
("stctx ${Dsp-16-u16},${Dsp-32-u24}")
(+ (f-0-4 #xB) (f-4-4 #x6) (f-8-4 #xD) (f-12-4 #x3) Dsp-16-u16 Dsp-32-u24)
(nop)
())
;-------------------------------------------------------------
; lde - load from extra far data area (m16)
; ste - store to extra far data area (m16)
;-------------------------------------------------------------
(lde-dst QI .b 0)
(lde-dst HI .w 1)
(ste-dst QI .b 0)
(ste-dst HI .w 1)
;-------------------------------------------------------------
; ldipl - load interrupt permission level
;-------------------------------------------------------------
; ??? semantics
; ldintb <==> ldc #imm,intbh ; ldc #imm,intbl
(dni ldipl16.imm "ldipl #imm" ((machine 16))
("ldipl #${Imm-13-u3}")
(+ (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #xA) (f-12-1 0) Imm-13-u3)
(nop)
())
(dni ldipl32.imm "ldipl #imm" ((machine 32))
("ldipl #${Imm-13-u3}")
(+ (f-0-4 #xD) (f-4-4 5) (f-8-4 #xE) (f-12-1 1) Imm-13-u3)
(nop)
())
;-------------------------------------------------------------
; max - maximum value
;-------------------------------------------------------------
; TODO check semantics for min -1,0
(define-pmacro (max-sem mode src dst)
(sequence ()
(if (gt mode src dst)
(set mode dst src)))
)
; max.size:G #imm,dst
(binary-arith32-imm-dst-Prefixed QI QI .b 0 max X #x8 #x3 #xF max-sem)
(binary-arith32-imm-dst-Prefixed HI HI .w 1 max X #x8 #x3 #xF max-sem)
; max.BW:G src,dst
(binary-arith32-src-dst-Prefixed QI QI .b 0 max X #x1 #xD max-sem)
(binary-arith32-src-dst-Prefixed HI HI .w 1 max X #x1 #xD max-sem)
;-------------------------------------------------------------
; min - minimum value
;-------------------------------------------------------------
(define-pmacro (min-sem mode src dst)
(sequence ()
(if (lt mode src dst)
(set mode dst src)))
)
; min.size:G #imm,dst
(binary-arith32-imm-dst-Prefixed QI QI .b 0 min X #x8 #x2 #xF min-sem)
(binary-arith32-imm-dst-Prefixed HI HI .w 1 min X #x8 #x2 #xF min-sem)
; min.BW:G src,dst
(binary-arith32-src-dst-Prefixed QI QI .b 0 min X #x1 #xC min-sem)
(binary-arith32-src-dst-Prefixed HI HI .w 1 min X #x1 #xC min-sem)
;-------------------------------------------------------------
; mov - move
;-------------------------------------------------------------
(define-pmacro (mov-sem mode src1 dst)
(sequence ((mode result))
(set result src1)
(set-z-and-s result)
(set mode dst src1))
)
(define-pmacro (mov-dspsp-dst-sem mach mode src1 dst)
(set dst (mem-mach mach mode (add sp src1)))
)
(define-pmacro (mov-src-dspsp-sem mach mode src dst1)
(set (mem-mach mach mode (add sp dst1)) src)
)
(define-pmacro (mov16-imm-an-defn size mode imm regn op1 op2)
(dni (.sym mov16. size .S-imm- regn)
(.str "mov." size ":S " imm "," regn)
((machine 16))
(.str "mov." size "$S #${" imm "}," regn)
(+ op1 op2 imm)
(mov-sem mode imm (reg (.sym h- regn)))
())
)
; mov.size:G #imm,dst (m16 #1 m32 #1)
(binary-arith-imm-dst mov G (f-0-4 7) (f-4-3 2) (f-8-4 #xC) #x9 #x2 #xF mov-sem)
; mov.L:G #imm32,dst (m32 #2)
(binary-arith32-imm-dst-defn SI SI .l 0 mov G #xB #x3 #x1 mov-sem)
; mov.BW:S #imm,dst2 (m32 #4)
(binary-arith32-s-imm-dst QI .b 0 mov #x0 #x2 mov-sem)
(binary-arith32-s-imm-dst HI .w 1 mov #x0 #x2 mov-sem)
; mov.b:S #imm8,dst3 (m16 #3)
(binary-arith16-b-S-imm8-dst3 mov ".b" (f-0-4 #xC) (f-4-1 0) mov-sem)
; mov.b:S #imm8,aN (m16 #4)
(mov16-imm-an-defn b QI Imm-8-QI a0 (f-0-4 #xE) (f-4-4 2))
(mov16-imm-an-defn b QI Imm-8-QI a1 (f-0-4 #xE) (f-4-4 #xA))
(mov16-imm-an-defn w HI Imm-8-HI a0 (f-0-4 #xA) (f-4-4 2))
(mov16-imm-an-defn w HI Imm-8-HI a1 (f-0-4 #xA) (f-4-4 #xA))
; mov.WL:S #imm,A0/A1 (m32 #5)
(define-pmacro (mov32-wl-s-defn mode sz op1 imm regn op2)
(dni (.sym mov32- sz - regn)
(.str "mov." sz ":s" imm "," regn)
((machine 32))
(.str "mov." sz "$S #${" imm "}," regn)
(+ (f-0-4 op1) (f-4-4 op2) imm)
(mov-sem mode imm (reg (.sym h- regn)))
())
)
(mov32-wl-s-defn HI w #x9 Imm-8-HI a0 #xC)
(mov32-wl-s-defn HI w #x9 Imm-8-HI a1 #xD)
(mov32-wl-s-defn SI l #xB Dsp-8-s24 a0 #xC)
(mov32-wl-s-defn SI l #xB Dsp-8-s24 a1 #xD)
; mov.size:Q #imm4,dst (m16 #2 m32 #3)
(binary-arith16-imm4-dst-defn QI .b 0 0 mov (f-0-4 #xD) (f-4-3 4) mov-sem)
(binary-arith16-imm4-dst-defn HI .w 0 1 mov (f-0-4 #xD) (f-4-3 4) mov-sem)
(binary-arith32-imm4-dst-defn QI .b 1 0 mov #x7 #x2 mov-sem)
(binary-arith32-imm4-dst-defn HI .w 1 1 mov #x7 #x2 mov-sem)
; mov.BW:Z #0,dst (m16 #5 m32 #6)
(dni mov16.b-Z-imm8-dst3
"mov.b:Z #0,Dst16-3-S-8"
((machine 16))
"mov.b$Z #0,${Dst16-3-S-8}"
(+ (f-0-4 #xB) (f-4-1 #x0) Dst16-3-S-8)
(mov-sem QI (const 0) Dst16-3-S-8)
())
; (binary-arith16-b-Z-imm8-dst3 mov ".b" (f-0-4 #xB) (f-4-1 0) mov-sem)
(binary-arith32-z-imm-dst QI .b 0 mov #x0 #x1 mov-sem)
(binary-arith32-z-imm-dst HI .w 1 mov #x0 #x1 mov-sem)
; mov.BW:G src,dst (m16 #6 m32 #7)
(binary-arith-src-dst mov G (f-0-4 #x7) (f-4-3 1) #x1 #xB mov-sem)
; mov.B:S src2,a0/a1 (m16 #7)
(dni (.sym mov 16 .b.S-An)
(.str mov ".b:S src2,a[01]")
((machine 16))
(.str mov ".b$S ${src16-2-S},${Dst16AnQI-S}")
(+ (f-0-4 #x3) (f-4-1 0) Dst16AnQI-S src16-2-S)
(mov-sem QI src16-2-S Dst16AnQI-S)
())
(define-pmacro (mov16-b-s-an-defn op1 op2 op2c)
(dni (.sym mov16.b.S- op1 - op2)
(.str mov ".b:S " op1 "," op2)
((machine 16))
(.str mov ".b$S " op1 "," op2)
(+ (f-0-4 #x3) op2c)
(mov-sem QI (reg (.sym h- op1)) (reg (.sym h- op2)))
())
)
(mov16-b-s-an-defn r0l a1 (f-4-4 #x4))
(mov16-b-s-an-defn r0h a0 (f-4-4 #x0))
; mov.L:G src,dst (m32 #8)
(binary-arith32-src-dst-defn SI SI .l 1 mov G #x1 #x3 mov-sem)
; mov.B:S r0l/r0h,dst2 (m16 #8)
(dni (.sym mov 16 .b.S-Rn-An)
(.str mov ".b:S r0[lh],src2")
((machine 16))
(.str mov ".b$S ${Dst16RnQI-S},${src16-2-S}")
(+ (f-0-4 #x0) (f-4-1 0) Dst16RnQI-S src16-2-S)
(mov-sem QI src16-2-S Dst16RnQI-S)
())
; mov.B.S src2,r0l/r0h (m16 #9)
(binary-arith16-b-S-src2 mov (f-0-4 0) (f-4-1 1) mov-sem)
; mov.BW:S src2,r0l/r0 (m32 #9)
; mov.BW:S src2,r1l/r1 (m32 #10)
(define-pmacro (mov32-src-r sz szcode mode src dst opc1 opc2)
(begin
(dni (.sym mov32. sz - src - dst)
(.str "mov." sz "src," dst)
((machine 32))
(.str "mov." sz "$S ${" (.sym src - mode) "}," dst)
(+ (f-0-2 opc1) (.sym src - mode) (f-4-3 opc2) (f-7-1 szcode))
(mov-sem mode (.sym src - mode) (reg (.sym h- dst)))
())
)
)
(mov32-src-r b 0 QI dst32-2-S-16 r0l 0 4)
(mov32-src-r w 1 HI dst32-2-S-16 r0 0 4)
(mov32-src-r b 0 QI dst32-2-S-8 r0l 0 4)
(mov32-src-r w 1 HI dst32-2-S-8 r0 0 4)
(mov32-src-r b 0 QI dst32-2-S-basic r1l 1 7)
(mov32-src-r w 1 HI dst32-2-S-basic r1 1 7)
(mov32-src-r b 0 QI dst32-2-S-16 r1l 1 7)
(mov32-src-r w 1 HI dst32-2-S-16 r1 1 7)
(mov32-src-r b 0 QI dst32-2-S-8 r1l 1 7)
(mov32-src-r w 1 HI dst32-2-S-8 r1 1 7)
; mov.BW:S r0l/r0,dst2 (m32 #11)
(define-pmacro (mov32-r-dest sz szcode mode src dst opc1 opc2)
(begin
(dni (.sym mov32. sz - src - dst)
(.str "mov." sz "src," dst)
((machine 32))
(.str "mov." sz "$S " src ",${" (.sym dst - mode) "}")
(+ (f-0-2 opc1) (.sym dst - mode) (f-4-3 opc2) (f-7-1 szcode))
(mov-sem mode (reg (.sym h- src)) (.sym dst - mode))
())
)
)
(mov32-r-dest b 0 QI r0l dst32-2-S-16 0 0)
(mov32-r-dest w 1 HI r0 dst32-2-S-16 0 0)
(mov32-r-dest b 0 QI r0l dst32-2-S-8 0 0)
(mov32-r-dest w 1 HI r0 dst32-2-S-8 0 0)
; mov.L:S src,A0/A1 (m32 #12)
(define-pmacro (mov32-src-a src dst dstcode opc1 opc2)
(begin
(dni (.sym mov32. sz - src - dst)
(.str "mov." sz "src," dst)
((machine 32))
(.str "mov.l" "$S ${" (.sym src - SI) "}," dst)
(+ (f-0-2 opc1) (.sym src - SI) (f-4-3 opc2) (f-7-1 dstcode))
(mov-sem SI (.sym src - SI) (reg (.sym h- dst)))
())
)
)
(mov32-src-a dst32-2-S-16 a0 0 1 4)
(mov32-src-a dst32-2-S-16 a1 1 1 4)
(mov32-src-a dst32-2-S-8 a0 0 1 4)
(mov32-src-a dst32-2-S-8 a1 1 1 4)
; mov.BW:G dsp8[sp],dst (m16 #10 m32 #13)
; mov.BW:G src,dsp8[sp] (m16 #11 m32 #14)
(mov-dspsp-dst mov (f-0-4 #x7) (f-4-3 2) (f-8-4 #xB) #xB #x0 #xF mov-dspsp-dst-sem)
(mov-src-dspsp mov (f-0-4 #x7) (f-4-3 2) (f-8-4 #x3) #xA #x0 #xF mov-src-dspsp-sem)
;-------------------------------------------------------------
; mova - move effective address
;-------------------------------------------------------------
(define-pmacro (mov16a-defn dst dstop dstcode)
(dni (.sym mova16. src - dst)
(.str "mova src," dst)
((machine 16))
(.str "mova ${dst16-16-Mova-HI}," dst)
(+ (f-0-4 #xE) (f-4-4 #xB) dst16-16-Mova-HI (f-8-4 dstcode))
(sequence () (set HI (reg dstop) dst16-16-Mova-HI))
())
)
(mov16a-defn r0 h-r0 0)
(mov16a-defn r1 h-r1 1)
(mov16a-defn r2 h-r2 2)
(mov16a-defn r3 h-r3 3)
(mov16a-defn a0 h-a0 4)
(mov16a-defn a1 h-a1 5)
(define-pmacro (mov32a-defn dst dstop dstcode)
(dni (.sym mova32. src - dst)
(.str "mova src," dst)
((machine 32))
(.str "mova ${dst32-16-Unprefixed-Mova-SI}," dst)
(+ (f-0-4 #xD) dst32-16-Unprefixed-Mova-SI (f-7-1 1) (f-10-2 1) (f-12-1 1) (f-13-3 dstcode))
(sequence () (set SI (reg dstop) dst32-16-Unprefixed-Mova-SI))
())
)
(mov32a-defn r2r0 h-r2r0 0)
(mov32a-defn r3r1 h-r3r1 1)
(mov32a-defn a0 h-a0 2)
(mov32a-defn a1 h-a1 3)
;-------------------------------------------------------------
; movDir - move nibble
;-------------------------------------------------------------
(define-pmacro (movdir-sem nib src dst)
(sequence ((SI tmp))
(case DFLT nib
((0) (set dst (or (and dst #xf0) (and src #xf))))
((1) (set dst (or (and dst #x0f) (sll (and src #xf) 4))))
((2) (set dst (or (and dst #xf0) (srl (and src #xf0) 4))))
((3) (set dst (or (and dst #x0f) (and src #xf0))))
)
)
)
; movDir src,dst
(define-pmacro (mov16dir-1-defn nib dircode dir)
(dni (.sym mov nib 16 ".r0l-dst")
(.str "mov" nib " r0l,dst")
((machine 16))
(.str "mov" nib " r0l,${dst16-16-QI}")
(+ (f-0-4 7) (f-4-4 #xC) (f-8-4 dir) dst16-16-QI)
(movdir-sem dircode (reg h-r0l) dst16-16-QI)
())
)
(mov16dir-1-defn ll 0 8)
(mov16dir-1-defn lh 1 #xA)
(mov16dir-1-defn hl 2 9)
(mov16dir-1-defn hh 3 #xB)
(define-pmacro (mov16dir-2-defn nib dircode dir)
(dni (.sym mov nib 16 ".src-r0l")
(.str "mov" nib " src,r0l")
((machine 16))
(.str "mov" nib " ${dst16-16-QI},r0l")
(+ (f-0-4 7) (f-4-4 #xC) (f-8-4 dir) dst16-16-QI)
(movdir-sem dircode dst16-16-QI (reg h-r0l))
())
)
(mov16dir-2-defn ll 0 0)
(mov16dir-2-defn lh 1 2)
(mov16dir-2-defn hl 2 1)
(mov16dir-2-defn hh 3 3)
(define-pmacro (mov32dir-1-defn nib o1o0)
(dni (.sym mov nib 32 ".r0l-dst")
(.str "mov" nib " r0l,dst")
((machine 32))
(.str "mov" nib " r0l,${dst32-24-Prefixed-QI}")
(+ (f-0-4 #x0) (f-4-4 #x1) (f-8-4 #xB) dst32-24-Prefixed-QI (f-15-1 0) (f-18-2 o1o0) (f-20-4 #xE))
(movdir-sem o1o0 (reg h-r0l) dst32-24-Prefixed-QI)
())
)
(mov32dir-1-defn ll 0)
(mov32dir-1-defn lh 1)
(mov32dir-1-defn hl 2)
(mov32dir-1-defn hh 3)
(define-pmacro (mov32dir-2-defn nib o1o0)
(dni (.sym mov nib 32 ".src-r0l")
(.str "mov" nib " src,r0l")
((machine 32))
(.str "mov" nib " ${dst32-24-Prefixed-QI},r0l")
(+ (f-0-4 #x0) (f-4-4 #x1) (f-8-4 #xA) dst32-24-Prefixed-QI (f-15-1 0) (f-18-2 o1o0) (f-20-4 #xE))
(movdir-sem o1o0 dst32-24-Prefixed-QI (reg h-r0l))
())
)
(mov32dir-2-defn ll 0)
(mov32dir-2-defn lh 1)
(mov32dir-2-defn hl 2)
(mov32dir-2-defn hh 3)
;-------------------------------------------------------------
; movx - move extend sign (m32)
;-------------------------------------------------------------
(define-pmacro (movx-sem mode src dst)
(sequence ((SI source) (SI result))
(set SI result src)
(set-z-and-s result)
(set dst result))
)
; movx #imm,dst
(binary-arith32-imm-dst-defn QI SI "" 0 movx X #xB #x1 #x1 movx-sem)
;-------------------------------------------------------------
; mul - multiply
;-------------------------------------------------------------
(define-pmacro (mul-sem mode src1 dst)
(sequence ((mode result))
(set obit (add-oflag mode src1 dst 0))
(set result (mul mode src1 dst))
(set dst result))
)
; mul.BW #imm,dst
(binary-arith-imm-dst mul G (f-0-4 7) (f-4-3 6) (f-8-4 5) #x8 #x1 #xF mul-sem)
; mul.BW src,dst
(binary-arith-src-dst mul G (f-0-4 #x7) (f-4-3 4) #x1 #xC mul-sem)
(dni mul_l "mul.l src,r2r0" ((machine 32))
("mul.l ${dst32-24-Prefixed-SI},r2r0")
(+ (f-0-4 #x0) (f-4-4 #x1) (f-8-4 #x8) (f-15-1 #x1) (f-18-2 #x1) (f-20-4 #xf)
dst32-24-Prefixed-SI)
() ())
(dni mulu_l "mulu.l src,r2r0" ((machine 32))
("mulu.l ${dst32-24-Prefixed-SI},r2r0")
(+ (f-0-4 #x0) (f-4-4 #x1) (f-8-4 #x8) (f-15-1 #x1) (f-18-2 #x0) (f-20-4 #xf)
dst32-24-Prefixed-SI)
() ())
;-------------------------------------------------------------
; mulex - multiple extend sign (m32)
;-------------------------------------------------------------
; mulex src,dst
; (dni mulex-absolute-indirect "mulex [src]" ((machine 32))
; ("mulex ${dst32-24-absolute-indirect-HI}")
; (+ (f-0-4 0) (f-4-4 9) (f-8-4 #xC) dst32-24-absolute-indirect-HI (f-15-1 1) (f-18-2 3) (f-20-4 #xE))
; (set R1R2R0 (mul DI (ext DI R2R0) (ext DI dst32-24-absolute-indirect-HI)))
; ())
(dni mulex "mulex src" ((machine 32))
("mulex ${dst32-16-Unprefixed-Mulex-HI}")
(+ (f-0-4 #xC) dst32-16-Unprefixed-Mulex-HI (f-7-1 1) (f-10-2 3) (f-12-4 #xE))
(set R1R2R0 (mul DI (ext DI R2R0) (ext DI dst32-16-Unprefixed-Mulex-HI)))
())
; (dni mulex-indirect "mulex [src]" ((machine 32))
; ("mulex ${dst32-24-indirect-HI}")
; (+ (f-0-4 0) (f-4-4 9) (f-8-4 #xC) dst32-24-indirect-HI (f-15-1 1) (f-18-2 3) (f-20-4 #xE))
; (set R1R2R0 (mul DI (ext DI R2R0) (ext DI dst32-24-indirect-HI)))
; ())
;-------------------------------------------------------------
; mulu - multiply unsigned
;-------------------------------------------------------------
(define-pmacro (mulu-sem mode src1 dst)
(sequence ((mode result))
(set obit (add-oflag mode src1 dst 0))
(set result (mul mode src1 dst))
(set dst result))
)
; mulu.BW #imm,dst
(binary-arith-imm-dst mulu G (f-0-4 7) (f-4-3 6) (f-8-4 4) #x8 #x0 #xF mulu-sem)
; mulu.BW src,dst
(binary-arith-src-dst mulu G (f-0-4 #x7) (f-4-3 0) #x1 #x4 mulu-sem)
;-------------------------------------------------------------
; neg - twos complement
;-------------------------------------------------------------
(define-pmacro (neg-sem mode dst)
(sequence ((mode result))
(set result (neg mode dst))
(set-z-and-s result)
(set dst result))
)
; neg.BW:G
(unary-insn neg (f-0-4 7) (f-4-3 2) (f-8-4 #x5) #xA #x2 #xF neg-sem)
;-------------------------------------------------------------
; not - twos complement
;-------------------------------------------------------------
(define-pmacro (not-sem mode dst)
(sequence ((mode result))
(set result (not mode dst))
(set-z-and-s result)
(set dst result))
)
; not.BW:G
(unary-insn-g not (f-0-4 7) (f-4-3 2) (f-8-4 #x7) #xA #x1 #xE not-sem)
(dni not16.b.s
"not.b:s Dst16-3-S-8"
((machine 16))
"not.b:s ${Dst16-3-S-8}"
(+ (f-0-4 #xb) (f-4-1 #x1) Dst16-3-S-8)
(not-sem QI Dst16-3-S-8)
())
;-------------------------------------------------------------
; nop
;-------------------------------------------------------------
(dni nop16
"nop"
((machine 16))
"nop"
(+ (f-0-4 #x0) (f-4-4 #x4))
(nop)
())
(dni nop32
"nop"
((machine 32))
"nop"
(+ (f-0-4 #xD) (f-4-4 #xE))
(nop)
())
;-------------------------------------------------------------
; or - logical or
;-------------------------------------------------------------
(define-pmacro (or-sem mode src1 dst)
(sequence ((mode result))
(set result (or mode src1 dst))
(set-z-and-s result)
(set dst result))
)
; or.BW #imm,dst (m16 #1 m32 #1)
(binary-arith-imm-dst or G (f-0-4 7) (f-4-3 3) (f-8-4 3) #x8 #x2 #xF or-sem)
; or.b:S #imm8,dst3 (m16 #2 m32 #2)
(binary-arith16-b-S-imm8-dst3 or ".b" (f-0-4 9) (f-4-1 1) or-sem)
(binary-arith32-s-imm-dst QI .b 0 or #x1 #x2 or-sem)
(binary-arith32-s-imm-dst HI .w 1 or #x1 #x2 or-sem)
; or.BW src,dst (m16 #3 m32 #3)
(binary-arith-src-dst or G (f-0-4 #x9) (f-4-3 4) #x1 #x5 or-sem)
; or.b:S src,r0[lh] (m16)
(binary-arith16-b-S-src2 or (f-0-4 1) (f-4-1 1) or-sem)
;-------------------------------------------------------------
; pop - restore register/memory
;-------------------------------------------------------------
; TODO future: split this into .b and .w semantics
(define-pmacro (pop-sem-mach mach mode dst)
(sequence ((mode b_or_w) (SI length))
(set b_or_w -1)
(set b_or_w (srl b_or_w #x8))
(if (eq b_or_w #x0)
(set length 1) ; .b
(set length 2)) ; .w
(case DFLT length
((1) (set dst (mem-mach mach QI (reg h-sp))))
((2) (set dst (mem-mach mach HI (reg h-sp)))))
(set (reg h-sp) (add (reg h-sp) length))
)
)
(define-pmacro (pop-sem16 mode dest) (pop-sem-mach 16 mode dest))
(define-pmacro (pop-sem32 mode dest) (pop-sem-mach 32 mode dest))
; pop.BW:G (m16 #1)
(unary-insn-mach-g 16 pop (f-0-4 7) (f-4-3 2) (f-8-4 #xD) pop-sem16 $G)
; pop.BW:G (m32 #1)
(unary-insn-mach 32 pop #xB #x2 #xF pop-sem32)
; pop.b:S r0l/r0h
(dni pop16.b-s-rn "pop.b:S r0[lh]" ((machine 16))
"pop.b$S ${Rn16-push-S-anyof}"
(+ (f-0-4 #x9) Rn16-push-S-anyof (f-5-3 #x2))
(pop-sem16 QI Rn16-push-S-anyof)
())
; pop.w:S a0/a1
(dni pop16.b-s-an "pop.w:S a[01]" ((machine 16))
"pop.w$S ${An16-push-S-anyof}"
(+ (f-0-4 #xD) An16-push-S-anyof (f-5-3 #x2))
(pop-sem16 HI An16-push-S-anyof)
())
;-------------------------------------------------------------
; popc - pop control register
; pushc - push control register
;-------------------------------------------------------------
(define-pmacro (popc32-cr1-sem mode dst)
(sequence ()
(case DFLT dst
((#x0) (set (reg h-dct0) (mem32 mode (reg h-sp))))
((#x1) (set (reg h-dct1) (mem32 mode (reg h-sp))))
((#x2) (sequence ((HI tflag))
(set tflag (mem32 mode (reg h-sp)))
(if (and tflag #x1) (set cbit 1))
(if (and tflag #x2) (set dbit 1))
(if (and tflag #x4) (set zbit 1))
(if (and tflag #x8) (set sbit 1))
(if (and tflag #x10) (set bbit 1))
(if (and tflag #x20) (set obit 1))
(if (and tflag #x40) (set ibit 1))
(if (and tflag #x80) (set ubit 1))))
((#x3) (set (reg h-svf) (mem32 mode (reg h-sp))))
((#x4) (set (reg h-drc0) (mem32 mode (reg h-sp))))
((#x5) (set (reg h-drc1) (mem32 mode (reg h-sp))))
((#x6) (set (reg h-dmd0) (mem32 mode (reg h-sp))))
((#x7) (set (reg h-dmd1) (mem32 mode (reg h-sp))))
)
(set (reg h-sp) (add (reg h-sp) 2))
)
)
(define-pmacro (popc32-cr2-sem mode dst)
(sequence ()
(case DFLT dst
((#x0) (set (reg h-intb) (mem32 mode (reg h-sp))))
((#x1) (set (reg h-sp) (mem32 mode (reg h-sp))))
((#x2) (set (reg h-sb) (mem32 mode (reg h-sp))))
((#x3) (set (reg h-fb) (mem32 mode (reg h-sp))))
((#x7) (set (reg h-isp) (mem32 mode (reg h-sp))))
)
(set (reg h-sp) (add (reg h-sp) 4))
)
)
(define-pmacro (popc16-sem mode dst)
(sequence ()
(case DFLT dst
((#x1) (set (reg h-intb) (or (and (reg h-intb) #x0000)
(mem16 mode (reg h-sp)))))
((#x2) (set (reg h-intb) (or (and (reg h-intb) #xffff0000)
(mem16 mode (reg h-sp)))))
((#x3) (sequence ((HI tflag))
(set tflag (mem16 mode (reg h-sp)))
(if (and tflag #x1) (set cbit 1))
(if (and tflag #x2) (set dbit 1))
(if (and tflag #x4) (set zbit 1))
(if (and tflag #x8) (set sbit 1))
(if (and tflag #x10) (set bbit 1))
(if (and tflag #x20) (set obit 1))
(if (and tflag #x40) (set ibit 1))
(if (and tflag #x80) (set ubit 1))))
((#x4) (set (reg h-isp) (mem16 mode (reg h-sp))))
((#x5) (set (reg h-sp) (mem16 mode (reg h-sp))))
((#x6) (set (reg h-sb) (mem16 mode (reg h-sp))))
((#x7) (set (reg h-fb) (mem16 mode (reg h-sp))))
)
(set (reg h-sp) (add (reg h-sp) 2))
)
)
; popc dest (m16c #1)
(dni popc16.imm16 "popc dst" ((machine 16))
("popc ${cr16}")
(+ (f-0-4 #xE) (f-4-4 #xB) (f-8-1 0) (f-12-4 3) cr16)
(popc16-sem HI cr16)
())
; popc dest (m32c #1)
(dni popc32.imm16-cr1 "popc dst" ((machine 32))
("popc ${cr1-Unprefixed-32}")
(+ (f-0-4 #xD) (f-4-4 3) (f-8-4 #xA) (f-12-1 1) cr1-Unprefixed-32)
(popc32-cr1-sem HI cr1-Unprefixed-32)
())
; popc dest (m32c #2)
(dni popc32.imm16-cr2 "popc dst" ((machine 32))
("popc ${cr2-32}")
(+ (f-0-4 #xD) (f-4-4 3) (f-8-4 2) (f-12-1 1) cr2-32)
(popc32-cr2-sem SI cr2-32)
())
(define-pmacro (pushc32-cr1-sem mode dst)
(sequence ()
(set (reg h-sp) (sub (reg h-sp) 2))
(case DFLT dst
((#x0) (set (mem32 mode (reg h-sp)) (reg h-dct0)))
((#x1) (set (mem32 mode (reg h-sp)) (reg h-dct1)))
((#x2) (sequence ((HI tflag))
(set tflag 0)
(if (eq cbit 1) (set tflag (or tflag #x1)))
(if (eq dbit 1) (set tflag (or tflag #x2)))
(if (eq zbit 1) (set tflag (or tflag #x4)))
(if (eq sbit 1) (set tflag (or tflag #x8)))
(if (eq bbit 1) (set tflag (or tflag #x10)))
(if (eq obit 1) (set tflag (or tflag #x20)))
(if (eq ibit 1) (set tflag (or tflag #x40)))
(if (eq ubit 1) (set tflag (or tflag #x80)))
(set (mem32 mode (reg h-sp)) tflag)))
((#x3) (set (mem32 mode (reg h-sp)) (reg h-svf)))
((#x4) (set (mem32 mode (reg h-sp)) (reg h-drc0)))
((#x5) (set (mem32 mode (reg h-sp)) (reg h-drc1)))
((#x6) (set (mem32 mode (reg h-sp)) (reg h-dmd0)))
((#x7) (set (mem32 mode (reg h-sp)) (reg h-dmd1)))
)
)
)
(define-pmacro (pushc32-cr2-sem mode dst)
(sequence ()
(set (reg h-sp) (sub (reg h-sp) 4))
(case DFLT dst
((#x0) (set (mem32 mode (reg h-sp)) (reg h-intb)))
((#x1) (set (mem32 mode (reg h-sp)) (reg h-sp)))
((#x2) (set (mem32 mode (reg h-sp)) (reg h-sb)))
((#x3) (set (mem32 mode (reg h-sp)) (reg h-fb)))
((#x7) (set (mem32 mode (reg h-sp)) (reg h-isp)))
)
)
)
(define-pmacro (pushc16-sem mode dst)
(sequence ()
(set (reg h-sp) (sub (reg h-sp) 2))
(case DFLT dst
((#x1) (set (mem16 mode (reg h-sp)) (and (reg h-intb) #xffff)))
((#x2) (set (mem16 mode (reg h-sp)) (and (reg h-intb) #xffff0000)))
((#x3) (sequence ((HI tflag))
(if (eq cbit 1) (set tflag (or tflag #x1)))
(if (eq dbit 1) (set tflag (or tflag #x2)))
(if (eq zbit 1) (set tflag (or tflag #x4)))
(if (eq sbit 1) (set tflag (or tflag #x8)))
(if (eq bbit 1) (set tflag (or tflag #x10)))
(if (eq obit 1) (set tflag (or tflag #x20)))
(if (eq ibit 1) (set tflag (or tflag #x40)))
(if (eq ubit 1) (set tflag (or tflag #x80)))
(set (mem16 mode (reg h-sp)) tflag)))
((#x4) (set (mem16 mode (reg h-sp)) (reg h-isp)))
((#x5) (set (mem16 mode (reg h-sp)) (reg h-sp)))
((#x6) (set (mem16 mode (reg h-sp)) (reg h-sb)))
((#x7) (set (mem16 mode (reg h-sp)) (reg h-fb)))
)
)
)
; pushc src (m16c)
(dni pushc16.imm16 "pushc dst" ((machine 16))
("pushc ${cr16}")
(+ (f-0-4 #xE) (f-4-4 #xB) (f-8-1 0) (f-12-4 2) cr16)
(pushc16-sem HI cr16)
())
; pushc src (m32c #1)
(dni pushc32.imm16-cr1 "pushc dst" ((machine 32))
("pushc ${cr1-Unprefixed-32}")
(+ (f-0-4 #xD) (f-4-4 1) (f-8-4 #xA) (f-12-1 1) cr1-Unprefixed-32)
(pushc32-cr1-sem HI cr1-Unprefixed-32)
())
; pushc src (m32c #2)
(dni pushc32.imm16-cr2 "pushc dst" ((machine 32))
("pushc ${cr2-32}")
(+ (f-0-4 #xD) (f-4-4 1) (f-8-4 2) (f-12-1 1) cr2-32)
(pushc32-cr2-sem SI cr2-32)
())
;-------------------------------------------------------------
; popm - pop multiple
; pushm - push multiple
;-------------------------------------------------------------
(define-pmacro (popm-sem machine dst)
(sequence ((SI addrlen))
(if (eq machine 16)
(set addrlen 2)
(set addrlen 4))
(if (and dst 1)
(sequence () (set R0 (mem-mach machine HI (reg h-sp)))
(set (reg h-sp) (add (reg h-sp) 2))))
(if (and dst 2)
(sequence () (set R1 (mem-mach machine HI (reg h-sp)))
(set (reg h-sp) (add (reg h-sp) 2))))
(if (and dst 4)
(sequence () (set R2 (mem-mach machine HI (reg h-sp)))
(set (reg h-sp) (add (reg h-sp) 2))))
(if (and dst 8)
(sequence () (set R3 (mem-mach machine HI (reg h-sp)))
(set (reg h-sp) (add (reg h-sp) 2))))
(if (and dst 16)
(sequence () (set A0 (mem-mach machine HI (reg h-sp)))
(set (reg h-sp) (add (reg h-sp) addrlen))))
(if (and dst 32)
(sequence () (set A1 (mem-mach machine HI (reg h-sp)))
(set (reg h-sp) (add (reg h-sp) addrlen))))
(if (and dst 64)
(sequence () (set (reg h-sb) (mem-mach machine HI (reg h-sp)))
(set (reg h-sp) (add (reg h-sp) addrlen))))
(if (eq dst 128)
(sequence () (set (reg h-fb) (mem-mach machine HI (reg h-sp)))
(set (reg h-sp) (add (reg h-sp) addrlen))))
)
)
(define-pmacro (pushm-sem machine dst)
(sequence ((SI count) (SI addrlen))
(if (eq machine 16)
(set addrlen 2)
(set addrlen 4))
(if (eq dst 1)
(sequence () (set (reg h-sp) (sub (reg h-sp) addrlen))
(set (mem-mach machine HI (reg h-sp)) (reg h-fb))))
(if (and dst 2)
(sequence () (set (reg h-sp) (sub (reg h-sp) addrlen))
(set (mem-mach machine HI (reg h-sp)) (reg h-sb))))
(if (and dst 4)
(sequence () (set (reg h-sp) (sub (reg h-sp) addrlen))
(set (mem-mach machine HI (reg h-sp)) A1)))
(if (and dst 8)
(sequence () (set (reg h-sp) (sub (reg h-sp) addrlen))
(set (mem-mach machine HI (reg h-sp)) A0)))
(if (and dst 16)
(sequence () (set (reg h-sp) (sub (reg h-sp) 2))
(set (mem-mach machine HI (reg h-sp)) R3)))
(if (and dst 32)
(sequence () (set (reg h-sp) (sub (reg h-sp) 2))
(set (mem-mach machine HI (reg h-sp)) R2)))
(if (and dst 64)
(sequence () (set (reg h-sp) (sub (reg h-sp) 2))
(set (mem-mach machine HI (reg h-sp)) R1)))
(if (and dst 128)
(sequence () (set (reg h-sp) (sub (reg h-sp) 2))
(set (mem-mach machine HI (reg h-sp)) R0)))
)
)
(dni popm16 "popm regs" ((machine 16))
("popm ${Regsetpop}")
(+ (f-0-4 #xE) (f-4-4 #xD) Regsetpop)
(popm-sem 16 Regsetpop)
())
(dni pushm16 "pushm regs" ((machine 16))
("pushm ${Regsetpush}")
(+ (f-0-4 #xE) (f-4-4 #xC) Regsetpush)
(pushm-sem 16 Regsetpush)
())
(dni popm "popm regs" ((machine 32))
("popm ${Regsetpop}")
(+ (f-0-4 #x8) (f-4-4 #xE) Regsetpop)
(popm-sem 32 Regsetpop)
())
(dni pushm "pushm regs" ((machine 32))
("pushm ${Regsetpush}")
(+ (f-0-4 #x8) (f-4-4 #xF) Regsetpush)
(pushm-sem 32 Regsetpush)
())
;-------------------------------------------------------------
; push - Save register/memory/immediate data
;-------------------------------------------------------------
; TODO future: split this into .b and .w semantics
(define-pmacro (push-sem-mach mach mode dst)
(sequence ((mode b_or_w) (SI length))
(set b_or_w -1)
(set b_or_w (srl b_or_w #x8))
(if (eq b_or_w #x0)
(set length 1) ; .b
(if (eq b_or_w #xff)
(set length 2) ; .w
(set length 4))) ; .l
(set (reg h-sp) (sub (reg h-sp) length))
(case DFLT length
((1) (set (mem-mach mach QI (reg h-sp)) dst))
((2) (set (mem-mach mach HI (reg h-sp)) dst))
((4) (set (mem-mach mach SI (reg h-sp)) dst)))
)
)
(define-pmacro (push-sem16 mode dst) (push-sem-mach 16 mode dst))
(define-pmacro (push-sem32 mode dst) (push-sem-mach 32 mode dst))
; push.BW:G imm (m16 #1 m32 #1)
(dni push16.b.G-imm "push.b:G #Imm-16-QI" ((machine 16))
("push.b$G #${Imm-16-QI}")
(+ (f-0-4 7) (f-4-4 #xC) (f-8-4 #xE) (f-12-4 2) Imm-16-QI)
(push-sem16 QI Imm-16-QI)
())
(dni push16.w.G-imm "push.w:G #Imm-16-HI" ((machine 16))
("push.w$G #${Imm-16-HI}")
(+ (f-0-4 7) (f-4-4 #xD) (f-8-4 #xE) (f-12-4 2) Imm-16-HI)
(push-sem16 HI Imm-16-HI)
())
(dni push32.b.imm "push.b #Imm-8-QI" ((machine 32))
("push.b #${Imm-8-QI}")
(+ (f-0-4 #xA) (f-4-4 #xE) Imm-8-QI)
(push-sem32 QI Imm-8-QI)
())
(dni push32.w.imm "push.w #Imm-8-HI" ((machine 32))
("push.w #${Imm-8-HI}")
(+ (f-0-4 #xA) (f-4-4 #xF) Imm-8-HI)
(push-sem32 HI Imm-8-HI)
())
; push.BW:G src (m16 #2)
(unary-insn-mach-g 16 push (f-0-4 7) (f-4-3 2) (f-8-4 #x4) push-sem16 $G)
; push.BW:G src (m32 #2)
(unary-insn-mach 32 push #xC #x0 #xE push-sem32)
; push.b:S r0l/r0h (m16 #3)
(dni push16.b-s-rn "push.b:S r0[lh]" ((machine 16))
"push.b$S ${Rn16-push-S-anyof}"
(+ (f-0-4 #x8) Rn16-push-S-anyof (f-5-3 #x2))
(push-sem16 QI Rn16-push-S-anyof)
())
; push.w:S a0/a1 (m16 #4)
(dni push16.b-s-an "push.w:S a[01]" ((machine 16))
"push.w$S ${An16-push-S-anyof}"
(+ (f-0-4 #xC) An16-push-S-anyof (f-5-3 #x2))
(push-sem16 HI An16-push-S-anyof)
())
; push.l imm32 (m32 #3)
(dni push32.l.imm "push.l #Imm-16-SI" ((machine 32))
("push.l #${Imm-16-SI}")
(+ (f-0-4 #xB) (f-4-4 6) (f-8-4 5) (f-12-4 3) Imm-16-SI)
(push-sem32 SI Imm-16-SI)
())
; push.l src (m32 #4)
(unary-insn-defn 32 16-Unprefixed SI .l push (+ (f-0-4 #xA) (f-7-1 0) dst32-16-Unprefixed-SI (f-10-2 0) (f-12-4 1)) push-sem32)
;-------------------------------------------------------------
; pusha - push effective address
;------------------------------------------------------------
(define-pmacro (push16a-sem mode dst)
(sequence ()
(set (reg h-sp) (sub (reg h-sp) 2))
(set (mem16 HI (reg h-sp)) dst))
)
(define-pmacro (push32a-sem mode dst)
(sequence ()
(set (reg h-sp) (sub (reg h-sp) 4))
(set (mem32 SI (reg h-sp)) dst))
)
(unary-insn-defn 16 16-Mova HI "" pusha (+ (f-0-4 7) (f-4-4 #xD) (f-8-4 9) dst16-16-Mova-HI) push16a-sem)
(unary-insn-defn 32 16-Unprefixed-Mova SI "" pusha (+ (f-0-4 #xB) (f-7-1 0) dst32-16-Unprefixed-Mova-SI (f-10-2 0) (f-12-4 1)) push32a-sem)
;-------------------------------------------------------------
; reit - return from interrupt
;-------------------------------------------------------------
; ??? semantics
(dni reit16 "REIT" ((machine 16))
("reit")
(+ (f-0-4 #xF) (f-4-4 #xB))
(nop)
())
(dni reit32 "REIT" ((machine 32))
("reit")
(+ (f-0-4 9) (f-4-4 #xE))
(nop)
())
;-------------------------------------------------------------
; rmpa - repeat multiple and addition
;-------------------------------------------------------------
; TODO semantics
(dni rmpa16.b "rmpa.size" ((machine 16))
("rmpa.b")
(+ (f-0-4 7) (f-4-4 #xC) (f-8-4 #xF) (f-12-4 1))
(nop)
())
(dni rmpa16.w "rmpa.size" ((machine 16))
("rmpa.w")
(+ (f-0-4 7) (f-4-4 #xD) (f-8-4 #xF) (f-12-4 1))
(nop)
())
(dni rmpa32.b "rmpa.size" ((machine 32))
("rmpa.b")
(+ (f-0-4 #xB) (f-4-4 8) (f-8-4 4) (f-12-4 3))
(nop)
())
(dni rmpa32.w "rmpa.size" ((machine 32))
("rmpa.w")
(+ (f-0-4 #xB) (f-4-4 8) (f-8-4 5) (f-12-4 3))
(nop)
())
;-------------------------------------------------------------
; rolc - rotate left with carry
;-------------------------------------------------------------
; TODO check semantics
; TODO future: split this into .b and .w semantics
(define-pmacro (rolc-sem mode dst)
(sequence ((mode result) (SI ocbit) (mode b_or_w) (USI mask))
(set b_or_w -1)
(set b_or_w (srl b_or_w #x8))
(if (eq b_or_w #x0)
(set mask #x8000) ; .b
(set mask #x80000000)) ; .w
(set ocbit cbit)
(set cbit (and dst mask))
(set result (sll mode dst 1))
(set result (or result ocbit))
(set-z-and-s result)
(set dst result))
)
; rolc.BW src,dst
(unary-insn rolc (f-0-4 7) (f-4-3 3) (f-8-4 #xA) #xB #x2 #xE rolc-sem)
;-------------------------------------------------------------
; rorc - rotate right with carry
;-------------------------------------------------------------
; TODO check semantics
; TODO future: split this into .b and .w semantics
(define-pmacro (rorc-sem mode dst)
(sequence ((mode result) (SI ocbit) (mode b_or_w) (USI mask) (SI shamt))
(set b_or_w -1)
(set b_or_w (srl b_or_w #x8))
(if (eq b_or_w #x0)
(sequence () (set mask #x7fff) (set shamt 15)) ; .b
(sequence () (set mask #x7fffffff) (set shamt 31))) ; .w
(set ocbit cbit)
(set cbit (and dst #x1))
(set result (srl mode dst (const 1)))
(set result (or (and result mask) (sll ocbit shamt)))
(set-z-and-s result)
(set dst result))
)
; rorc.BW src,dst
(unary-insn rorc (f-0-4 7) (f-4-3 3) (f-8-4 #xB) #xA #x2 #xE rorc-sem)
;-------------------------------------------------------------
; rot - rotate
;-------------------------------------------------------------
; TODO future: split this into .b and .w semantics
(define-pmacro (rot-1-sem mode src1 dst)
(sequence ((mode tmp) (mode b_or_w) (USI mask) (SI shift))
(case DFLT src1
((#x0) (set shift 1))
((#x1) (set shift 2))
((#x2) (set shift 3))
((#x3) (set shift 4))
((#x4) (set shift 5))
((#x5) (set shift 6))
((#x6) (set shift 7))
((#x7) (set shift 8))
((-8) (set shift -1))
((-7) (set shift -2))
((-6) (set shift -3))
((-5) (set shift -4))
((-4) (set shift -5))
((-3) (set shift -6))
((-2) (set shift -7))
((-1) (set shift -8))
(else (set shift 0))
)
(set b_or_w -1)
(set b_or_w (srl b_or_w #x8))
(if (eq b_or_w #x0)
(set mask #x7fff) ; .b
(set mask #x7fffffff)) ; .w
(set tmp dst)
(if (gt mode shift 0)
(sequence ()
(set tmp (rol mode tmp shift))
(set cbit (and tmp #x1)))
(sequence ()
(set tmp (ror mode tmp (mul shift -1)))
(set cbit (and tmp mask))))
(set-z-and-s tmp)
(set dst tmp))
)
(define-pmacro (rot-2-sem mode dst)
(sequence ((mode tmp) (mode b_or_w) (USI mask))
(set b_or_w -1)
(set b_or_w (srl b_or_w #x8))
(if (eq b_or_w #x0)
(set mask #x7fff) ; .b
(set mask #x7fffffff)) ; .w
(set tmp dst)
(if (gt mode (reg h-r1h) 0)
(sequence ()
(set tmp (rol mode tmp (reg h-r1h)))
(set cbit (and tmp #x1)))
(sequence ()
(set tmp (ror mode tmp (reg h-r1h)))
(set cbit (and tmp mask))))
(set-z-and-s tmp)
(set dst tmp))
)
; rot.BW #imm4,dst
(binary-arith16-shimm4-dst-defn QI .b 0 0 rot (f-0-4 #xE) (f-4-3 0) rot-1-sem)
(binary-arith16-shimm4-dst-defn HI .w 0 1 rot (f-0-4 #xE) (f-4-3 0) rot-1-sem)
(binary-arith32-shimm4-dst-defn QI .b 0 0 rot #x7 #x2 rot-1-sem)
(binary-arith32-shimm4-dst-defn HI .w 0 1 rot #x7 #x2 rot-1-sem)
; rot.BW src,dst
(dni rot16.b-dst "rot r1h,dest" ((machine 16))
("rot.b r1h,${dst16-16-QI}")
(+ (f-0-4 7) (f-4-4 #x4) (f-8-4 #x6) dst16-16-QI)
(rot-2-sem QI dst16-16-QI)
())
(dni rot16.w-dst "rot r1h,dest" ((machine 16))
("rot.w r1h,${dst16-16-HI}")
(+ (f-0-4 7) (f-4-4 #x5) (f-8-4 #x6) dst16-16-HI)
(rot-2-sem HI dst16-16-HI)
())
(dni rot32.b-dst "rot r1h,dest" ((machine 32))
("rot.b r1h,${dst32-16-Unprefixed-QI}")
(+ (f-0-4 #xA) dst32-16-Unprefixed-QI (f-7-1 0) (f-10-2 3) (f-12-4 #xF))
(rot-2-sem QI dst32-16-Unprefixed-QI)
())
(dni rot32.w-dst "rot r1h,dest" ((machine 32))
("rot.w r1h,${dst32-16-Unprefixed-HI}")
(+ (f-0-4 #xA) dst32-16-Unprefixed-HI (f-7-1 1) (f-10-2 3) (f-12-4 #xF))
(rot-2-sem HI dst32-16-Unprefixed-HI)
())
;-------------------------------------------------------------
; rts - return from subroutine
;-------------------------------------------------------------
(define-pmacro (rts16-sem)
(sequence ((SI tpc))
(set tpc (mem16 HI (reg h-sp)))
(set (reg h-sp) (add (reg h-sp) 2))
(set tpc (or tpc (sll (mem16 QI (reg h-sp)) 16)))
(set (reg h-sp) (add (reg h-sp) 1))
(set pc tpc)
)
)
(define-pmacro (rts32-sem)
(sequence ((SI tpc))
(set tpc (mem32 HI (reg h-sp)))
(set (reg h-sp) (add (reg h-sp) 2))
(set tpc (or tpc (sll (mem32 HI (reg h-sp)) 16)))
(set (reg h-sp) (add (reg h-sp) 2))
(set pc tpc)
)
)
(dni rts16 "rts" ((machine 16))
("rts")
(+ (f-0-4 #xF) (f-4-4 3))
(rts16-sem)
())
(dni rts32 "rts" ((machine 32))
("rts")
(+ (f-0-4 #xD) (f-4-4 #xF))
(rts32-sem)
())
;-------------------------------------------------------------
; sbb - subtract with borrow
;-------------------------------------------------------------
(define-pmacro (sbb-sem mode src dst)
(sequence ((mode result))
(set result (subc mode dst src cbit))
(set obit (add-oflag mode dst src cbit))
(set cbit (add-oflag mode dst src cbit))
(set-z-and-s result)
(set dst result))
)
; sbb.size:G #imm,dst
(binary-arith16-imm-dst-defn QI QI .b 0 sbb X (f-0-4 7) (f-4-3 3) (f-8-4 7) sbb-sem)
(binary-arith16-imm-dst-defn HI HI .w 1 sbb X (f-0-4 7) (f-4-3 3) (f-8-4 7) sbb-sem)
(binary-arith32-imm-dst-Prefixed QI QI .b 0 sbb X #x9 #x2 #xE sbb-sem)
(binary-arith32-imm-dst-Prefixed HI HI .w 1 sbb X #x9 #x2 #xE sbb-sem)
; sbb.BW:G src,dst
(binary-arith16-src-dst-defn QI QI .b 0 sbb X (f-0-4 #xB) (f-4-3 4) sbb-sem)
(binary-arith16-src-dst-defn HI HI .w 1 sbb X (f-0-4 #xB) (f-4-3 4) sbb-sem)
(binary-arith32-src-dst-Prefixed QI QI .b 0 sbb X #x1 #x6 sbb-sem)
(binary-arith32-src-dst-Prefixed HI HI .w 1 sbb X #x1 #x6 sbb-sem)
;-------------------------------------------------------------
; sbjnz - subtract then jump on not zero
;-------------------------------------------------------------
(define-pmacro (sub-jnz-sem mode src dst label)
(sequence ((mode result))
(set result (sub mode dst src))
(set dst result)
(if (ne result 0)
(set pc label)))
)
; sbjnz.size #imm4,dst,label
(arith-jnz-imm4-dst sbjnz s4n (f-0-4 #xF) (f-4-3 4) #xf #x1 sub-jnz-sem)
;-------------------------------------------------------------
; sccnd - store condition on condition (m32)
;-------------------------------------------------------------
(define-pmacro (sccnd-sem cnd dst)
(sequence ()
(set dst 0)
(case DFLT cnd
((#x00) (if (not cbit) (set dst 1))) ;ltu nc
((#x01) (if (or cbit zbit) (set dst 1))) ;leu
((#x02) (if (not zbit) (set dst 1))) ;ne nz
((#x03) (if (not sbit) (set dst 1))) ;pz
((#x04) (if (not obit) (set dst 1))) ;no
((#x05) (if (not (or zbit (xor sbit obit))) (set dst 1))) ;gt
((#x06) (if (xor sbit obit) (set dst 1))) ;ge
((#x08) (if (trunc BI cbit) (set dst 1))) ;geu c
((#x09) (if (not (or cbit zbit)) (set dst 1))) ;gtu
((#x0a) (if (trunc BI zbit) (set dst 1))) ;eq z
((#x0b) (if (trunc BI sbit) (set dst 1))) ;n
((#x0c) (if (trunc BI obit) (set dst 1))) ;o
((#x0d) (if (or zbit (xor sbit obit)) (set dst 1))) ;le
((#x0e) (if (xor sbit obit) (set dst 1))) ;lt
)
)
)
; scCND dst
(dni sccnd
"sccnd dst"
((machine 32))
"sc$sccond32 ${dst32-16-Unprefixed-HI}"
(+ (f-0-4 #xD) dst32-16-Unprefixed-HI (f-7-1 1) (f-10-2 3) sccond32)
(sccnd-sem sccond32 dst32-16-Unprefixed-HI)
())
;-------------------------------------------------------------
; scmpu - string compare unequal (m32)
;-------------------------------------------------------------
; TODO semantics
(dni scmpu.b "scmpu.b" ((machine 32))
("scmpu.b")
(+ (f-0-4 #xB) (f-4-4 8) (f-8-4 #xC) (f-12-4 3))
(c-call VOID "scmpu_QI_semantics")
())
(dni scmpu.w "scmpu.w" ((machine 32))
("scmpu.w")
(+ (f-0-4 #xB) (f-4-4 8) (f-8-4 #xD) (f-12-4 3))
(c-call VOID "scmpu_HI_semantics")
())
;-------------------------------------------------------------
; sha - shift arithmetic
;-------------------------------------------------------------
; TODO future: split this into .b and .w semantics
(define-pmacro (sha-sem mode src1 dst)
(sequence ((mode result)(mode shift)(mode shmode))
(case DFLT src1
((#x0) (set shift 1))
((#x1) (set shift 2))
((#x2) (set shift 3))
((#x3) (set shift 4))
((#x4) (set shift 5))
((#x5) (set shift 6))
((#x6) (set shift 7))
((#x7) (set shift 8))
((-8) (set shift -1))
((-7) (set shift -2))
((-6) (set shift -3))
((-5) (set shift -4))
((-4) (set shift -5))
((-3) (set shift -6))
((-2) (set shift -7))
((-1) (set shift -8))
(else (set shift 0))
)
(set shmode -1)
(set shmode (srl shmode #x8))
(if (lt mode shift #x0) (set result (sra mode dst (mul shift -1))))
(if (gt mode shift 0) (set result (sll mode dst shift)))
(if (eq shmode #x0) ; QI
(sequence
((mode cbitamt))
(if (lt mode shift #x0)
(set cbitamt (sub #x8 shift)) ; sra
(set cbitamt (sub shift 1))) ; sll
(set cbit (srl (and (sll dst cbitamt) #x80) #x7))
(set obit (ne (and dst #x80) (and result #x80)))
))
(if (eq shmode #xff) ; HI
(sequence
((mode cbitamt))
(if (lt mode shift #x0)
(set cbitamt (sub 16 shift)) ; sra
(set cbitamt (sub shift 1))) ; sll
(set cbit (srl (and (sll dst cbitamt) #x8000) #xf))
(set obit (ne (and dst #x8000) (and result #x8000)))
))
(set-z-and-s result)
(set dst result))
)
(define-pmacro (shar1h-sem mode dst)
(sequence ((mode result)(mode shmode))
(set shmode -1)
(set shmode (srl shmode #x8))
(if (lt mode (reg h-r1h) 0) (set result (sra mode dst (reg h-r1h))))
(if (gt mode (reg h-r1h) 0) (set result (sll mode dst (reg h-r1h))))
(if (eq shmode #x0) ; QI
(sequence
((mode cbitamt))
(if (lt mode (reg h-r1h) #x0)
(set cbitamt (sub #x8 (reg h-r1h))) ; sra
(set cbitamt (sub (reg h-r1h) 1))) ; sll
(set cbit (srl (and (sll dst cbitamt) #x80) #x7))
(set obit (ne (and dst #x80) (and result #x80)))
))
(if (eq shmode #xff) ; HI
(sequence
((mode cbitamt))
(if (lt mode (reg h-r1h) #x0)
(set cbitamt (sub 16 (reg h-r1h))) ; sra
(set cbitamt (sub (reg h-r1h) 1))) ; sll
(set cbit (srl (and (sll dst cbitamt) #x8000) #xf))
(set obit (ne (and dst #x8000) (and result #x8000)))
))
(set-z-and-s result)
(set dst result))
)
; sha.BW #imm4,dst (m16 #1 m32 #1)
(binary-arith16-shimm4-dst-defn QI .b 0 0 sha (f-0-4 #xF) (f-4-3 0) sha-sem)
(binary-arith16-shimm4-dst-defn HI .w 0 1 sha (f-0-4 #xF) (f-4-3 0) sha-sem)
(binary-arith32-shimm4-dst-defn QI .b 1 0 sha #x7 #x0 sha-sem)
(binary-arith32-shimm4-dst-defn HI .w 1 1 sha #x7 #x0 sha-sem)
; sha.BW r1h,dst (m16 #2 m32 #3)
(dni sha16.b-dst "sha.b r1h,dest" ((machine 16))
("sha.b r1h,${dst16-16-QI}")
(+ (f-0-4 7) (f-4-4 4) (f-8-4 #xF) dst16-16-QI)
(shar1h-sem HI dst16-16-QI)
())
(dni sha16.w-dst "sha.w r1h,dest" ((machine 16))
("sha.w r1h,${dst16-16-HI}")
(+ (f-0-4 7) (f-4-4 5) (f-8-4 #xF) dst16-16-HI)
(shar1h-sem HI dst16-16-HI)
())
(dni sha32.b-dst "sha.b r1h,dest" ((machine 32))
("sha.b r1h,${dst32-16-Unprefixed-QI}")
(+ (f-0-4 #xB) dst32-16-Unprefixed-QI (f-7-1 0) (f-10-2 3) (f-12-4 #xE))
(shar1h-sem QI dst32-16-Unprefixed-QI)
())
(dni sha32.w-dst "sha.w r1h,dest" ((machine 32))
("sha.w r1h,${dst32-16-Unprefixed-HI}")
(+ (f-0-4 #xB) dst32-16-Unprefixed-HI (f-7-1 1) (f-10-2 3) (f-12-4 #xE))
(shar1h-sem HI dst32-16-Unprefixed-HI)
())
; sha.L #imm,dst (m16 #3)
(dni sha16-L-imm-r2r0 "sha.L #Imm-sh-12-s4,r2r0" ((machine 16))
"sha.l #${Imm-sh-12-s4},r2r0"
(+ (f-0-4 #xE) (f-4-4 #xB) (f-8-4 #xA) Imm-sh-12-s4)
(sha-sem SI Imm-sh-12-s4 (reg h-r2r0))
())
(dni sha16-L-imm-r3r1 "sha.L #Imm-sh-12-s4,r3r1" ((machine 16))
"sha.l #${Imm-sh-12-s4},r3r1"
(+ (f-0-4 #xE) (f-4-4 #xB) (f-8-4 #xB) Imm-sh-12-s4)
(sha-sem SI Imm-sh-12-s4 (reg h-r3r1))
())
; sha.L r1h,dst (m16 #4)
(dni sha16-L-r1h-r2r0 "sha.L r1h,r2r0" ((machine 16))
"sha.l r1h,r2r0"
(+ (f-0-4 #xE) (f-4-4 #xB) (f-8-4 2) (f-12-4 1))
(sha-sem SI (reg h-r1h) (reg h-r2r0))
())
(dni sha16-L-r1h-r3r1 "sha.L r1h,r3r1" ((machine 16))
"sha.l r1h,r3r1"
(+ (f-0-4 #xE) (f-4-4 #xB) (f-8-4 3) (f-12-4 1))
(sha-sem SI (reg h-r1h) (reg h-r3r1))
())
; sha.L #imm8,dst (m32 #2)
(binary-arith32-imm-dst-defn QI SI .l 0 sha X #xA #x2 #x1 sha-sem)
; sha.L r1h,dst (m32 #4)
(dni sha32.l-dst "sha.l r1h,dest" ((machine 32))
("sha.l r1h,${dst32-16-Unprefixed-SI}")
(+ (f-0-4 #xC) dst32-16-Unprefixed-SI (f-7-1 0) (f-10-2 1) (f-12-4 1))
(shar1h-sem QI dst32-16-Unprefixed-SI)
())
;-------------------------------------------------------------
; shanc - shift arithmetic non carry (m32)
;-------------------------------------------------------------
; TODO check semantics
; shanc.L #imm8,dst
(binary-arith32-imm-dst-defn QI SI .l 0 shanc X #xC #x2 #x1 sha-sem)
;-------------------------------------------------------------
; shl - shift logical
;-------------------------------------------------------------
; TODO future: split this into .b and .w semantics
(define-pmacro (shl-sem mode src1 dst)
(sequence ((mode result)(mode shift)(mode shmode))
(case DFLT src1
((#x0) (set shift 1))
((#x1) (set shift 2))
((#x2) (set shift 3))
((#x3) (set shift 4))
((#x4) (set shift 5))
((#x5) (set shift 6))
((#x6) (set shift 7))
((#x7) (set shift 8))
((-8) (set shift -1))
((-7) (set shift -2))
((-6) (set shift -3))
((-5) (set shift -4))
((-4) (set shift -5))
((-3) (set shift -6))
((-2) (set shift -7))
((-1) (set shift -8))
(else (set shift 0))
)
(set shmode -1)
(set shmode (srl shmode #x8))
(if (lt mode shift #x0) (set result (srl mode dst (mul shift -1))))
(if (gt mode shift 0) (set result (sll mode dst shift)))
(if (eq shmode #x0) ; QI
(sequence
((mode cbitamt))
(if (lt mode shift #x0)
(set cbitamt (sub #x8 shift)); srl
(set cbitamt (sub shift 1))) ; sll
(set cbit (srl (and (sll dst cbitamt) #x80) #x7))
(set obit (ne (and dst #x80) (and result #x80)))
))
(if (eq shmode #xff) ; HI
(sequence
((mode cbitamt))
(if (lt mode shift #x0)
(set cbitamt (sub 16 shift)) ; srl
(set cbitamt (sub shift 1))) ; sll
(set cbit (srl (and (sll dst cbitamt) #x8000) #xf))
(set obit (ne (and dst #x8000) (and result #x8000)))
))
(set-z-and-s result)
(set dst result))
)
(define-pmacro (shlr1h-sem mode dst)
(sequence ((mode result)(mode shmode))
(set shmode -1)
(set shmode (srl shmode #x8))
(if (lt mode (reg h-r1h) 0) (set result (srl mode dst (reg h-r1h))))
(if (gt mode (reg h-r1h) 0) (set result (sll mode dst (reg h-r1h))))
(if (eq shmode #x0) ; QI
(sequence
((mode cbitamt))
(if (lt mode (reg h-r1h) #x0)
(set cbitamt (sub #x8 (reg h-r1h))) ; srl
(set cbitamt (sub (reg h-r1h) 1))) ; sll
(set cbit (srl (and (sll dst cbitamt) #x80) #x7))
(set obit (ne (and dst #x80) (and result #x80)))
))
(if (eq shmode #xff) ; HI
(sequence
((mode cbitamt))
(if (lt mode (reg h-r1h) #x0)
(set cbitamt (sub 16 (reg h-r1h))) ; srl
(set cbitamt (sub (reg h-r1h) 1))) ; sll
(set cbit (srl (and (sll dst cbitamt) #x8000) #xf))
(set obit (ne (and dst #x8000) (and result #x8000)))
))
(set-z-and-s result)
(set dst result))
)
; shl.BW #imm4,dst (m16 #1 m32 #1)
(binary-arith16-shimm4-dst-defn QI .b 0 0 shl (f-0-4 #xE) (f-4-3 4) shl-sem)
(binary-arith16-shimm4-dst-defn HI .w 0 1 shl (f-0-4 #xE) (f-4-3 4) shl-sem)
(binary-arith32-shimm4-dst-defn QI .b 0 0 shl #x7 #x0 shl-sem)
(binary-arith32-shimm4-dst-defn HI .w 0 1 shl #x7 #x0 shl-sem)
; shl.BW r1h,dst (m16 #2 m32 #3)
(dni shl16.b-dst "shl.b r1h,dest" ((machine 16))
("shl.b r1h,${dst16-16-QI}")
(+ (f-0-4 7) (f-4-4 4) (f-8-4 #xE) dst16-16-QI)
(shlr1h-sem HI dst16-16-QI)
())
(dni shl16.w-dst "shl.w r1h,dest" ((machine 16))
("shl.w r1h,${dst16-16-HI}")
(+ (f-0-4 7) (f-4-4 5) (f-8-4 #xE) dst16-16-HI)
(shlr1h-sem HI dst16-16-HI)
())
(dni shl32.b-dst "shl.b r1h,dest" ((machine 32))
("shl.b r1h,${dst32-16-Unprefixed-QI}")
(+ (f-0-4 #xA) dst32-16-Unprefixed-QI (f-7-1 0) (f-10-2 3) (f-12-4 #xE))
(shlr1h-sem QI dst32-16-Unprefixed-QI)
())
(dni shl32.w-dst "shl.w r1h,dest" ((machine 32))
("shl.w r1h,${dst32-16-Unprefixed-HI}")
(+ (f-0-4 #xA) dst32-16-Unprefixed-HI (f-7-1 1) (f-10-2 3) (f-12-4 #xE))
(shlr1h-sem HI dst32-16-Unprefixed-HI)
())
; shl.L #imm,dst (m16 #3)
(dni shl16-L-imm-r2r0 "shl.L #Imm-sh-12-s4,r2r0" ((machine 16))
"shl.l #${Imm-sh-12-s4},r2r0"
(+ (f-0-4 #xE) (f-4-4 #xB) (f-8-4 #x8) Imm-sh-12-s4)
(shl-sem SI Imm-sh-12-s4 (reg h-r2r0))
())
(dni shl16-L-imm-r3r1 "shl.L #Imm-sh-12-s4,r3r1" ((machine 16))
"shl.l #${Imm-sh-12-s4},r3r1"
(+ (f-0-4 #xE) (f-4-4 #xB) (f-8-4 #x9) Imm-sh-12-s4)
(shl-sem SI Imm-sh-12-s4 (reg h-r3r1))
())
; shl.L r1h,dst (m16 #4)
(dni shl16-L-r1h-r2r0 "shl.L r1h,r2r0" ((machine 16))
"shl.l r1h,r2r0"
(+ (f-0-4 #xE) (f-4-4 #xB) (f-8-4 0) (f-12-4 1))
(shl-sem SI (reg h-r1h) (reg h-r2r0))
())
(dni shl16-L-r1h-r3r1 "shl.L r1h,r3r1" ((machine 16))
"shl.l r1h,r3r1"
(+ (f-0-4 #xE) (f-4-4 #xB) (f-8-4 1) (f-12-4 1))
(shl-sem SI (reg h-r1h) (reg h-r3r1))
())
; shl.L #imm8,dst (m32 #2)
(binary-arith32-imm-dst-defn QI SI .l 0 shl X #x9 #x2 #x1 shl-sem)
; shl.L r1h,dst (m32 #4)
(dni shl32.l-dst "shl.l r1h,dest" ((machine 32))
("shl.l r1h,${dst32-16-Unprefixed-SI}")
(+ (f-0-4 #xC) dst32-16-Unprefixed-SI (f-7-1 0) (f-10-2 0) (f-12-4 1))
(shlr1h-sem QI dst32-16-Unprefixed-SI)
())
;-------------------------------------------------------------
; shlnc - shift logical non carry
;-------------------------------------------------------------
; TODO check semantics
; shlnc.L #imm8,dst
(binary-arith32-imm-dst-defn QI SI .l 0 shlnc X #x8 #x2 #x1 shl-sem)
;-------------------------------------------------------------
; sin - string input (m32)
;-------------------------------------------------------------
; TODO semantics
(dni sin32.b "sin" ((machine 32))
("sin.b")
(+ (f-0-4 #xB) (f-4-4 2) (f-8-4 8) (f-12-4 3))
(c-call VOID "sin_QI_semantics")
())
(dni sin32.w "sin" ((machine 32))
("sin.w")
(+ (f-0-4 #xB) (f-4-4 2) (f-8-4 9) (f-12-4 3))
(c-call VOID "sin_HI_semantics")
())
;-------------------------------------------------------------
; smovb - string move backward
;-------------------------------------------------------------
; TODO semantics
(dni smovb16.b "smovb.b" ((machine 16))
("smovb.b")
(+ (f-0-4 7) (f-4-4 #xC) (f-8-4 #xE) (f-12-4 9))
(c-call VOID "smovb_QI_semantics")
())
(dni smovb16.w "smovb.w" ((machine 16))
("smovb.w")
(+ (f-0-4 7) (f-4-4 #xD) (f-8-4 #xE) (f-12-4 9))
(c-call VOID "smovb_HI_semantics")
())
(dni smovb32.b "smovb.b" ((machine 32))
("smovb.b")
(+ (f-0-4 #xB) (f-4-4 6) (f-8-4 8) (f-12-4 3))
(c-call VOID "smovb_QI_semantics")
())
(dni smovb32.w "smovb.w" ((machine 32))
("smovb.w")
(+ (f-0-4 #xB) (f-4-4 6) (f-8-4 9) (f-12-4 3))
(c-call VOID "smovb_HI_semantics")
())
;-------------------------------------------------------------
; smovf - string move forward (m32)
;-------------------------------------------------------------
; TODO semantics
(dni smovf16.b "smovf.b" ((machine 16))
("smovf.b")
(+ (f-0-4 7) (f-4-4 #xC) (f-8-4 #xE) (f-12-4 8))
(c-call VOID "smovf_QI_semantics")
())
(dni smovf16.w "smovf.w" ((machine 16))
("smovf.w")
(+ (f-0-4 7) (f-4-4 #xD) (f-8-4 #xE) (f-12-4 8))
(c-call VOID "smovf_HI_semantics")
())
(dni smovf32.b "smovf.b" ((machine 32))
("smovf.b")
(+ (f-0-4 #xB) (f-4-4 0) (f-8-4 8) (f-12-4 3))
(c-call VOID "smovf_QI_semantics")
())
(dni smovf32.w "smovf.w" ((machine 32))
("smovf.w")
(+ (f-0-4 #xB) (f-4-4 0) (f-8-4 9) (f-12-4 3))
(c-call VOID "smovf_HI_semantics")
())
;-------------------------------------------------------------
; smovu - string move unequal (m32)
;-------------------------------------------------------------
; TODO semantics
(dni smovu.b "smovu.b" ((machine 32))
("smovu.b")
(+ (f-0-4 #xB) (f-4-4 8) (f-8-4 8) (f-12-4 3))
(c-call VOID "smovu_QI_semantics")
())
(dni smovu.w "smovu.w" ((machine 32))
("smovu.w")
(+ (f-0-4 #xB) (f-4-4 8) (f-8-4 9) (f-12-4 3))
(c-call VOID "smovu_HI_semantics")
())
;-------------------------------------------------------------
; sout - string output (m32)
;-------------------------------------------------------------
; TODO semantics
(dni sout.b "sout.b" ((machine 32))
("sout.b")
(+ (f-0-4 #xB) (f-4-4 4) (f-8-4 8) (f-12-4 3))
(c-call VOID "sout_QI_semantics")
())
(dni sout.w "sout" ((machine 32))
("sout.w")
(+ (f-0-4 #xB) (f-4-4 4) (f-8-4 9) (f-12-4 3))
(c-call VOID "sout_HI_semantics")
())
;-------------------------------------------------------------
; sstr - string store
;-------------------------------------------------------------
; TODO semantics
(dni sstr16.b "sstr.b" ((machine 16))
("sstr.b")
(+ (f-0-4 7) (f-4-4 #xC) (f-8-4 #xE) (f-12-4 #xA))
(c-call VOID "sstr_QI_semantics")
())
(dni sstr16.w "sstr.w" ((machine 16))
("sstr.w")
(+ (f-0-4 7) (f-4-4 #xD) (f-8-4 #xE) (f-12-4 #xA))
(c-call VOID "sstr_HI_semantics")
())
(dni sstr.b "sstr" ((machine 32))
("sstr.b")
(+ (f-0-4 #xB) (f-4-4 8) (f-8-4 0) (f-12-4 3))
(c-call VOID "sstr_QI_semantics")
())
(dni sstr.w "sstr" ((machine 32))
("sstr.w")
(+ (f-0-4 #xB) (f-4-4 8) (f-8-4 1) (f-12-4 3))
(c-call VOID "sstr_HI_semantics")
())
;-------------------------------------------------------------
; stnz - store on not zero
;-------------------------------------------------------------
(define-pmacro (stnz-sem mode src dst)
(sequence ()
(if (ne zbit (const 1))
(set dst src)))
)
; stnz #imm8,dst3 (m16)
(binary-arith16-b-S-imm8-dst3 stnz "" (f-0-4 #xD) (f-4-1 0) stnz-sem)
; stnz.BW #imm,dst (m32)
(binary-arith32-imm-dst-defn QI QI .b 0 stnz X #x9 #x1 #xF stnz-sem)
(binary-arith32-imm-dst-defn HI HI .w 1 stnz X #x9 #x1 #xF stnz-sem)
;-------------------------------------------------------------
; stz - store on zero
;-------------------------------------------------------------
(define-pmacro (stz-sem mode src dst)
(sequence ()
(if (eq zbit (const 1))
(set dst src)))
)
; stz #imm8,dst3 (m16)
(binary-arith16-b-S-imm8-dst3 stz "" (f-0-4 #xC) (f-4-1 1) stz-sem)
; stz.BW #imm,dst (m32)
(binary-arith32-imm-dst-defn QI QI .b 0 stz X #x9 #x0 #xF stz-sem)
(binary-arith32-imm-dst-defn HI HI .w 1 stz X #x9 #x0 #xF stz-sem)
;-------------------------------------------------------------
; stzx - store on zero extention
;-------------------------------------------------------------
(define-pmacro (stzx-sem mode src1 src2 dst)
(sequence ()
(if (eq zbit (const 1))
(set dst src1)
(set dst src2)))
)
; stzx #imm8,dst3 (m16)
(dni stzx16-imm8-imm8-r0h "stzx #Imm8,#Imm8,r0h" ((machine 16))
("stzx #${Imm-8-QI},#${Imm-16-QI},r0h")
(+ (f-0-4 #xD) (f-4-4 #xB) Imm-8-QI Imm-16-QI)
(stzx-sem QI Imm-8-QI Imm-16-QI (reg h-r0h))
())
(dni stzx16-imm8-imm8-r0l "stzx #Imm8,#Imm8,r0l" ((machine 16))
("stzx #${Imm-8-QI},#${Imm-16-QI},r0l")
(+ (f-0-4 #xD) (f-4-4 #xC) Imm-8-QI Imm-16-QI)
(stzx-sem QI Imm-8-QI Imm-16-QI (reg h-r0l))
())
(dni stzx16-imm8-imm8-dsp8sb "stzx #Imm8,#Imm8,dsp8[sb]" ((machine 16))
("stzx #${Imm-8-QI},#${Imm-24-QI},${Dsp-16-u8}[sb]")
(+ (f-0-4 #xD) (f-4-4 #xD) Imm-8-QI Dsp-16-u8 Imm-24-QI)
(stzx-sem QI Imm-8-QI Imm-16-QI (mem16 QI (add (reg h-sb) Dsp-24-u8)))
())
(dni stzx16-imm8-imm8-dsp8fb "stzx #Imm8,#Imm8,dsp8[fb]" ((machine 16))
("stzx #${Imm-8-QI},#${Imm-24-QI},${Dsp-16-s8}[fb]")
(+ (f-0-4 #xD) (f-4-4 #xE) Imm-8-QI Dsp-16-s8 Imm-24-QI)
(stzx-sem QI Imm-8-QI Imm-24-QI (mem16 QI (add (reg h-fb) Dsp-16-s8)))
())
(dni stzx16-imm8-imm8-abs16 "stzx #Imm8,#Imm8,abs16" ((machine 16))
("stzx #${Imm-8-QI},#${Imm-32-QI},${Dsp-16-u16}")
(+ (f-0-4 #xD) (f-4-4 #xE) Imm-8-QI Dsp-16-u16 Imm-32-QI)
(stzx-sem QI Imm-8-QI Imm-32-QI (mem16 QI Dsp-16-u16))
())
; stzx.BW #imm,dst (m32)
(insn-imm1-imm2-dst-Unprefixed stzx #x9 #x3 #xF stzx-sem)
;-------------------------------------------------------------
; subx - subtract extend (m32)
;-------------------------------------------------------------
(define-pmacro (subx-sem mode src1 dst)
(sequence ((mode result))
(set result (sub mode dst (ext mode src1)))
(set obit (sub-oflag mode dst (ext mode src1) 0))
(set cbit (sub-cflag mode dst (ext mode src1) 0))
(set dst result)
(set-z-and-s result)))
; subx #imm8,dst
(binary-arith32-imm-dst-defn QI SI "" 0 subx G #x9 #x1 #x1 subx-sem)
; subx src,dst
(binary-arith32-src-dst-defn QI SI "" 0 subx G #x1 #x0 subx-sem)
;-------------------------------------------------------------
; tst - test
;-------------------------------------------------------------
(define-pmacro (tst-sem mode src1 dst)
(sequence ((mode result))
(set result (and mode dst src1))
(set-z-and-s result))
)
; tst.BW #imm,dst (m16 #1 m32 #1)
(binary-arith-imm-dst tst G (f-0-4 7) (f-4-3 3) (f-8-4 0) #x9 #x3 #xE tst-sem)
; tst.BW src,dst (m16 #2 m32 #3)
(binary-arith16-src-dst-defn QI QI .b 0 tst X (f-0-4 #x8) (f-4-3 0) tst-sem)
(binary-arith16-src-dst-defn HI HI .w 1 tst X (f-0-4 #x8) (f-4-3 0) tst-sem)
(binary-arith32-src-dst-Prefixed QI QI .b 0 tst G #x1 #x9 tst-sem)
(binary-arith32-src-dst-Prefixed HI HI .w 1 tst G #x1 #x9 tst-sem)
; tst.BW:S #imm,dst2 (m32 #2)
(binary-arith32-s-imm-dst QI .b 0 tst #x0 #x6 tst-sem)
(binary-arith32-s-imm-dst HI .w 1 tst #x0 #x6 tst-sem)
;-------------------------------------------------------------
; und - undefined
;-------------------------------------------------------------
(dni und16 "und" ((machine 16))
("und")
(+ (f-0-4 #xF) (f-4-4 #xF))
(nop)
())
(dni und32 "und" ((machine 32))
("und")
(+ (f-0-4 #xF) (f-4-4 #xF))
(nop)
())
;-------------------------------------------------------------
; wait
;-------------------------------------------------------------
; ??? semantics
(dni wait16 "wait" ((machine 16))
("wait")
(+ (f-0-4 7) (f-4-4 #xD) (f-8-4 #xF) (f-12-4 3))
(nop)
())
(dni wait "wait" ((machine 32))
("wait")
(+ (f-0-4 #xB) (f-4-4 2) (f-8-4 0) (f-12-4 3))
(nop)
())
;-------------------------------------------------------------
; xchg - exchange
;-------------------------------------------------------------
(define-pmacro (xchg-sem mode src dst)
(sequence ((mode result))
(set result src)
(set src dst)
(set dst result))
)
(define-pmacro (xchg16-defn mode sz szc src srcreg)
(dni (.sym xchg16 sz - srcreg)
(.str "xchg" sz "-" srcreg ",dst16-16-" mode)
((machine 16))
(.str "xchg." sz " " srcreg ",${dst16-16-" mode "}")
(+ (f-0-4 #x7) (f-4-3 #x5) (f-7-1 szc) (f-8-2 0) (f-10-2 src) (.sym dst16-16- mode))
(xchg-sem mode (reg (.sym h- srcreg)) (.sym dst16-16- mode))
())
)
(xchg16-defn QI b 0 0 r0l)
(xchg16-defn QI b 0 1 r0h)
(xchg16-defn QI b 0 2 r1l)
(xchg16-defn QI b 0 3 r1h)
(xchg16-defn HI w 1 0 r0)
(xchg16-defn HI w 1 1 r1)
(xchg16-defn HI w 1 2 r2)
(xchg16-defn HI w 1 3 r3)
(define-pmacro (xchg32-defn mode sz szc src srcreg)
(dni (.sym xchg32 sz - srcreg)
(.str "xchg" sz "-" srcreg ",dst32-16-Unprefixed-" mode)
((machine 32))
(.str "xchg." sz " " srcreg ",${dst32-16-Unprefixed-" mode "}")
(+ (f-0-4 #xD) (.sym dst32-16-Unprefixed- mode) (f-7-1 szc) (f-10-2 0) (f-12-1 1) (f-13-3 src))
(xchg-sem mode (reg (.sym h- srcreg)) (.sym dst32-16-Unprefixed- mode))
())
)
(xchg32-defn QI b 0 0 r0l)
(xchg32-defn QI b 0 1 r1l)
(xchg32-defn QI b 0 2 a0)
(xchg32-defn QI b 0 3 a1)
(xchg32-defn QI b 0 4 r0h)
(xchg32-defn QI b 0 5 r1h)
(xchg32-defn HI w 1 0 r0)
(xchg32-defn HI w 1 1 r1)
(xchg32-defn HI w 1 2 a0)
(xchg32-defn HI w 1 3 a1)
(xchg32-defn HI w 1 4 r2)
(xchg32-defn HI w 1 5 r3)
;-------------------------------------------------------------
; xor - exclusive or
;-------------------------------------------------------------
(define-pmacro (xor-sem mode src1 dst)
(sequence ((mode result))
(set result (xor mode src1 dst))
(set-z-and-s result)
(set dst result))
)
; xor.BW #imm,dst (m16 #1 m32 #1)
(binary-arith-imm-dst xor G (f-0-4 7) (f-4-3 3) (f-8-4 1) #x9 #x0 #xE xor-sem)
; xor.BW src,dst (m16 #3 m32 #3)
(binary-arith-src-dst xor G (f-0-4 #x8) (f-4-3 4) #x1 #x9 xor-sem)
;-------------------------------------------------------------
; Widening
;-------------------------------------------------------------
(define-pmacro (exts-sem smode dmode src dst)
(set dst (ext dmode (trunc smode src)))
)
(define-pmacro (extz-sem smode dmode src dst)
(set dst (zext dmode (trunc smode src)))
)
; exts.b dst for m16c
(ext16-defn QI HI .b 0 exts (f-0-4 7) (f-4-3 6) (f-8-4 6) exts-sem)
; exts.w r0 for m16c
(dni exts16.w-r0
"exts.w r0"
((machine 16))
"exts.w r0"
(+ (f-0-4 #x7) (f-4-4 #xC) (f-8-4 #xF) (f-12-4 3))
(exts-sem HI SI R0 R2R0)
())
; exts.size dst for m32c
(ext32-defn QI HI .b 0 exts (f-0-4 #xC) (f-10-2 1) (f-12-4 #xE) exts-sem)
(ext32-defn HI SI .w 1 exts (f-0-4 #xC) (f-10-2 1) (f-12-4 #xE) exts-sem)
; exts.b src,dst for m32c
(ext32-binary-defn exts .b #x1 #x7 exts-sem)
; extz.b src,dst for m32c
(ext32-binary-defn extz "" #x1 #xB extz-sem)
;-------------------------------------------------------------
; Indirect
;-------------------------------------------------------------
; TODO semantics
(dni srcind "SRC-INDIRECT" ((machine 32))
("src-indirect")
(+ (f-0-4 4) (f-4-4 1))
(set (reg h-src-indirect) 1)
())
(dni destind "DEST-INDIRECT" ((machine 32))
("dest-indirect")
(+ (f-0-4 0) (f-4-4 9))
(set (reg h-dst-indirect) 1)
())
(dni srcdestind "SRC-DEST-INDIRECT" ((machine 32))
("src-dest-indirect")
(+ (f-0-4 4) (f-4-4 9))
(sequence () (set (reg h-src-indirect) 1) (set (reg h-dst-indirect) 1))
())
Reference in New Issue View Git Blame Copy Permalink