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https://github.com/darlinghq/darling-gdb.git
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72c9954b87
* arm-tdep.c (arm_apcs_32): New global. (arm_addr_bits_remove, arm_saved_pc_after_call, arm_push_dummy_frame, arm_pop_frame): New functions. (arm_skip_prologue): Updated version from Richard Earnshaw. (_initialize_arm_tdep): Add set/show "apcs32". * config/arm/tm-arm.h (ADDR_BITS_REMOVE): Call arm_addr_bits_remove. (SAVED_PC_AFTER_CALL): Call arm_saved_pc_after_call. (frame_find_saved_regs): Declare properly. (PUSH_DUMMY_FRAME): Call arm_push_dummy_frame. (POP_FRAME): Call arm_pop_frame, use ADDR_BITS_REMOVE instead of explicit mask. * config/arm/nm-arm.h: New file. * config/arm/xm-arm.h (KERNEL_U_ADDR, FETCH_INFERIOR_REGISTERS): Move definitions to nm-arm.h. * config/arm/arm.mh (NAT_FILE): Define. PR 8941
594 lines
15 KiB
C
594 lines
15 KiB
C
/* Target-dependent code for the Acorn Risc Machine, for GDB, the GNU Debugger.
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Copyright (C) 1988, 1989, 1991, 1992, 1993, 1995, 1996
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Free Software Foundation, Inc.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#include "defs.h"
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#include "frame.h"
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#include "inferior.h"
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#include "gdbcmd.h"
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/* Set to true if the 32-bit mode is in use. */
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int arm_apcs_32 = 1;
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CORE_ADDR
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arm_addr_bits_remove (val)
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CORE_ADDR val;
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{
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return (val & (arm_apcs_32 ? 0xfffffffc : 0x03fffffc));
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}
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CORE_ADDR
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arm_saved_pc_after_call (frame)
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struct frame_info *frame;
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{
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return ADDR_BITS_REMOVE (read_register (LR_REGNUM));
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}
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/* APCS (ARM procedure call standard) defines the following prologue:
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mov ip, sp
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[stmfd sp!, {a1,a2,a3,a4}]
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stmfd sp!, {...,fp,ip,lr,pc}
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[stfe f7, [sp, #-12]!]
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[stfe f6, [sp, #-12]!]
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[stfe f5, [sp, #-12]!]
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[stfe f4, [sp, #-12]!]
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sub fp, ip, #nn // nn == 20 or 4 depending on second ins
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*/
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CORE_ADDR
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arm_skip_prologue (pc)
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CORE_ADDR pc;
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{
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unsigned long inst;
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CORE_ADDR skip_pc = pc;
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inst = read_memory_integer (skip_pc, 4);
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if (inst != 0xe1a0c00d) /* mov ip, sp */
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return pc;
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skip_pc += 4;
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inst = read_memory_integer (skip_pc, 4);
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if ((inst & 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */
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{
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skip_pc += 4;
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inst = read_memory_integer (skip_pc, 4);
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}
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if ((inst & 0xfffff800) != 0xe92dd800) /* stmfd sp!,{...,fp,ip,lr,pc} */
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return pc;
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skip_pc += 4;
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inst = read_memory_integer (skip_pc, 4);
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/* Any insns after this point may float into the code, if it makes
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for better instruction scheduling, so we skip them only if
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we find them, but still consdier the function to be frame-ful */
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/* We may have either one sfmfd instruction here, or several stfe insns,
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depending on the version of floating point code we support. */
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if ((inst & 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
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{
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skip_pc += 4;
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inst = read_memory_integer (skip_pc, 4);
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}
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else
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{
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while ((inst & 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */
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{
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skip_pc += 4;
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inst = read_memory_integer (skip_pc, 4);
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}
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}
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if ((inst & 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */
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skip_pc += 4;
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return skip_pc;
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}
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void
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arm_frame_find_saved_regs (frame_info, saved_regs_addr)
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struct frame_info *frame_info;
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struct frame_saved_regs *saved_regs_addr;
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{
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register int regnum;
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register int frame;
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register int next_addr;
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register int return_data_save;
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register int saved_register_mask;
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memset (saved_regs_addr, '\0', sizeof (*saved_regs_addr));
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frame = frame_info->frame;
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return_data_save = read_memory_integer (frame, 4) & 0x03fffffc - 12;
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saved_register_mask = read_memory_integer (return_data_save, 4);
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next_addr = frame - 12;
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for (regnum = 4; regnum < 10; regnum++)
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if (saved_register_mask & (1 << regnum))
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{
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next_addr -= 4;
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saved_regs_addr->regs[regnum] = next_addr;
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}
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if (read_memory_integer (return_data_save + 4, 4) == 0xed6d7103)
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{
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next_addr -= 12;
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saved_regs_addr->regs[F0_REGNUM + 7] = next_addr;
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}
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if (read_memory_integer (return_data_save + 8, 4) == 0xed6d6103)
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{
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next_addr -= 12;
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saved_regs_addr->regs[F0_REGNUM + 6] = next_addr;
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}
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if (read_memory_integer (return_data_save + 12, 4) == 0xed6d5103)
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{
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next_addr -= 12;
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saved_regs_addr->regs[F0_REGNUM + 5] = next_addr;
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}
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if (read_memory_integer(return_data_save + 16, 4) == 0xed6d4103)
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{
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next_addr -= 12;
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saved_regs_addr->regs[F0_REGNUM + 4] = next_addr;
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}
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saved_regs_addr->regs[SP_REGNUM] = next_addr;
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saved_regs_addr->regs[PC_REGNUM] = frame - 4;
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saved_regs_addr->regs[PS_REGNUM] = frame - 4;
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saved_regs_addr->regs[FP_REGNUM] = frame - 12;
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}
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void
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arm_push_dummy_frame ()
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{
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register CORE_ADDR sp = read_register (SP_REGNUM);
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register int regnum;
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/* opcode for ldmdb fp,{v1-v6,fp,ip,lr,pc}^ */
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sp = push_word (sp, 0xe92dbf0); /* dummy return_data_save ins */
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/* push a pointer to the dummy instruction minus 12 */
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sp = push_word (sp, read_register (SP_REGNUM) - 16);
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sp = push_word (sp, read_register (PS_REGNUM));
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sp = push_word (sp, read_register (SP_REGNUM));
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sp = push_word (sp, read_register (FP_REGNUM));
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for (regnum = 9; regnum >= 4; regnum --)
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sp = push_word (sp, read_register (regnum));
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write_register (FP_REGNUM, read_register (SP_REGNUM) - 8);
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write_register (SP_REGNUM, sp);
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}
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void
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arm_pop_frame ()
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{
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register CORE_ADDR fp = read_register (FP_REGNUM);
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register unsigned long return_data_save =
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read_memory_integer (ADDR_BITS_REMOVE (read_memory_integer (fp, 4)) - 12,
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4);
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register int regnum;
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write_register (PS_REGNUM, read_memory_integer (fp - 4, 4));
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write_register (PC_REGNUM, ADDR_BITS_REMOVE (read_register (PS_REGNUM)));
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write_register (SP_REGNUM, read_memory_integer (fp - 8, 4));
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write_register (FP_REGNUM, read_memory_integer (fp - 12, 4));
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fp -= 12;
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for (regnum = 9; regnum >= 4; regnum--)
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{
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if (return_data_save & (1 << regnum))
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{
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fp -= 4;
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write_register (regnum, read_memory_integer (fp, 4));
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}
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}
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flush_cached_frames ();
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}
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static void
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print_fpu_flags (flags)
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int flags;
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{
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if (flags & (1 << 0)) fputs ("IVO ", stdout);
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if (flags & (1 << 1)) fputs ("DVZ ", stdout);
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if (flags & (1 << 2)) fputs ("OFL ", stdout);
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if (flags & (1 << 3)) fputs ("UFL ", stdout);
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if (flags & (1 << 4)) fputs ("INX ", stdout);
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putchar ('\n');
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}
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void
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arm_float_info ()
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{
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register unsigned long status = read_register (FPS_REGNUM);
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int type;
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type = (status >> 24) & 127;
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printf ("%s FPU type %d\n",
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(status & (1<<31)) ? "Hardware" : "Software",
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type);
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fputs ("mask: ", stdout);
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print_fpu_flags (status >> 16);
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fputs ("flags: ", stdout);
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print_fpu_flags (status);
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}
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static void
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arm_othernames ()
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{
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static int toggle;
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static char *original[] = ORIGINAL_REGISTER_NAMES;
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static char *extra_crispy[] = ADDITIONAL_REGISTER_NAMES;
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memcpy (reg_names, toggle ? extra_crispy : original, sizeof(original));
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toggle = !toggle;
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}
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/* FIXME: Fill in with the 'right thing', see asm
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template in arm-convert.s */
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void
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convert_from_extended (ptr, dbl)
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void *ptr;
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double *dbl;
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{
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*dbl = *(double*)ptr;
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}
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void
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convert_to_extended (dbl, ptr)
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void *ptr;
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double *dbl;
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{
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*(double*)ptr = *dbl;
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}
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int
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arm_nullified_insn (inst)
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unsigned long inst;
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{
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unsigned long cond = inst & 0xf0000000;
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unsigned long status_reg;
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if (cond == INST_AL || cond == INST_NV)
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return 0;
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status_reg = read_register (PS_REGNUM);
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switch (cond)
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{
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case INST_EQ:
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return ((status_reg & FLAG_Z) == 0);
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case INST_NE:
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return ((status_reg & FLAG_Z) != 0);
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case INST_CS:
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return ((status_reg & FLAG_C) == 0);
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case INST_CC:
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return ((status_reg & FLAG_C) != 0);
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case INST_MI:
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return ((status_reg & FLAG_N) == 0);
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case INST_PL:
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return ((status_reg & FLAG_N) != 0);
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case INST_VS:
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return ((status_reg & FLAG_V) == 0);
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case INST_VC:
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return ((status_reg & FLAG_V) != 0);
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case INST_HI:
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return ((status_reg & (FLAG_C | FLAG_Z)) != FLAG_C);
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case INST_LS:
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return (((status_reg & (FLAG_C | FLAG_Z)) ^ FLAG_C) == 0);
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case INST_GE:
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return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0));
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case INST_LT:
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return (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0));
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case INST_GT:
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return (((status_reg & FLAG_Z) != 0) ||
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(((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0)));
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case INST_LE:
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return (((status_reg & FLAG_Z) == 0) &&
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(((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0)));
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}
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return 0;
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}
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#define submask(x) ((1L << ((x) + 1)) - 1)
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#define bit(obj,st) (((obj) & (1L << (st))) >> st)
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#define bits(obj,st,fn) \
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(((obj) & submask (fn) & ~ submask ((st) - 1)) >> (st))
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#define sbits(obj,st,fn) \
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((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
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#define BranchDest(addr,instr) \
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((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
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#define ARM_PC_32 1
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static unsigned long
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shifted_reg_val (inst, carry, pc_val)
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unsigned long inst;
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int carry;
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unsigned long pc_val;
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{
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unsigned long res, shift;
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int rm = bits (inst, 0, 3);
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unsigned long shifttype = bits (inst, 5, 6);
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if (bit(inst, 4))
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{
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int rs = bits (inst, 8, 11);
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shift = (rs == 15 ? pc_val + 8 : read_register (rs)) & 0xFF;
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}
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else
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shift = bits (inst, 7, 11);
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res = (rm == 15
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? ((pc_val | (ARM_PC_32 ? 0 : read_register (PS_REGNUM)))
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+ (bit (inst, 4) ? 12 : 8))
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: read_register (rm));
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switch (shifttype)
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{
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case 0: /* LSL */
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res = shift >= 32 ? 0 : res << shift;
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break;
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case 1: /* LSR */
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res = shift >= 32 ? 0 : res >> shift;
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break;
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case 2: /* ASR */
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if (shift >= 32) shift = 31;
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res = ((res & 0x80000000L)
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? ~((~res) >> shift) : res >> shift);
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break;
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case 3: /* ROR/RRX */
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shift &= 31;
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if (shift == 0)
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res = (res >> 1) | (carry ? 0x80000000L : 0);
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else
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res = (res >> shift) | (res << (32-shift));
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break;
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}
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return res & 0xffffffff;
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}
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CORE_ADDR
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arm_get_next_pc (pc)
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CORE_ADDR pc;
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{
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unsigned long pc_val = (unsigned long) pc;
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unsigned long this_instr = read_memory_integer (pc, 4);
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unsigned long status = read_register (PS_REGNUM);
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CORE_ADDR nextpc = (CORE_ADDR) (pc_val + 4); /* Default case */
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if (! arm_nullified_insn (this_instr))
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{
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switch (bits(this_instr, 24, 27))
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{
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case 0x0: case 0x1: /* data processing */
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case 0x2: case 0x3:
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{
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unsigned long operand1, operand2, result = 0;
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unsigned long rn;
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int c;
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if (bits(this_instr, 12, 15) != 15)
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break;
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if (bits (this_instr, 22, 25) == 0
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&& bits (this_instr, 4, 7) == 9) /* multiply */
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error ("Illegal update to pc in instruction");
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/* Multiply into PC */
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c = (status & FLAG_C) ? 1 : 0;
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rn = bits (this_instr, 16, 19);
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operand1 = (rn == 15) ? pc_val + 8 : read_register (rn);
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if (bit (this_instr, 25))
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{
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unsigned long immval = bits (this_instr, 0, 7);
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unsigned long rotate = 2 * bits (this_instr, 8, 11);
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operand2 = ((immval >> rotate) | (immval << (32-rotate))
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& 0xffffffff);
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}
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else /* operand 2 is a shifted register */
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operand2 = shifted_reg_val (this_instr, c, pc_val);
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switch (bits (this_instr, 21, 24))
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{
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case 0x0: /*and*/
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result = operand1 & operand2;
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break;
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case 0x1: /*eor*/
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result = operand1 ^ operand2;
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break;
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case 0x2: /*sub*/
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result = operand1 - operand2;
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break;
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case 0x3: /*rsb*/
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result = operand2 - operand1;
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break;
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case 0x4: /*add*/
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result = operand1 + operand2;
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break;
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case 0x5: /*adc*/
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result = operand1 + operand2 + c;
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break;
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case 0x6: /*sbc*/
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result = operand1 - operand2 + c;
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break;
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case 0x7: /*rsc*/
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result = operand2 - operand1 + c;
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break;
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case 0x8: case 0x9: case 0xa: case 0xb: /* tst, teq, cmp, cmn */
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result = (unsigned long) nextpc;
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break;
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case 0xc: /*orr*/
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result = operand1 | operand2;
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break;
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case 0xd: /*mov*/
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/* Always step into a function. */
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result = operand2;
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break;
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case 0xe: /*bic*/
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result = operand1 & ~operand2;
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break;
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case 0xf: /*mvn*/
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result = ~operand2;
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break;
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}
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nextpc = (CORE_ADDR) ADDR_BITS_REMOVE (result);
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if (nextpc == pc)
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error ("Infinite loop detected");
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break;
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}
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case 0x4: case 0x5: /* data transfer */
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case 0x6: case 0x7:
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if (bit (this_instr, 20))
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{
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/* load */
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if (bits (this_instr, 12, 15) == 15)
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{
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/* rd == pc */
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unsigned long rn;
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unsigned long base;
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if (bit (this_instr, 22))
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error ("Illegal update to pc in instruction");
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/* byte write to PC */
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rn = bits (this_instr, 16, 19);
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base = (rn == 15) ? pc_val + 8 : read_register (rn);
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if (bit (this_instr, 24))
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{
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/* pre-indexed */
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int c = (status & FLAG_C) ? 1 : 0;
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unsigned long offset =
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(bit (this_instr, 25)
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? shifted_reg_val (this_instr, c, pc_val)
|
|
: bits (this_instr, 0, 11));
|
|
|
|
if (bit (this_instr, 23))
|
|
base += offset;
|
|
else
|
|
base -= offset;
|
|
}
|
|
nextpc = (CORE_ADDR) read_memory_integer ((CORE_ADDR) base,
|
|
4);
|
|
|
|
nextpc = ADDR_BITS_REMOVE (nextpc);
|
|
|
|
if (nextpc == pc)
|
|
error ("Infinite loop detected");
|
|
}
|
|
}
|
|
break;
|
|
|
|
case 0x8: case 0x9: /* block transfer */
|
|
if (bit (this_instr, 20))
|
|
{
|
|
/* LDM */
|
|
if (bit (this_instr, 15))
|
|
{
|
|
/* loading pc */
|
|
int offset = 0;
|
|
|
|
if (bit (this_instr, 23))
|
|
{
|
|
/* up */
|
|
unsigned long reglist = bits (this_instr, 0, 14);
|
|
unsigned long regbit;
|
|
|
|
for (; reglist != 0; reglist &= ~regbit)
|
|
{
|
|
regbit = reglist & (-reglist);
|
|
offset += 4;
|
|
}
|
|
|
|
if (bit (this_instr, 24)) /* pre */
|
|
offset += 4;
|
|
}
|
|
else if (bit (this_instr, 24))
|
|
offset = -4;
|
|
|
|
{
|
|
unsigned long rn_val =
|
|
read_register (bits (this_instr, 16, 19));
|
|
nextpc =
|
|
(CORE_ADDR) read_memory_integer ((CORE_ADDR) (rn_val
|
|
+ offset),
|
|
4);
|
|
}
|
|
nextpc = ADDR_BITS_REMOVE (nextpc);
|
|
if (nextpc == pc)
|
|
error ("Infinite loop detected");
|
|
}
|
|
}
|
|
break;
|
|
|
|
case 0xb: /* branch & link */
|
|
case 0xa: /* branch */
|
|
{
|
|
nextpc = BranchDest (pc, this_instr);
|
|
|
|
nextpc = ADDR_BITS_REMOVE (nextpc);
|
|
if (nextpc == pc)
|
|
error ("Infinite loop detected");
|
|
break;
|
|
}
|
|
|
|
case 0xc: case 0xd:
|
|
case 0xe: /* coproc ops */
|
|
case 0xf: /* SWI */
|
|
break;
|
|
|
|
default:
|
|
fprintf (stderr, "Bad bit-field extraction\n");
|
|
return (pc);
|
|
}
|
|
}
|
|
|
|
return nextpc;
|
|
}
|
|
|
|
void
|
|
_initialize_arm_tdep ()
|
|
{
|
|
tm_print_insn = print_insn_little_arm;
|
|
|
|
add_com ("othernames", class_obscure, arm_othernames,
|
|
"Switch to the other set of register names.");
|
|
|
|
add_show_from_set (add_set_cmd ("apcs32", no_class,
|
|
var_integer, (char *)&arm_apcs_32,
|
|
"Set usage of ARM 32-bit mode.\n", &setlist),
|
|
&showlist);
|
|
|
|
}
|