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536 lines
14 KiB
C
536 lines
14 KiB
C
# Simulator main loop for m32r2. -*- C -*-
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#
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# Copyright 1996-2017 Free Software Foundation, Inc.
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#
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# This file is part of GDB, the GNU debugger.
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; either version 3 of the License, or
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# (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program. If not, see <http://www.gnu.org/licenses/>.
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# Syntax:
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# /bin/sh mainloop.in command
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#
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# Command is one of:
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#
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# init
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# support
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# extract-{simple,scache,pbb}
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# {full,fast}-exec-{simple,scache,pbb}
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#
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# A target need only provide a "full" version of one of simple,scache,pbb.
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# If the target wants it can also provide a fast version of same, or if
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# the slow (full featured) version is `simple', then the fast version can be
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# one of scache/pbb.
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# A target can't provide more than this.
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# ??? After a few more ports are done, revisit.
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# Will eventually need to machine generate a lot of this.
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case "x$1" in
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xsupport)
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cat <<EOF
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/* Emit insns to write back the results of insns executed in parallel.
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SC points to a sufficient number of scache entries for the writeback
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handlers.
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SC1/ID1 is the first insn (left slot, lower address).
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SC2/ID2 is the second insn (right slot, higher address). */
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static INLINE void
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emit_par_finish (SIM_CPU *current_cpu, PCADDR pc, SCACHE *sc,
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SCACHE *sc1, const IDESC *id1, SCACHE *sc2, const IDESC *id2)
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{
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ARGBUF *abuf;
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abuf = &sc->argbuf;
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id1 = id1->par_idesc;
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abuf->fields.write.abuf = &sc1->argbuf;
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@cpu@_fill_argbuf (current_cpu, abuf, id1, pc, 0);
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/* no need to set trace_p,profile_p */
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#if 0 /* not currently needed for id2 since results written directly */
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abuf = &sc[1].argbuf;
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id2 = id2->par_idesc;
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abuf->fields.write.abuf = &sc2->argbuf;
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@cpu@_fill_argbuf (current_cpu, abuf, id2, pc + 2, 0);
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/* no need to set trace_p,profile_p */
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#endif
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}
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static INLINE const IDESC *
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emit_16 (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn,
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SCACHE *sc, int fast_p, int parallel_p)
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{
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ARGBUF *abuf = &sc->argbuf;
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const IDESC *id = @cpu@_decode (current_cpu, pc, insn, insn, abuf);
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if (parallel_p)
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id = id->par_idesc;
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@cpu@_fill_argbuf (current_cpu, abuf, id, pc, fast_p);
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return id;
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}
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static INLINE const IDESC *
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emit_full16 (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn, SCACHE *sc,
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int trace_p, int profile_p)
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{
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const IDESC *id;
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@cpu@_emit_before (current_cpu, sc, pc, 1);
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id = emit_16 (current_cpu, pc, insn, sc + 1, 0, 0);
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@cpu@_emit_after (current_cpu, sc + 2, pc);
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sc[1].argbuf.trace_p = trace_p;
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sc[1].argbuf.profile_p = profile_p;
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return id;
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}
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static INLINE const IDESC *
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emit_parallel (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn,
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SCACHE *sc, int fast_p)
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{
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const IDESC *id,*id2;
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/* Emit both insns, then emit a finisher-upper.
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We speed things up by handling the second insn serially
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[not parallelly]. Then the writeback only has to deal
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with the first insn. */
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/* ??? Revisit to handle exceptions right. */
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/* FIXME: No need to handle this parallely if second is nop. */
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id = emit_16 (current_cpu, pc, insn >> 16, sc, fast_p, 1);
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/* Note that this can never be a cti. No cti's go in the S pipeline. */
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id2 = emit_16 (current_cpu, pc + 2, insn & 0x7fff, sc + 1, fast_p, 0);
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/* Set sc/snc insns notion of where to skip to. */
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if (IDESC_SKIP_P (id))
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SEM_SKIP_COMPILE (current_cpu, sc, 1);
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/* Emit code to finish executing the semantics
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(write back the results). */
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emit_par_finish (current_cpu, pc, sc + 2, sc, id, sc + 1, id2);
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return id;
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}
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static INLINE const IDESC *
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emit_full_parallel (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn,
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SCACHE *sc, int trace_p, int profile_p)
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{
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const IDESC *id,*id2;
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/* Emit both insns, then emit a finisher-upper.
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We speed things up by handling the second insn serially
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[not parallelly]. Then the writeback only has to deal
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with the first insn. */
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/* ??? Revisit to handle exceptions right. */
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@cpu@_emit_before (current_cpu, sc, pc, 1);
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/* FIXME: No need to handle this parallelly if second is nop. */
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id = emit_16 (current_cpu, pc, insn >> 16, sc + 1, 0, 1);
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sc[1].argbuf.trace_p = trace_p;
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sc[1].argbuf.profile_p = profile_p;
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@cpu@_emit_before (current_cpu, sc + 2, pc, 0);
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/* Note that this can never be a cti. No cti's go in the S pipeline. */
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id2 = emit_16 (current_cpu, pc + 2, insn & 0x7fff, sc + 3, 0, 0);
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sc[3].argbuf.trace_p = trace_p;
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sc[3].argbuf.profile_p = profile_p;
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/* Set sc/snc insns notion of where to skip to. */
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if (IDESC_SKIP_P (id))
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SEM_SKIP_COMPILE (current_cpu, sc, 4);
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/* Emit code to finish executing the semantics
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(write back the results). */
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emit_par_finish (current_cpu, pc, sc + 4, sc + 1, id, sc + 3, id2);
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@cpu@_emit_after (current_cpu, sc + 5, pc);
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return id;
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}
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static INLINE const IDESC *
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emit_32 (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn,
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SCACHE *sc, int fast_p)
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{
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ARGBUF *abuf = &sc->argbuf;
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const IDESC *id = @cpu@_decode (current_cpu, pc,
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(USI) insn >> 16, insn, abuf);
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@cpu@_fill_argbuf (current_cpu, abuf, id, pc, fast_p);
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return id;
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}
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static INLINE const IDESC *
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emit_full32 (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn, SCACHE *sc,
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int trace_p, int profile_p)
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{
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const IDESC *id;
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@cpu@_emit_before (current_cpu, sc, pc, 1);
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id = emit_32 (current_cpu, pc, insn, sc + 1, 0);
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@cpu@_emit_after (current_cpu, sc + 2, pc);
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sc[1].argbuf.trace_p = trace_p;
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sc[1].argbuf.profile_p = profile_p;
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return id;
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}
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EOF
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;;
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xinit)
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# Nothing needed.
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;;
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xextract-pbb)
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# Inputs: current_cpu, pc, sc, max_insns, FAST_P
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# Outputs: sc, pc
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# sc must be left pointing past the last created entry.
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# pc must be left pointing past the last created entry.
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# If the pbb is terminated by a cti insn, SET_CTI_VPC(sc) must be called
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# to record the vpc of the cti insn.
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# SET_INSN_COUNT(n) must be called to record number of real insns.
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cat <<EOF
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{
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const IDESC *idesc;
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int icount = 0;
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if ((pc & 3) != 0)
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{
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/* This occurs when single stepping and when compiling the not-taken
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part of conditional branches. */
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UHI insn = GETIMEMUHI (current_cpu, pc);
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int trace_p = PC_IN_TRACE_RANGE_P (current_cpu, pc);
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int profile_p = PC_IN_PROFILE_RANGE_P (current_cpu, pc);
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SCACHE *cti_sc; /* ??? tmp hack */
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/* A parallel insn isn't allowed here, but we don't mind nops.
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??? We need to wait until the insn is executed before signalling
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the error, for situations where such signalling is wanted. */
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#if 0
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if ((insn & 0x8000) != 0
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&& (insn & 0x7fff) != 0x7000) /* parallel nops are ok */
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sim_engine_invalid_insn (current_cpu, pc, 0);
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#endif
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/* Only emit before/after handlers if necessary. */
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if (FAST_P || (! trace_p && ! profile_p))
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{
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idesc = emit_16 (current_cpu, pc, insn & 0x7fff, sc, FAST_P, 0);
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cti_sc = sc;
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++sc;
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--max_insns;
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}
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else
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{
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idesc = emit_full16 (current_cpu, pc, insn & 0x7fff, sc,
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trace_p, profile_p);
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cti_sc = sc + 1;
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sc += 3;
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max_insns -= 3;
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}
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++icount;
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pc += 2;
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if (IDESC_CTI_P (idesc))
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{
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SET_CTI_VPC (cti_sc);
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goto Finish;
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}
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}
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/* There are two copies of the compiler: full(!fast) and fast.
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The "full" case emits before/after handlers for each insn.
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Having two copies of this code is a tradeoff, having one copy
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seemed a bit more difficult to read (due to constantly testing
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FAST_P). ??? On the other hand, with address ranges we'll want to
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omit before/after handlers for unwanted insns. Having separate loops
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for FAST/!FAST avoids constantly doing the test in the loop, but
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typically FAST_P is a constant and such tests will get optimized out. */
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if (FAST_P)
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{
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while (max_insns > 0)
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{
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USI insn = GETIMEMUSI (current_cpu, pc);
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if ((SI) insn < 0)
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{
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/* 32 bit insn */
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idesc = emit_32 (current_cpu, pc, insn, sc, 1);
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++sc;
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--max_insns;
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++icount;
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pc += 4;
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if (IDESC_CTI_P (idesc))
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{
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SET_CTI_VPC (sc - 1);
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break;
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}
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}
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else
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{
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if ((insn & 0x8000) != 0) /* parallel? */
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{
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int up_count;
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if (((insn >> 16) & 0xfff0) == 0x10f0)
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{
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/* FIXME: No need to handle this sequentially if system
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calls will be able to execute after second insn in
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parallel. ( trap #num || insn ) */
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/* insn */
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idesc = emit_16 (current_cpu, pc + 2, insn & 0x7fff,
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sc, 1, 0);
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/* trap */
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emit_16 (current_cpu, pc, insn >> 16, sc + 1, 1, 0);
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up_count = 2;
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}
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else
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{
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/* Yep. Here's the "interesting" [sic] part. */
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idesc = emit_parallel (current_cpu, pc, insn, sc, 1);
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up_count = 3;
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}
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sc += up_count;
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max_insns -= up_count;
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icount += 2;
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pc += 4;
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if (IDESC_CTI_P (idesc))
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{
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SET_CTI_VPC (sc - up_count);
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break;
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}
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}
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else /* 2 serial 16 bit insns */
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{
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idesc = emit_16 (current_cpu, pc, insn >> 16, sc, 1, 0);
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++sc;
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--max_insns;
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++icount;
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pc += 2;
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if (IDESC_CTI_P (idesc))
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{
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SET_CTI_VPC (sc - 1);
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break;
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}
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/* While we're guaranteed that there's room to extract the
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insn, when single stepping we can't; the pbb must stop
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after the first insn. */
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if (max_insns == 0)
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break;
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idesc = emit_16 (current_cpu, pc, insn & 0x7fff, sc, 1, 0);
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++sc;
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--max_insns;
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++icount;
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pc += 2;
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if (IDESC_CTI_P (idesc))
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{
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SET_CTI_VPC (sc - 1);
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break;
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}
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}
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}
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}
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}
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else /* ! FAST_P */
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{
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while (max_insns > 0)
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{
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USI insn = GETIMEMUSI (current_cpu, pc);
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int trace_p = PC_IN_TRACE_RANGE_P (current_cpu, pc);
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int profile_p = PC_IN_PROFILE_RANGE_P (current_cpu, pc);
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SCACHE *cti_sc; /* ??? tmp hack */
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if ((SI) insn < 0)
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{
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/* 32 bit insn
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Only emit before/after handlers if necessary. */
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if (trace_p || profile_p)
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{
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idesc = emit_full32 (current_cpu, pc, insn, sc,
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trace_p, profile_p);
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cti_sc = sc + 1;
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sc += 3;
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max_insns -= 3;
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}
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else
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{
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idesc = emit_32 (current_cpu, pc, insn, sc, 0);
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cti_sc = sc;
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++sc;
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--max_insns;
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}
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++icount;
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pc += 4;
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if (IDESC_CTI_P (idesc))
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{
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SET_CTI_VPC (cti_sc);
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break;
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}
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}
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else
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{
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if ((insn & 0x8000) != 0) /* parallel? */
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{
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/* Yep. Here's the "interesting" [sic] part.
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Only emit before/after handlers if necessary. */
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if (trace_p || profile_p)
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{
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if (((insn >> 16) & 0xfff0) == 0x10f0)
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{
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/* FIXME: No need to handle this sequentially if
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system calls will be able to execute after second
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insn in parallel. ( trap #num || insn ) */
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/* insn */
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idesc = emit_full16 (current_cpu, pc + 2,
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insn & 0x7fff, sc, 0, 0);
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/* trap */
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emit_full16 (current_cpu, pc, insn >> 16, sc + 3,
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0, 0);
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}
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else
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{
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idesc = emit_full_parallel (current_cpu, pc, insn,
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sc, trace_p, profile_p);
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}
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cti_sc = sc + 1;
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sc += 6;
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max_insns -= 6;
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}
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else
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{
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int up_count;
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if (((insn >> 16) & 0xfff0) == 0x10f0)
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{
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/* FIXME: No need to handle this sequentially if
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system calls will be able to execute after second
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insn in parallel. ( trap #num || insn ) */
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/* insn */
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idesc = emit_16 (current_cpu, pc + 2, insn & 0x7fff,
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sc, 0, 0);
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/* trap */
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emit_16 (current_cpu, pc, insn >> 16, sc + 1, 0, 0);
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up_count = 2;
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}
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else
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{
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idesc = emit_parallel (current_cpu, pc, insn, sc, 0);
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up_count = 3;
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}
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cti_sc = sc;
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sc += up_count;
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max_insns -= up_count;
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}
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icount += 2;
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pc += 4;
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if (IDESC_CTI_P (idesc))
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{
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SET_CTI_VPC (cti_sc);
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break;
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}
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}
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else /* 2 serial 16 bit insns */
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{
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/* Only emit before/after handlers if necessary. */
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if (trace_p || profile_p)
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{
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idesc = emit_full16 (current_cpu, pc, insn >> 16, sc,
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trace_p, profile_p);
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cti_sc = sc + 1;
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sc += 3;
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max_insns -= 3;
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}
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else
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{
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idesc = emit_16 (current_cpu, pc, insn >> 16, sc, 0, 0);
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cti_sc = sc;
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++sc;
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--max_insns;
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}
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++icount;
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pc += 2;
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if (IDESC_CTI_P (idesc))
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{
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SET_CTI_VPC (cti_sc);
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break;
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}
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/* While we're guaranteed that there's room to extract the
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insn, when single stepping we can't; the pbb must stop
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after the first insn. */
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if (max_insns <= 0)
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break;
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/* Use the same trace/profile address for the 2nd insn.
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Saves us having to compute it and they come in pairs
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anyway (e.g. can never branch to the 2nd insn). */
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if (trace_p || profile_p)
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{
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idesc = emit_full16 (current_cpu, pc, insn & 0x7fff, sc,
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trace_p, profile_p);
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cti_sc = sc + 1;
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sc += 3;
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max_insns -= 3;
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}
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else
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{
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idesc = emit_16 (current_cpu, pc, insn & 0x7fff, sc, 0, 0);
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|
cti_sc = sc;
|
|
++sc;
|
|
--max_insns;
|
|
}
|
|
++icount;
|
|
pc += 2;
|
|
if (IDESC_CTI_P (idesc))
|
|
{
|
|
SET_CTI_VPC (cti_sc);
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
Finish:
|
|
SET_INSN_COUNT (icount);
|
|
}
|
|
EOF
|
|
|
|
;;
|
|
|
|
xfull-exec-pbb)
|
|
|
|
# Inputs: current_cpu, vpc, FAST_P
|
|
# Outputs: vpc
|
|
# vpc is the virtual program counter.
|
|
|
|
cat <<EOF
|
|
#define DEFINE_SWITCH
|
|
#include "sem2-switch.c"
|
|
EOF
|
|
|
|
;;
|
|
|
|
*)
|
|
echo "Invalid argument to mainloop.in: $1" >&2
|
|
exit 1
|
|
;;
|
|
|
|
esac
|