mirror of
https://github.com/darlinghq/darling-gdb.git
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a685700c57
control the translation. (m68hc11tim_print_timer): Update cycle_to_string conversion. (m68hc11tim_timer_event): Fix handling of output compare register with its interrupts. (m68hc11tim_io_write_buffer): Check output compare after setting M6811_TMSK1. (m68hc11tim_io_read_buffer): Fix compilation warning. * dv-m68hc11.c (m68hc11_option_handler): Likewise. * dv-m68hc11spi.c (m68hc11spi_info): Likewise. * dv-m68hc11sio.c (m68hc11sio_info): Likewise. * interrupts.c (interrupts_info): Likewise. (interrupts_reset): Recognize bootstrap mode. * sim-main.h (PRINT_CYCLE, PRINT_TIME): New defines. (_sim_cpu): Add cpu_start_mode. (cycle_to_string): Add flags member. * m68hc11_sim.c (OPTION_CPU_BOOTSTRAP): New option. (cpu_options): Declare new option bootstrap. (cpu_option_handler): Handle it. (cpu_info): Update call to cycle_to_string.
537 lines
13 KiB
C
537 lines
13 KiB
C
/* dv-m68hc11spi.c -- Simulation of the 68HC11 SPI
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Copyright (C) 2000, 2002, 2003 Free Software Foundation, Inc.
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Written by Stephane Carrez (stcarrez@nerim.fr)
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(From a driver model Contributed by Cygnus Solutions.)
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This file is part of the program GDB, the GNU debugger.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#include "sim-main.h"
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#include "hw-main.h"
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#include "dv-sockser.h"
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#include "sim-assert.h"
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/* DEVICE
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m68hc11spi - m68hc11 SPI interface
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DESCRIPTION
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Implements the m68hc11 Synchronous Serial Peripheral Interface
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described in the m68hc11 user guide (Chapter 8 in pink book).
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The SPI I/O controller is directly connected to the CPU
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interrupt. The simulator implements:
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- SPI clock emulation
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- Data transfer
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- Write collision detection
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PROPERTIES
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None
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PORTS
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reset (input)
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Reset port. This port is only used to simulate a reset of the SPI
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I/O controller. It should be connected to the RESET output of the cpu.
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*/
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/* port ID's */
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enum
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{
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RESET_PORT
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};
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static const struct hw_port_descriptor m68hc11spi_ports[] =
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{
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{ "reset", RESET_PORT, 0, input_port, },
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{ NULL, },
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};
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/* SPI */
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struct m68hc11spi
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{
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/* Information about next character to be transmited. */
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unsigned char tx_char;
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int tx_bit;
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unsigned char mode;
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unsigned char rx_char;
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unsigned char rx_clear_scsr;
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unsigned char clk_pin;
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/* SPI clock rate (twice the real clock). */
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unsigned int clock;
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/* Periodic SPI event. */
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struct hw_event* spi_event;
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};
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/* Finish off the partially created hw device. Attach our local
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callbacks. Wire up our port names etc */
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static hw_io_read_buffer_method m68hc11spi_io_read_buffer;
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static hw_io_write_buffer_method m68hc11spi_io_write_buffer;
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static hw_port_event_method m68hc11spi_port_event;
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static hw_ioctl_method m68hc11spi_ioctl;
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#define M6811_SPI_FIRST_REG (M6811_SPCR)
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#define M6811_SPI_LAST_REG (M6811_SPDR)
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static void
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attach_m68hc11spi_regs (struct hw *me,
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struct m68hc11spi *controller)
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{
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hw_attach_address (hw_parent (me), M6811_IO_LEVEL, io_map,
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M6811_SPI_FIRST_REG,
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M6811_SPI_LAST_REG - M6811_SPI_FIRST_REG + 1,
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me);
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}
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static void
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m68hc11spi_finish (struct hw *me)
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{
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struct m68hc11spi *controller;
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controller = HW_ZALLOC (me, struct m68hc11spi);
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set_hw_data (me, controller);
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set_hw_io_read_buffer (me, m68hc11spi_io_read_buffer);
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set_hw_io_write_buffer (me, m68hc11spi_io_write_buffer);
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set_hw_ports (me, m68hc11spi_ports);
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set_hw_port_event (me, m68hc11spi_port_event);
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#ifdef set_hw_ioctl
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set_hw_ioctl (me, m68hc11spi_ioctl);
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#else
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me->to_ioctl = m68hc11spi_ioctl;
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#endif
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/* Attach ourself to our parent bus. */
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attach_m68hc11spi_regs (me, controller);
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/* Initialize to reset state. */
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controller->spi_event = NULL;
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controller->rx_clear_scsr = 0;
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}
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/* An event arrives on an interrupt port */
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static void
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m68hc11spi_port_event (struct hw *me,
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int my_port,
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struct hw *source,
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int source_port,
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int level)
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{
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SIM_DESC sd;
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struct m68hc11spi *controller;
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sim_cpu* cpu;
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unsigned8 val;
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controller = hw_data (me);
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sd = hw_system (me);
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cpu = STATE_CPU (sd, 0);
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switch (my_port)
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{
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case RESET_PORT:
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{
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HW_TRACE ((me, "SPI reset"));
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/* Reset the state of SPI registers. */
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controller->rx_clear_scsr = 0;
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if (controller->spi_event)
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{
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hw_event_queue_deschedule (me, controller->spi_event);
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controller->spi_event = 0;
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}
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val = 0;
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m68hc11spi_io_write_buffer (me, &val, io_map,
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(unsigned_word) M6811_SPCR, 1);
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break;
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}
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default:
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hw_abort (me, "Event on unknown port %d", my_port);
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break;
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}
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}
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static void
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set_bit_port (struct hw *me, sim_cpu *cpu, int port, int mask, int value)
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{
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uint8 val;
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if (value)
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val = cpu->ios[port] | mask;
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else
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val = cpu->ios[port] & ~mask;
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/* Set the new value and post an event to inform other devices
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that pin 'port' changed. */
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m68hc11cpu_set_port (me, cpu, port, val);
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}
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/* When a character is sent/received by the SPI, the PD2..PD5 line
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are driven by the following signals:
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B7 B6
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-----+---------+--------+---/-+-------
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MOSI | | | | | |
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MISO +---------+--------+---/-+
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____ ___
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CLK _______/ \____/ \__ CPOL=0, CPHA=0
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_______ ____ __
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\____/ \___/ CPOL=1, CPHA=0
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____ ____ __
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__/ \____/ \___/ CPOL=0, CPHA=1
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__ ____ ___
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\____/ \____/ \__ CPOL=1, CPHA=1
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SS ___ ____
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\__________________________//___/
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MISO = PD2
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MOSI = PD3
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SCK = PD4
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SS = PD5
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*/
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#define SPI_START_BYTE 0
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#define SPI_START_BIT 1
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#define SPI_MIDDLE_BIT 2
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void
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m68hc11spi_clock (struct hw *me, void *data)
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{
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SIM_DESC sd;
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struct m68hc11spi* controller;
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sim_cpu *cpu;
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int check_interrupt = 0;
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controller = hw_data (me);
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sd = hw_system (me);
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cpu = STATE_CPU (sd, 0);
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/* Cleanup current event. */
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if (controller->spi_event)
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{
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hw_event_queue_deschedule (me, controller->spi_event);
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controller->spi_event = 0;
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}
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/* Change a bit of data at each two SPI event. */
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if (controller->mode == SPI_START_BIT)
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{
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/* Reflect the bit value on bit 2 of port D. */
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set_bit_port (me, cpu, M6811_PORTD, (1 << 2),
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(controller->tx_char & (1 << controller->tx_bit)));
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controller->tx_bit--;
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controller->mode = SPI_MIDDLE_BIT;
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}
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else if (controller->mode == SPI_MIDDLE_BIT)
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{
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controller->mode = SPI_START_BIT;
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}
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if (controller->mode == SPI_START_BYTE)
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{
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/* Start a new SPI transfer. */
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/* TBD: clear SS output. */
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controller->mode = SPI_START_BIT;
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controller->tx_bit = 7;
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set_bit_port (me, cpu, M6811_PORTD, (1 << 4), ~controller->clk_pin);
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}
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else
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{
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/* Change the SPI clock at each event on bit 4 of port D. */
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controller->clk_pin = ~controller->clk_pin;
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set_bit_port (me, cpu, M6811_PORTD, (1 << 4), controller->clk_pin);
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}
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/* Transmit is now complete for this byte. */
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if (controller->mode == SPI_START_BIT && controller->tx_bit < 0)
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{
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controller->rx_clear_scsr = 0;
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cpu->ios[M6811_SPSR] |= M6811_SPIF;
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if (cpu->ios[M6811_SPCR] & M6811_SPIE)
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check_interrupt = 1;
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}
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else
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{
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controller->spi_event = hw_event_queue_schedule (me, controller->clock,
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m68hc11spi_clock,
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NULL);
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}
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if (check_interrupt)
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interrupts_update_pending (&cpu->cpu_interrupts);
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}
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/* Flags of the SPCR register. */
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io_reg_desc spcr_desc[] = {
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{ M6811_SPIE, "SPIE ", "Serial Peripheral Interrupt Enable" },
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{ M6811_SPE, "SPE ", "Serial Peripheral System Enable" },
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{ M6811_DWOM, "DWOM ", "Port D Wire-OR mode option" },
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{ M6811_MSTR, "MSTR ", "Master Mode Select" },
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{ M6811_CPOL, "CPOL ", "Clock Polarity" },
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{ M6811_CPHA, "CPHA ", "Clock Phase" },
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{ M6811_SPR1, "SPR1 ", "SPI Clock Rate Select" },
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{ M6811_SPR0, "SPR0 ", "SPI Clock Rate Select" },
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{ 0, 0, 0 }
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};
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/* Flags of the SPSR register. */
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io_reg_desc spsr_desc[] = {
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{ M6811_SPIF, "SPIF ", "SPI Transfer Complete flag" },
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{ M6811_WCOL, "WCOL ", "Write Collision" },
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{ M6811_MODF, "MODF ", "Mode Fault" },
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{ 0, 0, 0 }
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};
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static void
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m68hc11spi_info (struct hw *me)
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{
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SIM_DESC sd;
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uint16 base = 0;
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sim_cpu *cpu;
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struct m68hc11spi *controller;
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uint8 val;
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sd = hw_system (me);
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cpu = STATE_CPU (sd, 0);
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controller = hw_data (me);
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sim_io_printf (sd, "M68HC11 SPI:\n");
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base = cpu_get_io_base (cpu);
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val = cpu->ios[M6811_SPCR];
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print_io_byte (sd, "SPCR", spcr_desc, val, base + M6811_SPCR);
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sim_io_printf (sd, "\n");
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val = cpu->ios[M6811_SPSR];
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print_io_byte (sd, "SPSR", spsr_desc, val, base + M6811_SPSR);
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sim_io_printf (sd, "\n");
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if (controller->spi_event)
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{
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signed64 t;
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sim_io_printf (sd, " SPI has %d bits to send\n",
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controller->tx_bit + 1);
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t = hw_event_remain_time (me, controller->spi_event);
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sim_io_printf (sd, " SPI current bit-cycle finished in %s\n",
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cycle_to_string (cpu, t, PRINT_TIME | PRINT_CYCLE));
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t += (controller->tx_bit + 1) * 2 * controller->clock;
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sim_io_printf (sd, " SPI operation finished in %s\n",
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cycle_to_string (cpu, t, PRINT_TIME | PRINT_CYCLE));
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}
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}
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static int
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m68hc11spi_ioctl (struct hw *me,
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hw_ioctl_request request,
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va_list ap)
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{
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m68hc11spi_info (me);
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return 0;
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}
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/* generic read/write */
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static unsigned
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m68hc11spi_io_read_buffer (struct hw *me,
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void *dest,
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int space,
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unsigned_word base,
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unsigned nr_bytes)
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{
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SIM_DESC sd;
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struct m68hc11spi *controller;
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sim_cpu *cpu;
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unsigned8 val;
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HW_TRACE ((me, "read 0x%08lx %d", (long) base, (int) nr_bytes));
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sd = hw_system (me);
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cpu = STATE_CPU (sd, 0);
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controller = hw_data (me);
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switch (base)
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{
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case M6811_SPSR:
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controller->rx_clear_scsr = cpu->ios[M6811_SCSR]
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& (M6811_SPIF | M6811_WCOL | M6811_MODF);
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case M6811_SPCR:
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val = cpu->ios[base];
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break;
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case M6811_SPDR:
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if (controller->rx_clear_scsr)
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{
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cpu->ios[M6811_SPSR] &= ~controller->rx_clear_scsr;
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controller->rx_clear_scsr = 0;
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interrupts_update_pending (&cpu->cpu_interrupts);
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}
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val = controller->rx_char;
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break;
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default:
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return 0;
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}
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*((unsigned8*) dest) = val;
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return 1;
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}
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static unsigned
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m68hc11spi_io_write_buffer (struct hw *me,
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const void *source,
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int space,
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unsigned_word base,
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unsigned nr_bytes)
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{
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SIM_DESC sd;
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struct m68hc11spi *controller;
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sim_cpu *cpu;
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unsigned8 val;
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HW_TRACE ((me, "write 0x%08lx %d", (long) base, (int) nr_bytes));
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sd = hw_system (me);
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cpu = STATE_CPU (sd, 0);
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controller = hw_data (me);
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val = *((const unsigned8*) source);
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switch (base)
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{
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case M6811_SPCR:
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cpu->ios[M6811_SPCR] = val;
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/* The SPI clock rate is 2, 4, 16, 32 of the internal CPU clock.
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We have to drive the clock pin and need a 2x faster clock. */
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switch (val & (M6811_SPR1 | M6811_SPR0))
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{
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case 0:
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controller->clock = 1;
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break;
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case 1:
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controller->clock = 2;
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break;
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case 2:
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controller->clock = 8;
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break;
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default:
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controller->clock = 16;
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break;
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}
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/* Set the clock pin. */
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if ((val & M6811_CPOL)
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&& (controller->spi_event == 0
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|| ((val & M6811_CPHA) && controller->mode == 1)))
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controller->clk_pin = 1;
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else
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controller->clk_pin = 0;
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set_bit_port (me, cpu, M6811_PORTD, (1 << 4), controller->clk_pin);
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break;
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/* Can't write to SPSR. */
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case M6811_SPSR:
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break;
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case M6811_SPDR:
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if (!(cpu->ios[M6811_SPCR] & M6811_SPE))
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{
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return 0;
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}
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if (controller->rx_clear_scsr)
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{
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cpu->ios[M6811_SPSR] &= ~controller->rx_clear_scsr;
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controller->rx_clear_scsr = 0;
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interrupts_update_pending (&cpu->cpu_interrupts);
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}
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/* If transfer is taking place, a write to SPDR
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generates a collision. */
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if (controller->spi_event)
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{
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cpu->ios[M6811_SPSR] |= M6811_WCOL;
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break;
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}
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/* Refuse the write if there was no read of SPSR. */
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/* ???? TBD. */
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/* Prepare to send a byte. */
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controller->tx_char = val;
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controller->mode = SPI_START_BYTE;
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/* Toggle clock pin internal value when CPHA is 0 so that
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it will really change in the middle of a bit. */
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if (!(cpu->ios[M6811_SPCR] & M6811_CPHA))
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controller->clk_pin = ~controller->clk_pin;
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cpu->ios[M6811_SPDR] = val;
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/* Activate transmission. */
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m68hc11spi_clock (me, NULL);
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break;
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default:
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return 0;
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}
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return nr_bytes;
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}
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const struct hw_descriptor dv_m68hc11spi_descriptor[] = {
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{ "m68hc11spi", m68hc11spi_finish },
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{ "m68hc12spi", m68hc11spi_finish },
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{ NULL },
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};
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