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364 lines
10 KiB
C
364 lines
10 KiB
C
/* Native-dependent code for GDB, for NYU Ultra3 running Sym1 OS.
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Copyright 1988, 1989, 1991, 1992, 1995, 1996, 1999, 2000, 2001
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Free Software Foundation, Inc.
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Contributed by David Wood (wood@nyu.edu) at New York University.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330,
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Boston, MA 02111-1307, USA. */
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#define DEBUG
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#include "defs.h"
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#include "frame.h"
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#include "inferior.h"
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#include "symtab.h"
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#include "value.h"
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#include "regcache.h"
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#include <sys/types.h>
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#include <sys/param.h>
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#include <signal.h>
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#include <sys/ioctl.h>
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#include <fcntl.h>
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#include "gdbcore.h"
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#include <sys/file.h>
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#include "gdb_stat.h"
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static void fetch_core_registers (char *, unsigned, int, CORE_ADDR);
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/* Assumes support for AMD's Binary Compatibility Standard
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for ptrace(). If you define ULTRA3, the ultra3 extensions to
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ptrace() are used allowing the reading of more than one register
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at a time.
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This file assumes KERNEL_DEBUGGING is turned off. This means
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that if the user/gdb tries to read gr64-gr95 or any of the
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protected special registers we silently return -1 (see the
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CANNOT_STORE/FETCH_REGISTER macros). */
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#define ULTRA3
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#if !defined (offsetof)
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#define offsetof(TYPE, MEMBER) ((unsigned long) &((TYPE *)0)->MEMBER)
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#endif
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extern int errno;
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struct ptrace_user pt_struct;
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/* Get all available registers from the inferior. Registers that are
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* defined in REGISTER_NAMES, but not available to the user/gdb are
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* supplied as -1. This may include gr64-gr95 and the protected special
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* purpose registers.
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*/
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void
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fetch_inferior_registers (int regno)
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{
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register int i, j, ret_val = 0;
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char buf[128];
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if (regno != -1)
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{
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fetch_register (regno);
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return;
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}
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/* Global Registers */
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#ifdef ULTRA3
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errno = 0;
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ptrace (PT_READ_STRUCT, inferior_pid,
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(PTRACE_ARG3_TYPE) register_addr (GR96_REGNUM, 0),
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(int) &pt_struct.pt_gr[0], 32 * 4);
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if (errno != 0)
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{
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perror_with_name ("reading global registers");
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ret_val = -1;
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}
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else
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for (regno = GR96_REGNUM, j = 0; j < 32; regno++, j++)
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{
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supply_register (regno, &pt_struct.pt_gr[j]);
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}
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#else
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for (regno = GR96_REGNUM; !ret_val && regno < GR96_REGNUM + 32; regno++)
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fetch_register (regno);
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#endif
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/* Local Registers */
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#ifdef ULTRA3
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errno = 0;
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ptrace (PT_READ_STRUCT, inferior_pid,
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(PTRACE_ARG3_TYPE) register_addr (LR0_REGNUM, 0),
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(int) &pt_struct.pt_lr[0], 128 * 4);
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if (errno != 0)
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{
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perror_with_name ("reading local registers");
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ret_val = -1;
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}
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else
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for (regno = LR0_REGNUM, j = 0; j < 128; regno++, j++)
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{
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supply_register (regno, &pt_struct.pt_lr[j]);
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}
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#else
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for (regno = LR0_REGNUM; !ret_val && regno < LR0_REGNUM + 128; regno++)
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fetch_register (regno);
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#endif
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/* Special Registers */
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fetch_register (GR1_REGNUM);
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fetch_register (CPS_REGNUM);
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fetch_register (PC_REGNUM);
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fetch_register (NPC_REGNUM);
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fetch_register (PC2_REGNUM);
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fetch_register (IPC_REGNUM);
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fetch_register (IPA_REGNUM);
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fetch_register (IPB_REGNUM);
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fetch_register (Q_REGNUM);
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fetch_register (BP_REGNUM);
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fetch_register (FC_REGNUM);
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/* Fake any registers that are in REGISTER_NAMES, but not available to gdb */
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registers_fetched ();
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}
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/* Store our register values back into the inferior.
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* If REGNO is -1, do this for all registers.
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* Otherwise, REGNO specifies which register (so we can save time).
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* NOTE: Assumes AMD's binary compatibility standard.
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*/
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void
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store_inferior_registers (int regno)
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{
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register unsigned int regaddr;
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char buf[80];
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if (regno >= 0)
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{
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if (CANNOT_STORE_REGISTER (regno))
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return;
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regaddr = register_addr (regno, 0);
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errno = 0;
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ptrace (PT_WRITE_U, inferior_pid,
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(PTRACE_ARG3_TYPE) regaddr, read_register (regno));
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if (errno != 0)
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{
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sprintf (buf, "writing register %s (#%d)", REGISTER_NAME (regno), regno);
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perror_with_name (buf);
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}
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}
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else
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{
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#ifdef ULTRA3
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pt_struct.pt_gr1 = read_register (GR1_REGNUM);
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for (regno = GR96_REGNUM; regno < GR96_REGNUM + 32; regno++)
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pt_struct.pt_gr[regno] = read_register (regno);
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for (regno = LR0_REGNUM; regno < LR0_REGNUM + 128; regno++)
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pt_struct.pt_gr[regno] = read_register (regno);
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errno = 0;
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ptrace (PT_WRITE_STRUCT, inferior_pid,
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(PTRACE_ARG3_TYPE) register_addr (GR1_REGNUM, 0),
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(int) &pt_struct.pt_gr1, (1 * 32 * 128) * 4);
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if (errno != 0)
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{
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sprintf (buf, "writing all local/global registers");
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perror_with_name (buf);
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}
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pt_struct.pt_psr = read_register (CPS_REGNUM);
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pt_struct.pt_pc0 = read_register (NPC_REGNUM);
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pt_struct.pt_pc1 = read_register (PC_REGNUM);
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pt_struct.pt_pc2 = read_register (PC2_REGNUM);
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pt_struct.pt_ipc = read_register (IPC_REGNUM);
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pt_struct.pt_ipa = read_register (IPA_REGNUM);
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pt_struct.pt_ipb = read_register (IPB_REGNUM);
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pt_struct.pt_q = read_register (Q_REGNUM);
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pt_struct.pt_bp = read_register (BP_REGNUM);
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pt_struct.pt_fc = read_register (FC_REGNUM);
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errno = 0;
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ptrace (PT_WRITE_STRUCT, inferior_pid,
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(PTRACE_ARG3_TYPE) register_addr (CPS_REGNUM, 0),
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(int) &pt_struct.pt_psr, (10) * 4);
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if (errno != 0)
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{
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sprintf (buf, "writing all special registers");
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perror_with_name (buf);
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return;
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}
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#else
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store_inferior_registers (GR1_REGNUM);
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for (regno = GR96_REGNUM; regno < GR96_REGNUM + 32; regno++)
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store_inferior_registers (regno);
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for (regno = LR0_REGNUM; regno < LR0_REGNUM + 128; regno++)
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store_inferior_registers (regno);
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store_inferior_registers (CPS_REGNUM);
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store_inferior_registers (PC_REGNUM);
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store_inferior_registers (NPC_REGNUM);
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store_inferior_registers (PC2_REGNUM);
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store_inferior_registers (IPC_REGNUM);
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store_inferior_registers (IPA_REGNUM);
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store_inferior_registers (IPB_REGNUM);
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store_inferior_registers (Q_REGNUM);
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store_inferior_registers (BP_REGNUM);
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store_inferior_registers (FC_REGNUM);
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#endif /* ULTRA3 */
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}
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}
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/*
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* Fetch an individual register (and supply it).
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* return 0 on success, -1 on failure.
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* NOTE: Assumes AMD's Binary Compatibility Standard for ptrace().
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*/
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static void
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fetch_register (int regno)
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{
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char buf[128];
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int val;
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if (CANNOT_FETCH_REGISTER (regno))
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{
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val = -1;
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supply_register (regno, &val);
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}
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else
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{
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errno = 0;
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val = ptrace (PT_READ_U, inferior_pid,
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(PTRACE_ARG3_TYPE) register_addr (regno, 0), 0);
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if (errno != 0)
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{
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sprintf (buf, "reading register %s (#%d)", REGISTER_NAME (regno), regno);
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perror_with_name (buf);
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}
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else
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{
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supply_register (regno, &val);
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}
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}
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}
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/*
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* Read AMD's Binary Compatibilty Standard conforming core file.
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* struct ptrace_user is the first thing in the core file
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*
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* CORE_REG_SECT, CORE_REG_SIZE, WHICH, and REG_ADDR are all ignored.
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*/
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static void
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fetch_core_registers (char *core_reg_sect, unsigned core_reg_size,
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int which, CORE_ADDR reg_addr)
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{
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register int regno;
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int val;
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char buf[4];
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for (regno = 0; regno < NUM_REGS; regno++)
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{
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if (!CANNOT_FETCH_REGISTER (regno))
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{
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val = bfd_seek (core_bfd, (file_ptr) register_addr (regno, 0), SEEK_SET);
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if (val < 0 || (val = bfd_read (buf, sizeof buf, 1, core_bfd)) < 0)
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{
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char *buffer = (char *) alloca (strlen (REGISTER_NAME (regno)) + 35);
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strcpy (buffer, "Reading core register ");
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strcat (buffer, REGISTER_NAME (regno));
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perror_with_name (buffer);
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}
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supply_register (regno, buf);
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}
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}
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/* Fake any registers that are in REGISTER_NAMES, but not available to gdb */
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registers_fetched ();
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}
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/*
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* Takes a register number as defined in tm.h via REGISTER_NAMES, and maps
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* it to an offset in a struct ptrace_user defined by AMD's BCS.
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* That is, it defines the mapping between gdb register numbers and items in
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* a struct ptrace_user.
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* A register protection scheme is set up here. If a register not
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* available to the user is specified in 'regno', then an address that
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* will cause ptrace() to fail is returned.
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*/
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CORE_ADDR
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register_addr (int regno, CORE_ADDR blockend)
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{
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if ((regno >= LR0_REGNUM) && (regno < LR0_REGNUM + 128))
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{
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return (offsetof (struct ptrace_user, pt_lr[regno - LR0_REGNUM]));
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}
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else if ((regno >= GR96_REGNUM) && (regno < GR96_REGNUM + 32))
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{
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return (offsetof (struct ptrace_user, pt_gr[regno - GR96_REGNUM]));
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}
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else
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{
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switch (regno)
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{
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case GR1_REGNUM:
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return (offsetof (struct ptrace_user, pt_gr1));
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case CPS_REGNUM:
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return (offsetof (struct ptrace_user, pt_psr));
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case NPC_REGNUM:
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return (offsetof (struct ptrace_user, pt_pc0));
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case PC_REGNUM:
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return (offsetof (struct ptrace_user, pt_pc1));
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case PC2_REGNUM:
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return (offsetof (struct ptrace_user, pt_pc2));
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case IPC_REGNUM:
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return (offsetof (struct ptrace_user, pt_ipc));
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case IPA_REGNUM:
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return (offsetof (struct ptrace_user, pt_ipa));
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case IPB_REGNUM:
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return (offsetof (struct ptrace_user, pt_ipb));
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case Q_REGNUM:
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return (offsetof (struct ptrace_user, pt_q));
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case BP_REGNUM:
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return (offsetof (struct ptrace_user, pt_bp));
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case FC_REGNUM:
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return (offsetof (struct ptrace_user, pt_fc));
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default:
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fprintf_filtered (gdb_stderr, "register_addr():Bad register %s (%d)\n",
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REGISTER_NAME (regno), regno);
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return (0xffffffff); /* Should make ptrace() fail */
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}
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}
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}
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/* Register that we are able to handle ultra3 core file formats.
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FIXME: is this really bfd_target_unknown_flavour? */
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static struct core_fns ultra3_core_fns =
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{
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bfd_target_unknown_flavour, /* core_flavour */
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default_check_format, /* check_format */
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default_core_sniffer, /* core_sniffer */
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fetch_core_registers, /* core_read_registers */
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NULL /* next */
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};
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void
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_initialize_core_ultra3 (void)
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{
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add_core_fns (&ultra3_core_fns);
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}
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