mirror of
https://github.com/darlinghq/darling-gdb.git
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8acc9f485b
Two modifications:
1. The addition of 2013 to the copyright year range for every file;
2. The use of a single year range, instead of potentially multiple
year ranges, as approved by the FSF.
64 lines
2.7 KiB
C
64 lines
2.7 KiB
C
/* Blackfin Direct Memory Access (DMA) Channel model.
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Copyright (C) 2010-2013 Free Software Foundation, Inc.
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Contributed by Analog Devices, Inc.
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This file is part of simulators.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#ifndef DV_BFIN_DMA_H
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#define DV_BFIN_DMA_H
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/* DMA_CONFIG Masks */
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#define DMAEN 0x0001 /* DMA Channel Enable */
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#define WNR 0x0002 /* Channel Direction (W/R*) */
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#define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */
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#define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */
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#define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */
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#define WDSIZE 0x000c /* Transfer Word Size */
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#define DMA2D 0x0010 /* DMA Mode (2D/1D*) */
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#define RESTART 0x0020 /* DMA Buffer Clear */
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#define DI_SEL 0x0040 /* Data Interrupt Timing Select */
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#define DI_EN 0x0080 /* Data Interrupt Enable */
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#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */
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#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */
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#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */
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#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */
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#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */
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#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */
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#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */
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#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */
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#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */
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#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */
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#define NDSIZE 0x0f00 /* Next Descriptor Size */
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#define NDSIZE_SHIFT 8
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#define DMAFLOW 0x7000 /* Flow Control */
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#define DMAFLOW_STOP 0x0000 /* Stop Mode */
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#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */
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#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */
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#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */
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#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */
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/* DMA_IRQ_STATUS Masks */
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#define DMA_DONE 0x0001 /* DMA Completion Interrupt Status */
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#define DMA_ERR 0x0002 /* DMA Error Interrupt Status */
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#define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */
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#define DMA_RUN 0x0008 /* DMA Channel Running Indicator */
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/* DMA_PERIPHERAL_MAP Masks */
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#define CTYPE (1 << 6)
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#endif
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