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fc3c25b9e0
* d10v-opc.c (d10v_predefined_registers, d10v_operands, d10v_opcodes): Split OPERAND_ACC into OPERAND_ACC0 and OPERAND_ACC1. Introduce OPERAND_GPR. * d10v-dis.c (print_operand): Likewise. include/opcode: * d10v.h (OPERAND_ACC): Split into: (OPERAND_ACC0, OPERAND_ACC1) . (OPERAND_GPR): Define. gas/config: * tc-d10v.c (parallel_ok, find_opcode): Split OPERAND_ACC into OPERAND_ACC0 and OPERAND_ACC1. Introduce OPERAND_GPR.
1511 lines
37 KiB
C
1511 lines
37 KiB
C
/* tc-d10v.c -- Assembler code for the Mitsubishi D10V
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Copyright (C) 1996, 1997, 1998 Free Software Foundation.
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This file is part of GAS, the GNU Assembler.
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GAS is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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GAS is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with GAS; see the file COPYING. If not, write to
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the Free Software Foundation, 59 Temple Place - Suite 330,
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Boston, MA 02111-1307, USA. */
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#include <stdio.h>
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#include <ctype.h>
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#include "as.h"
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#include "subsegs.h"
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#include "opcode/d10v.h"
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#include "elf/ppc.h"
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const char comment_chars[] = ";";
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const char line_comment_chars[] = "#";
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const char line_separator_chars[] = "";
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const char *md_shortopts = "O";
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const char EXP_CHARS[] = "eE";
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const char FLT_CHARS[] = "dD";
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int Optimizing = 0;
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#define AT_WORD_P(X) ((X)->X_op == O_right_shift \
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&& (X)->X_op_symbol != NULL \
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&& (X)->X_op_symbol->sy_value.X_op == O_constant \
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&& (X)->X_op_symbol->sy_value.X_add_number == AT_WORD_RIGHT_SHIFT)
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#define AT_WORD_RIGHT_SHIFT 2
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/* fixups */
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#define MAX_INSN_FIXUPS (5)
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struct d10v_fixup
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{
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expressionS exp;
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int operand;
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int pcrel;
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int size;
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bfd_reloc_code_real_type reloc;
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};
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typedef struct _fixups
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{
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int fc;
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struct d10v_fixup fix[MAX_INSN_FIXUPS];
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struct _fixups *next;
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} Fixups;
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static Fixups FixUps[2];
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static Fixups *fixups;
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/* local functions */
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static int reg_name_search PARAMS ((char *name));
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static int register_name PARAMS ((expressionS *expressionP));
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static int check_range PARAMS ((unsigned long num, int bits, int flags));
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static int postfix PARAMS ((char *p));
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static bfd_reloc_code_real_type get_reloc PARAMS ((struct d10v_operand *op));
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static int get_operands PARAMS ((expressionS exp[]));
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static struct d10v_opcode *find_opcode PARAMS ((struct d10v_opcode *opcode, expressionS ops[]));
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static unsigned long build_insn PARAMS ((struct d10v_opcode *opcode, expressionS *opers, unsigned long insn));
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static void write_long PARAMS ((struct d10v_opcode *opcode, unsigned long insn, Fixups *fx));
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static void write_1_short PARAMS ((struct d10v_opcode *opcode, unsigned long insn, Fixups *fx));
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static int write_2_short PARAMS ((struct d10v_opcode *opcode1, unsigned long insn1,
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struct d10v_opcode *opcode2, unsigned long insn2, int exec_type, Fixups *fx));
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static unsigned long do_assemble PARAMS ((char *str, struct d10v_opcode **opcode));
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static unsigned long d10v_insert_operand PARAMS (( unsigned long insn, int op_type,
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offsetT value, int left, fixS *fix));
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static int parallel_ok PARAMS ((struct d10v_opcode *opcode1, unsigned long insn1,
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struct d10v_opcode *opcode2, unsigned long insn2,
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int exec_type));
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struct option md_longopts[] = {
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#define OPTION_NOWARNSWAP (OPTION_MD_BASE)
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{"nowarnswap", no_argument, NULL, OPTION_NOWARNSWAP},
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{NULL, no_argument, NULL, 0}
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};
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size_t md_longopts_size = sizeof(md_longopts);
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static void d10v_dot_word PARAMS ((int));
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/* The target specific pseudo-ops which we support. */
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const pseudo_typeS md_pseudo_table[] =
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{
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{ "word", d10v_dot_word, 2 },
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{ NULL, NULL, 0 }
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};
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/* Opcode hash table. */
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static struct hash_control *d10v_hash;
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/* reg_name_search does a binary search of the d10v_predefined_registers
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array to see if "name" is a valid regiter name. Returns the register
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number from the array on success, or -1 on failure. */
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static int
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reg_name_search (name)
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char *name;
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{
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int middle, low, high;
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int cmp;
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low = 0;
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high = d10v_reg_name_cnt() - 1;
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do
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{
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middle = (low + high) / 2;
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cmp = strcasecmp (name, d10v_predefined_registers[middle].name);
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if (cmp < 0)
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high = middle - 1;
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else if (cmp > 0)
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low = middle + 1;
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else
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return d10v_predefined_registers[middle].value;
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}
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while (low <= high);
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return -1;
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}
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/* register_name() checks the string at input_line_pointer
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to see if it is a valid register name */
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static int
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register_name (expressionP)
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expressionS *expressionP;
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{
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int reg_number;
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char c, *p = input_line_pointer;
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while (*p && *p!='\n' && *p!='\r' && *p !=',' && *p!=' ' && *p!=')')
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p++;
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c = *p;
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if (c)
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*p++ = 0;
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/* look to see if it's in the register table */
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reg_number = reg_name_search (input_line_pointer);
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if (reg_number >= 0)
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{
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expressionP->X_op = O_register;
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/* temporarily store a pointer to the string here */
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expressionP->X_op_symbol = (struct symbol *)input_line_pointer;
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expressionP->X_add_number = reg_number;
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input_line_pointer = p;
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return 1;
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}
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if (c)
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*(p-1) = c;
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return 0;
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}
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static int
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check_range (num, bits, flags)
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unsigned long num;
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int bits;
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int flags;
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{
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long min, max, bit1;
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int retval=0;
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/* don't bother checking 16-bit values */
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if (bits == 16)
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return 0;
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if (flags & OPERAND_SHIFT)
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{
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/* all special shift operands are unsigned */
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/* and <= 16. We allow 0 for now. */
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if (num>16)
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return 1;
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else
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return 0;
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}
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if (flags & OPERAND_SIGNED)
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{
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max = (1 << (bits - 1))-1;
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min = - (1 << (bits - 1));
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if (((long)num > max) || ((long)num < min))
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retval = 1;
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}
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else
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{
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max = (1 << bits) - 1;
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min = 0;
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if ((num > max) || (num < min))
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retval = 1;
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}
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return retval;
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}
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void
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md_show_usage (stream)
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FILE *stream;
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{
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fprintf(stream, "D10V options:\n\
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-O optimize. Will do some operations in parallel.\n");
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}
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int
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md_parse_option (c, arg)
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int c;
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char *arg;
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{
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switch (c)
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{
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case 'O':
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/* Optimize. Will attempt to parallelize operations */
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Optimizing = 1;
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break;
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case OPTION_NOWARNSWAP:
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flag_warn_suppress_instructionswap = 1;
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break;
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default:
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return 0;
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}
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return 1;
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}
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symbolS *
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md_undefined_symbol (name)
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char *name;
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{
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return 0;
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}
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/* Turn a string in input_line_pointer into a floating point constant of type
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type, and store the appropriate bytes in *litP. The number of LITTLENUMS
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emitted is stored in *sizeP . An error message is returned, or NULL on OK.
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*/
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char *
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md_atof (type, litP, sizeP)
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int type;
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char *litP;
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int *sizeP;
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{
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int prec;
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LITTLENUM_TYPE words[4];
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char *t;
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int i;
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switch (type)
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{
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case 'f':
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prec = 2;
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break;
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case 'd':
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prec = 4;
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break;
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default:
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*sizeP = 0;
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return "bad call to md_atof";
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}
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t = atof_ieee (input_line_pointer, type, words);
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if (t)
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input_line_pointer = t;
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*sizeP = prec * 2;
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for (i = 0; i < prec; i++)
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{
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md_number_to_chars (litP, (valueT) words[i], 2);
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litP += 2;
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}
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return NULL;
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}
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void
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md_convert_frag (abfd, sec, fragP)
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bfd *abfd;
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asection *sec;
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fragS *fragP;
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{
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abort ();
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}
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valueT
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md_section_align (seg, addr)
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asection *seg;
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valueT addr;
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{
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int align = bfd_get_section_alignment (stdoutput, seg);
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return ((addr + (1 << align) - 1) & (-1 << align));
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}
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void
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md_begin ()
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{
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char *prev_name = "";
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struct d10v_opcode *opcode;
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d10v_hash = hash_new();
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/* Insert unique names into hash table. The D10v instruction set
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has many identical opcode names that have different opcodes based
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on the operands. This hash table then provides a quick index to
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the first opcode with a particular name in the opcode table. */
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for (opcode = (struct d10v_opcode *)d10v_opcodes; opcode->name; opcode++)
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{
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if (strcmp (prev_name, opcode->name))
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{
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prev_name = (char *)opcode->name;
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hash_insert (d10v_hash, opcode->name, (char *) opcode);
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}
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}
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fixups = &FixUps[0];
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FixUps[0].next = &FixUps[1];
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FixUps[1].next = &FixUps[0];
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}
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/* this function removes the postincrement or postdecrement
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operator ( '+' or '-' ) from an expression */
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static int postfix (p)
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char *p;
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{
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while (*p != '-' && *p != '+')
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{
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if (*p==0 || *p=='\n' || *p=='\r')
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break;
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p++;
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}
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if (*p == '-')
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{
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*p = ' ';
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return (-1);
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}
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if (*p == '+')
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{
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*p = ' ';
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return (1);
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}
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return (0);
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}
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static bfd_reloc_code_real_type
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get_reloc (op)
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struct d10v_operand *op;
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{
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int bits = op->bits;
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if (bits <= 4)
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return (0);
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if (op->flags & OPERAND_ADDR)
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{
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if (bits == 8)
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return (BFD_RELOC_D10V_10_PCREL_R);
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else
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return (BFD_RELOC_D10V_18_PCREL);
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}
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return (BFD_RELOC_16);
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}
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/* get_operands parses a string of operands and returns
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an array of expressions */
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static int
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get_operands (exp)
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expressionS exp[];
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{
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char *p = input_line_pointer;
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int numops = 0;
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int post = 0;
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while (*p)
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{
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while (*p == ' ' || *p == '\t' || *p == ',')
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p++;
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if (*p==0 || *p=='\n' || *p=='\r')
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break;
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if (*p == '@')
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{
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p++;
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exp[numops].X_op = O_absent;
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if (*p == '(')
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{
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p++;
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exp[numops].X_add_number = OPERAND_ATPAR;
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}
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else if (*p == '-')
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{
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p++;
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exp[numops].X_add_number = OPERAND_ATMINUS;
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}
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else
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{
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exp[numops].X_add_number = OPERAND_ATSIGN;
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post = postfix (p);
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}
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numops++;
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continue;
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}
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if (*p == ')')
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{
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/* just skip the trailing paren */
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p++;
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continue;
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}
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input_line_pointer = p;
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/* check to see if it might be a register name */
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if (!register_name (&exp[numops]))
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{
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/* parse as an expression */
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expression (&exp[numops]);
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}
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if (strncasecmp (input_line_pointer, "@word", 5) == 0)
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{
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input_line_pointer += 5;
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if (exp[numops].X_op == O_register)
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{
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/* if it looked like a register name but was followed by
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"@word" then it was really a symbol, so change it to
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one */
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exp[numops].X_op = O_symbol;
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exp[numops].X_add_symbol = symbol_find_or_make ((char *)exp[numops].X_op_symbol);
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}
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/* check for identifier@word+constant */
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if (*input_line_pointer == '-' || *input_line_pointer == '+')
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{
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char *orig_line = input_line_pointer;
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expressionS new_exp;
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expression (&new_exp);
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exp[numops].X_add_number = new_exp.X_add_number;
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}
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/* convert expr into a right shift by AT_WORD_RIGHT_SHIFT */
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{
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expressionS new_exp;
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memset (&new_exp, 0, sizeof new_exp);
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new_exp.X_add_number = AT_WORD_RIGHT_SHIFT;
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new_exp.X_op = O_constant;
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new_exp.X_unsigned = 1;
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exp[numops].X_op_symbol = make_expr_symbol (&new_exp);
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exp[numops].X_op = O_right_shift;
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}
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know (AT_WORD_P (&exp[numops]));
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}
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if (exp[numops].X_op == O_illegal)
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as_bad ("illegal operand");
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else if (exp[numops].X_op == O_absent)
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as_bad ("missing operand");
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numops++;
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p = input_line_pointer;
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}
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switch (post)
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{
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case -1: /* postdecrement mode */
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exp[numops].X_op = O_absent;
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exp[numops++].X_add_number = OPERAND_MINUS;
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break;
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case 1: /* postincrement mode */
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exp[numops].X_op = O_absent;
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exp[numops++].X_add_number = OPERAND_PLUS;
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break;
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}
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exp[numops].X_op = 0;
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return (numops);
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}
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static unsigned long
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d10v_insert_operand (insn, op_type, value, left, fix)
|
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unsigned long insn;
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int op_type;
|
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offsetT value;
|
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int left;
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fixS *fix;
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{
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int shift, bits;
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shift = d10v_operands[op_type].shift;
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if (left)
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shift += 15;
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bits = d10v_operands[op_type].bits;
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|
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/* truncate to the proper number of bits */
|
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if (check_range (value, bits, d10v_operands[op_type].flags))
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as_bad_where (fix->fx_file, fix->fx_line, "operand out of range: %d", value);
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value &= 0x7FFFFFFF >> (31 - bits);
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insn |= (value << shift);
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return insn;
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}
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|
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/* build_insn takes a pointer to the opcode entry in the opcode table
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and the array of operand expressions and returns the instruction */
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|
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static unsigned long
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build_insn (opcode, opers, insn)
|
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struct d10v_opcode *opcode;
|
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expressionS *opers;
|
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unsigned long insn;
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{
|
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int i, bits, shift, flags, format;
|
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unsigned long number;
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|
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/* the insn argument is only used for the DIVS kludge */
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if (insn)
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format = LONG_R;
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else
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{
|
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insn = opcode->opcode;
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format = opcode->format;
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}
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for (i=0;opcode->operands[i];i++)
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{
|
|
flags = d10v_operands[opcode->operands[i]].flags;
|
|
bits = d10v_operands[opcode->operands[i]].bits;
|
|
shift = d10v_operands[opcode->operands[i]].shift;
|
|
number = opers[i].X_add_number;
|
|
|
|
if (flags & OPERAND_REG)
|
|
{
|
|
number &= REGISTER_MASK;
|
|
if (format == LONG_L)
|
|
shift += 15;
|
|
}
|
|
|
|
if (opers[i].X_op != O_register && opers[i].X_op != O_constant)
|
|
{
|
|
/* now create a fixup */
|
|
|
|
if (fixups->fc >= MAX_INSN_FIXUPS)
|
|
as_fatal ("too many fixups");
|
|
|
|
if (AT_WORD_P (&opers[i]))
|
|
{
|
|
/* Reconize XXX>>1+N aka XXX@word+N as special (AT_WORD) */
|
|
fixups->fix[fixups->fc].reloc = BFD_RELOC_D10V_18;
|
|
opers[i].X_op = O_symbol;
|
|
opers[i].X_op_symbol = NULL; /* Should free it */
|
|
/* number is left shifted by AT_WORD_RIGHT_SHIFT so
|
|
that, it is aligned with the symbol's value. Later,
|
|
BFD_RELOC_D10V_18 will right shift (symbol_value +
|
|
X_add_number). */
|
|
number <<= AT_WORD_RIGHT_SHIFT;
|
|
opers[i].X_add_number = number;
|
|
}
|
|
else
|
|
fixups->fix[fixups->fc].reloc =
|
|
get_reloc((struct d10v_operand *)&d10v_operands[opcode->operands[i]]);
|
|
|
|
if (fixups->fix[fixups->fc].reloc == BFD_RELOC_16 ||
|
|
fixups->fix[fixups->fc].reloc == BFD_RELOC_D10V_18)
|
|
fixups->fix[fixups->fc].size = 2;
|
|
else
|
|
fixups->fix[fixups->fc].size = 4;
|
|
|
|
fixups->fix[fixups->fc].exp = opers[i];
|
|
fixups->fix[fixups->fc].operand = opcode->operands[i];
|
|
fixups->fix[fixups->fc].pcrel = (flags & OPERAND_ADDR) ? true : false;
|
|
(fixups->fc)++;
|
|
}
|
|
|
|
/* truncate to the proper number of bits */
|
|
if ((opers[i].X_op == O_constant) && check_range (number, bits, flags))
|
|
as_bad("operand out of range: %d",number);
|
|
number &= 0x7FFFFFFF >> (31 - bits);
|
|
insn = insn | (number << shift);
|
|
}
|
|
|
|
/* kludge: for DIVS, we need to put the operands in twice */
|
|
/* on the second pass, format is changed to LONG_R to force */
|
|
/* the second set of operands to not be shifted over 15 */
|
|
if ((opcode->opcode == OPCODE_DIVS) && (format==LONG_L))
|
|
insn = build_insn (opcode, opers, insn);
|
|
|
|
return insn;
|
|
}
|
|
|
|
/* write out a long form instruction */
|
|
static void
|
|
write_long (opcode, insn, fx)
|
|
struct d10v_opcode *opcode;
|
|
unsigned long insn;
|
|
Fixups *fx;
|
|
{
|
|
int i, where;
|
|
char *f = frag_more(4);
|
|
|
|
insn |= FM11;
|
|
number_to_chars_bigendian (f, insn, 4);
|
|
|
|
for (i=0; i < fx->fc; i++)
|
|
{
|
|
if (fx->fix[i].reloc)
|
|
{
|
|
where = f - frag_now->fr_literal;
|
|
if (fx->fix[i].size == 2)
|
|
where += 2;
|
|
|
|
if (fx->fix[i].reloc == BFD_RELOC_D10V_18)
|
|
fx->fix[i].operand |= 4096;
|
|
|
|
fix_new_exp (frag_now,
|
|
where,
|
|
fx->fix[i].size,
|
|
&(fx->fix[i].exp),
|
|
fx->fix[i].pcrel,
|
|
fx->fix[i].operand|2048);
|
|
}
|
|
}
|
|
fx->fc = 0;
|
|
}
|
|
|
|
|
|
/* write out a short form instruction by itself */
|
|
static void
|
|
write_1_short (opcode, insn, fx)
|
|
struct d10v_opcode *opcode;
|
|
unsigned long insn;
|
|
Fixups *fx;
|
|
{
|
|
char *f = frag_more(4);
|
|
int i, where;
|
|
|
|
if (opcode->exec_type & PARONLY)
|
|
as_fatal ("Instruction must be executed in parallel with another instruction.");
|
|
|
|
/* the other container needs to be NOP */
|
|
/* according to 4.3.1: for FM=00, sub-instructions performed only
|
|
by IU cannot be encoded in L-container. */
|
|
if (opcode->unit == IU)
|
|
insn |= FM00 | (NOP << 15); /* right container */
|
|
else
|
|
insn = FM00 | (insn << 15) | NOP; /* left container */
|
|
|
|
number_to_chars_bigendian (f, insn, 4);
|
|
for (i=0; i < fx->fc; i++)
|
|
{
|
|
if (fx->fix[i].reloc)
|
|
{
|
|
where = f - frag_now->fr_literal;
|
|
if (fx->fix[i].size == 2)
|
|
where += 2;
|
|
|
|
if (fx->fix[i].reloc == BFD_RELOC_D10V_18)
|
|
fx->fix[i].operand |= 4096;
|
|
|
|
/* if it's an R reloc, we may have to switch it to L */
|
|
if ( (fx->fix[i].reloc == BFD_RELOC_D10V_10_PCREL_R) && (opcode->unit != IU) )
|
|
fx->fix[i].operand |= 1024;
|
|
|
|
fix_new_exp (frag_now,
|
|
where,
|
|
fx->fix[i].size,
|
|
&(fx->fix[i].exp),
|
|
fx->fix[i].pcrel,
|
|
fx->fix[i].operand|2048);
|
|
}
|
|
}
|
|
fx->fc = 0;
|
|
}
|
|
|
|
/* write out a short form instruction if possible */
|
|
/* return number of instructions not written out */
|
|
static int
|
|
write_2_short (opcode1, insn1, opcode2, insn2, exec_type, fx)
|
|
struct d10v_opcode *opcode1, *opcode2;
|
|
unsigned long insn1, insn2;
|
|
int exec_type;
|
|
Fixups *fx;
|
|
{
|
|
unsigned long insn;
|
|
char *f;
|
|
int i,j, where;
|
|
|
|
if ( (exec_type != 1) && ((opcode1->exec_type & PARONLY)
|
|
|| (opcode2->exec_type & PARONLY)))
|
|
as_fatal("Instruction must be executed in parallel");
|
|
|
|
if ( (opcode1->format & LONG_OPCODE) || (opcode2->format & LONG_OPCODE))
|
|
as_fatal ("Long instructions may not be combined.");
|
|
|
|
if(opcode1->exec_type & BRANCH_LINK && exec_type == 0)
|
|
{
|
|
/* Instructions paired with a subroutine call are executed before the
|
|
subroutine, so don't do these pairings unless explicitly requested. */
|
|
write_1_short (opcode1, insn1, fx->next);
|
|
return (1);
|
|
}
|
|
|
|
switch (exec_type)
|
|
{
|
|
case 0: /* order not specified */
|
|
if ( Optimizing && parallel_ok (opcode1, insn1, opcode2, insn2, exec_type))
|
|
{
|
|
/* parallel */
|
|
if (opcode1->unit == IU)
|
|
insn = FM00 | (insn2 << 15) | insn1;
|
|
else if (opcode2->unit == MU)
|
|
insn = FM00 | (insn2 << 15) | insn1;
|
|
else
|
|
{
|
|
insn = FM00 | (insn1 << 15) | insn2;
|
|
fx = fx->next;
|
|
}
|
|
}
|
|
else if (opcode1->unit == IU)
|
|
{
|
|
/* reverse sequential */
|
|
insn = FM10 | (insn2 << 15) | insn1;
|
|
}
|
|
else
|
|
{
|
|
/* sequential */
|
|
insn = FM01 | (insn1 << 15) | insn2;
|
|
fx = fx->next;
|
|
}
|
|
break;
|
|
case 1: /* parallel */
|
|
if (opcode1->exec_type & SEQ || opcode2->exec_type & SEQ)
|
|
as_fatal ("One of these instructions may not be executed in parallel.");
|
|
|
|
if (opcode1->unit == IU)
|
|
{
|
|
if (opcode2->unit == IU)
|
|
as_fatal ("Two IU instructions may not be executed in parallel");
|
|
if (!flag_warn_suppress_instructionswap)
|
|
as_warn ("Swapping instruction order");
|
|
insn = FM00 | (insn2 << 15) | insn1;
|
|
}
|
|
else if (opcode2->unit == MU)
|
|
{
|
|
if (opcode1->unit == MU)
|
|
as_fatal ("Two MU instructions may not be executed in parallel");
|
|
if (!flag_warn_suppress_instructionswap)
|
|
as_warn ("Swapping instruction order");
|
|
insn = FM00 | (insn2 << 15) | insn1;
|
|
}
|
|
else
|
|
{
|
|
insn = FM00 | (insn1 << 15) | insn2;
|
|
fx = fx->next;
|
|
}
|
|
break;
|
|
case 2: /* sequential */
|
|
if (opcode1->unit == IU)
|
|
as_fatal ("IU instruction may not be in the left container");
|
|
insn = FM01 | (insn1 << 15) | insn2;
|
|
fx = fx->next;
|
|
break;
|
|
case 3: /* reverse sequential */
|
|
if (opcode2->unit == MU)
|
|
as_fatal ("MU instruction may not be in the right container");
|
|
insn = FM10 | (insn1 << 15) | insn2;
|
|
fx = fx->next;
|
|
break;
|
|
default:
|
|
as_fatal("unknown execution type passed to write_2_short()");
|
|
}
|
|
|
|
f = frag_more(4);
|
|
number_to_chars_bigendian (f, insn, 4);
|
|
|
|
for (j=0; j<2; j++)
|
|
{
|
|
for (i=0; i < fx->fc; i++)
|
|
{
|
|
if (fx->fix[i].reloc)
|
|
{
|
|
where = f - frag_now->fr_literal;
|
|
if (fx->fix[i].size == 2)
|
|
where += 2;
|
|
|
|
if ( (fx->fix[i].reloc == BFD_RELOC_D10V_10_PCREL_R) && (j == 0) )
|
|
fx->fix[i].operand |= 1024;
|
|
|
|
if (fx->fix[i].reloc == BFD_RELOC_D10V_18)
|
|
fx->fix[i].operand |= 4096;
|
|
|
|
fix_new_exp (frag_now,
|
|
where,
|
|
fx->fix[i].size,
|
|
&(fx->fix[i].exp),
|
|
fx->fix[i].pcrel,
|
|
fx->fix[i].operand|2048);
|
|
}
|
|
}
|
|
fx->fc = 0;
|
|
fx = fx->next;
|
|
}
|
|
return (0);
|
|
}
|
|
|
|
|
|
/* Check 2 instructions and determine if they can be safely */
|
|
/* executed in parallel. Returns 1 if they can be. */
|
|
static int
|
|
parallel_ok (op1, insn1, op2, insn2, exec_type)
|
|
struct d10v_opcode *op1, *op2;
|
|
unsigned long insn1, insn2;
|
|
int exec_type;
|
|
{
|
|
int i, j, flags, mask, shift, regno;
|
|
unsigned long ins, mod[2], used[2];
|
|
struct d10v_opcode *op;
|
|
|
|
if ((op1->exec_type & SEQ) != 0 || (op2->exec_type & SEQ) != 0
|
|
|| (op1->exec_type & PAR) == 0 || (op2->exec_type & PAR) == 0
|
|
|| (op1->unit == BOTH) || (op2->unit == BOTH)
|
|
|| (op1->unit == IU && op2->unit == IU)
|
|
|| (op1->unit == MU && op2->unit == MU))
|
|
return 0;
|
|
|
|
/* If the first instruction is a branch and this is auto parallazation,
|
|
don't combine with any second instruction. */
|
|
if (exec_type == 0 && (op1->exec_type & BRANCH) != 0)
|
|
return 0;
|
|
|
|
/* The idea here is to create two sets of bitmasks (mod and used)
|
|
which indicate which registers are modified or used by each
|
|
instruction. The operation can only be done in parallel if
|
|
instruction 1 and instruction 2 modify different registers, and
|
|
the first instruction does not modify registers that the second
|
|
is using (The second instruction can modify registers that the
|
|
first is using as they are only written back after the first
|
|
instruction has completed). Accesses to control registers, PSW,
|
|
and memory are treated as accesses to a single register. So if
|
|
both instructions write memory or if the first instruction writes
|
|
memory and the second reads, then they cannot be done in
|
|
parallel. Likewise, if the first instruction mucks with the psw
|
|
and the second reads the PSW (which includes C, F0, and F1), then
|
|
they cannot operate safely in parallel. */
|
|
|
|
/* the bitmasks (mod and used) look like this (bit 31 = MSB) */
|
|
/* r0-r15 0-15 */
|
|
/* a0-a1 16-17 */
|
|
/* cr (not psw) 18 */
|
|
/* psw 19 */
|
|
/* mem 20 */
|
|
|
|
for (j=0;j<2;j++)
|
|
{
|
|
if (j == 0)
|
|
{
|
|
op = op1;
|
|
ins = insn1;
|
|
}
|
|
else
|
|
{
|
|
op = op2;
|
|
ins = insn2;
|
|
}
|
|
mod[j] = used[j] = 0;
|
|
if (op->exec_type & BRANCH_LINK)
|
|
mod[j] |= 1 << 13;
|
|
|
|
for (i = 0; op->operands[i]; i++)
|
|
{
|
|
flags = d10v_operands[op->operands[i]].flags;
|
|
shift = d10v_operands[op->operands[i]].shift;
|
|
mask = 0x7FFFFFFF >> (31 - d10v_operands[op->operands[i]].bits);
|
|
if (flags & OPERAND_REG)
|
|
{
|
|
regno = (ins >> shift) & mask;
|
|
if (flags & (OPERAND_ACC0|OPERAND_ACC1))
|
|
regno += 16;
|
|
else if (flags & OPERAND_CONTROL) /* mvtc or mvfc */
|
|
{
|
|
if (regno == 0)
|
|
regno = 19;
|
|
else
|
|
regno = 18;
|
|
}
|
|
else if (flags & (OPERAND_FFLAG|OPERAND_CFLAG))
|
|
regno = 19;
|
|
|
|
if ( flags & OPERAND_DEST )
|
|
{
|
|
mod[j] |= 1 << regno;
|
|
if (flags & OPERAND_EVEN)
|
|
mod[j] |= 1 << (regno + 1);
|
|
}
|
|
else
|
|
{
|
|
used[j] |= 1 << regno ;
|
|
if (flags & OPERAND_EVEN)
|
|
used[j] |= 1 << (regno + 1);
|
|
|
|
/* Auto inc/dec also modifies the register. */
|
|
if (op->operands[i+1] != 0
|
|
&& (d10v_operands[op->operands[i+1]].flags
|
|
& (OPERAND_PLUS | OPERAND_MINUS)) != 0)
|
|
mod[j] |= 1 << regno;
|
|
}
|
|
}
|
|
else if (flags & OPERAND_ATMINUS)
|
|
{
|
|
/* SP implicitly used/modified */
|
|
mod[j] |= 1 << 15;
|
|
used[j] |= 1 << 15;
|
|
}
|
|
}
|
|
if (op->exec_type & RMEM)
|
|
used[j] |= 1 << 20;
|
|
else if (op->exec_type & WMEM)
|
|
mod[j] |= 1 << 20;
|
|
else if (op->exec_type & RF0)
|
|
used[j] |= 1 << 19;
|
|
else if (op->exec_type & WF0)
|
|
mod[j] |= 1 << 19;
|
|
else if (op->exec_type & WCAR)
|
|
mod[j] |= 1 << 19;
|
|
}
|
|
if ((mod[0] & mod[1]) == 0 && (mod[0] & used[1]) == 0)
|
|
return 1;
|
|
return 0;
|
|
}
|
|
|
|
|
|
/* This is the main entry point for the machine-dependent assembler. str points to a
|
|
machine-dependent instruction. This function is supposed to emit the frags/bytes
|
|
it assembles to. For the D10V, it mostly handles the special VLIW parsing and packing
|
|
and leaves the difficult stuff to do_assemble().
|
|
*/
|
|
|
|
static unsigned long prev_insn;
|
|
static struct d10v_opcode *prev_opcode = 0;
|
|
static subsegT prev_subseg;
|
|
static segT prev_seg = 0;;
|
|
|
|
void
|
|
md_assemble (str)
|
|
char *str;
|
|
{
|
|
struct d10v_opcode *opcode;
|
|
unsigned long insn;
|
|
int extype=0; /* execution type; parallel, etc */
|
|
static int etype=0; /* saved extype. used for multiline instructions */
|
|
char *str2;
|
|
|
|
if (etype == 0)
|
|
{
|
|
/* look for the special multiple instruction separators */
|
|
str2 = strstr (str, "||");
|
|
if (str2)
|
|
extype = 1;
|
|
else
|
|
{
|
|
str2 = strstr (str, "->");
|
|
if (str2)
|
|
extype = 2;
|
|
else
|
|
{
|
|
str2 = strstr (str, "<-");
|
|
if (str2)
|
|
extype = 3;
|
|
}
|
|
}
|
|
/* str2 points to the separator, if one */
|
|
if (str2)
|
|
{
|
|
*str2 = 0;
|
|
|
|
/* if two instructions are present and we already have one saved
|
|
then first write it out */
|
|
d10v_cleanup();
|
|
|
|
/* assemble first instruction and save it */
|
|
prev_insn = do_assemble (str, &prev_opcode);
|
|
if (prev_insn == -1)
|
|
as_fatal ("can't find opcode ");
|
|
fixups = fixups->next;
|
|
str = str2 + 2;
|
|
}
|
|
}
|
|
|
|
insn = do_assemble (str, &opcode);
|
|
if (insn == -1)
|
|
{
|
|
if (extype)
|
|
{
|
|
etype = extype;
|
|
return;
|
|
}
|
|
as_fatal ("can't find opcode ");
|
|
}
|
|
|
|
if (etype)
|
|
{
|
|
extype = etype;
|
|
etype = 0;
|
|
}
|
|
|
|
/* if this is a long instruction, write it and any previous short instruction */
|
|
if (opcode->format & LONG_OPCODE)
|
|
{
|
|
if (extype)
|
|
as_fatal("Unable to mix instructions as specified");
|
|
d10v_cleanup();
|
|
write_long (opcode, insn, fixups);
|
|
prev_opcode = NULL;
|
|
return;
|
|
}
|
|
|
|
if (prev_opcode && prev_seg && ((prev_seg != now_seg) || (prev_subseg != now_subseg)))
|
|
d10v_cleanup();
|
|
|
|
if (prev_opcode && (write_2_short (prev_opcode, prev_insn, opcode, insn, extype, fixups) == 0))
|
|
{
|
|
/* no instructions saved */
|
|
prev_opcode = NULL;
|
|
}
|
|
else
|
|
{
|
|
if (extype)
|
|
as_fatal("Unable to mix instructions as specified");
|
|
/* save off last instruction so it may be packed on next pass */
|
|
prev_opcode = opcode;
|
|
prev_insn = insn;
|
|
prev_seg = now_seg;
|
|
prev_subseg = now_subseg;
|
|
fixups = fixups->next;
|
|
}
|
|
}
|
|
|
|
|
|
/* do_assemble assembles a single instruction and returns an opcode */
|
|
/* it returns -1 (an invalid opcode) on error */
|
|
|
|
static unsigned long
|
|
do_assemble (str, opcode)
|
|
char *str;
|
|
struct d10v_opcode **opcode;
|
|
{
|
|
unsigned char *op_start, *save;
|
|
unsigned char *op_end;
|
|
char name[20];
|
|
int nlen = 0;
|
|
expressionS myops[6];
|
|
unsigned long insn;
|
|
|
|
/* Drop leading whitespace */
|
|
while (*str == ' ')
|
|
str++;
|
|
|
|
/* find the opcode end */
|
|
for (op_start = op_end = (unsigned char *) (str);
|
|
*op_end
|
|
&& nlen < 20
|
|
&& !is_end_of_line[*op_end] && *op_end != ' ';
|
|
op_end++)
|
|
{
|
|
name[nlen] = tolower(op_start[nlen]);
|
|
nlen++;
|
|
}
|
|
name[nlen] = 0;
|
|
|
|
if (nlen == 0)
|
|
return (-1);
|
|
|
|
/* find the first opcode with the proper name */
|
|
*opcode = (struct d10v_opcode *)hash_find (d10v_hash, name);
|
|
if (*opcode == NULL)
|
|
as_fatal ("unknown opcode: %s",name);
|
|
|
|
save = input_line_pointer;
|
|
input_line_pointer = op_end;
|
|
*opcode = find_opcode (*opcode, myops);
|
|
if (*opcode == 0)
|
|
return -1;
|
|
input_line_pointer = save;
|
|
|
|
insn = build_insn ((*opcode), myops, 0);
|
|
return (insn);
|
|
}
|
|
|
|
/* find_opcode() gets a pointer to an entry in the opcode table. */
|
|
/* It must look at all opcodes with the same name and use the operands */
|
|
/* to choose the correct opcode. */
|
|
|
|
static struct d10v_opcode *
|
|
find_opcode (opcode, myops)
|
|
struct d10v_opcode *opcode;
|
|
expressionS myops[];
|
|
{
|
|
int i, match, done;
|
|
struct d10v_opcode *next_opcode;
|
|
|
|
/* get all the operands and save them as expressions */
|
|
get_operands (myops);
|
|
|
|
/* now see if the operand is a fake. If so, find the correct size */
|
|
/* instruction, if possible */
|
|
if (opcode->format == OPCODE_FAKE)
|
|
{
|
|
int opnum = opcode->operands[0];
|
|
int flags;
|
|
|
|
if (myops[opnum].X_op == O_register)
|
|
{
|
|
myops[opnum].X_op = O_symbol;
|
|
myops[opnum].X_add_symbol = symbol_find_or_make ((char *)myops[opnum].X_op_symbol);
|
|
myops[opnum].X_add_number = 0;
|
|
myops[opnum].X_op_symbol = NULL;
|
|
}
|
|
|
|
next_opcode=opcode+1;
|
|
|
|
/* If the first operand is supposed to be a register, make sure
|
|
we got a valid one. */
|
|
flags = d10v_operands[next_opcode->operands[0]].flags;
|
|
if (flags & OPERAND_REG)
|
|
{
|
|
int X_op = myops[0].X_op;
|
|
int num = myops[0].X_add_number;
|
|
|
|
if (X_op != O_register
|
|
|| (num & ~flags
|
|
& (OPERAND_GPR | OPERAND_ACC0 | OPERAND_ACC1
|
|
| OPERAND_FFLAG | OPERAND_CFLAG | OPERAND_CONTROL)))
|
|
{
|
|
as_bad ("bad opcode or operands");
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
if (myops[opnum].X_op == O_constant || (myops[opnum].X_op == O_symbol &&
|
|
S_IS_DEFINED(myops[opnum].X_add_symbol) &&
|
|
(S_GET_SEGMENT(myops[opnum].X_add_symbol) == now_seg)))
|
|
{
|
|
for (i=0; opcode->operands[i+1]; i++)
|
|
{
|
|
int bits = d10v_operands[next_opcode->operands[opnum]].bits;
|
|
int flags = d10v_operands[next_opcode->operands[opnum]].flags;
|
|
if (flags & OPERAND_ADDR)
|
|
bits += 2;
|
|
if (myops[opnum].X_op == O_constant)
|
|
{
|
|
if (!check_range (myops[opnum].X_add_number, bits, flags))
|
|
return next_opcode;
|
|
}
|
|
else
|
|
{
|
|
fragS *f;
|
|
long value;
|
|
/* calculate the current address by running through the previous frags */
|
|
/* and adding our current offset */
|
|
for (value = 0, f = frchain_now->frch_root; f; f = f->fr_next)
|
|
value += f->fr_fix + f->fr_offset;
|
|
|
|
if (flags & OPERAND_ADDR)
|
|
value = S_GET_VALUE(myops[opnum].X_add_symbol) - value -
|
|
(obstack_next_free(&frchain_now->frch_obstack) - frag_now->fr_literal);
|
|
else
|
|
value = S_GET_VALUE(myops[opnum].X_add_symbol);
|
|
|
|
if (AT_WORD_P (&myops[opnum]))
|
|
{
|
|
if (bits > 4)
|
|
{
|
|
bits += 2;
|
|
if (!check_range (value, bits, flags))
|
|
return next_opcode;
|
|
}
|
|
}
|
|
else if (!check_range (value, bits, flags))
|
|
return next_opcode;
|
|
}
|
|
next_opcode++;
|
|
}
|
|
as_fatal ("value out of range");
|
|
}
|
|
else
|
|
{
|
|
/* not a constant, so use a long instruction */
|
|
return opcode+2;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
match = 0;
|
|
/* now search the opcode table table for one with operands */
|
|
/* that matches what we've got */
|
|
while (!match)
|
|
{
|
|
match = 1;
|
|
for (i = 0; opcode->operands[i]; i++)
|
|
{
|
|
int flags = d10v_operands[opcode->operands[i]].flags;
|
|
int X_op = myops[i].X_op;
|
|
int num = myops[i].X_add_number;
|
|
|
|
if (X_op==0)
|
|
{
|
|
match=0;
|
|
break;
|
|
}
|
|
|
|
if (flags & OPERAND_REG)
|
|
{
|
|
if ((X_op != O_register)
|
|
|| (num & ~flags
|
|
& (OPERAND_GPR | OPERAND_ACC0 | OPERAND_ACC1
|
|
| OPERAND_FFLAG | OPERAND_CFLAG
|
|
| OPERAND_CONTROL)))
|
|
{
|
|
match=0;
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (((flags & OPERAND_MINUS) && ((X_op != O_absent) || (num != OPERAND_MINUS))) ||
|
|
((flags & OPERAND_PLUS) && ((X_op != O_absent) || (num != OPERAND_PLUS))) ||
|
|
((flags & OPERAND_ATMINUS) && ((X_op != O_absent) || (num != OPERAND_ATMINUS))) ||
|
|
((flags & OPERAND_ATPAR) && ((X_op != O_absent) || (num != OPERAND_ATPAR))) ||
|
|
((flags & OPERAND_ATSIGN) && ((X_op != O_absent) || (num != OPERAND_ATSIGN))))
|
|
{
|
|
match=0;
|
|
break;
|
|
}
|
|
}
|
|
/* we're only done if the operands matched so far AND there
|
|
are no more to check */
|
|
if (match && myops[i].X_op==0)
|
|
break;
|
|
else
|
|
match = 0;
|
|
|
|
next_opcode = opcode+1;
|
|
if (next_opcode->opcode == 0)
|
|
break;
|
|
if (strcmp(next_opcode->name, opcode->name))
|
|
break;
|
|
opcode = next_opcode;
|
|
}
|
|
}
|
|
|
|
if (!match)
|
|
{
|
|
as_bad ("bad opcode or operands");
|
|
return (0);
|
|
}
|
|
|
|
/* Check that all registers that are required to be even are. */
|
|
/* Also, if any operands were marked as registers, but were really symbols */
|
|
/* fix that here. */
|
|
for (i=0; opcode->operands[i]; i++)
|
|
{
|
|
if ((d10v_operands[opcode->operands[i]].flags & OPERAND_EVEN) &&
|
|
(myops[i].X_add_number & 1))
|
|
as_fatal("Register number must be EVEN");
|
|
if (myops[i].X_op == O_register)
|
|
{
|
|
if (!(d10v_operands[opcode->operands[i]].flags & OPERAND_REG))
|
|
{
|
|
myops[i].X_op = O_symbol;
|
|
myops[i].X_add_symbol = symbol_find_or_make ((char *)myops[i].X_op_symbol);
|
|
myops[i].X_add_number = 0;
|
|
myops[i].X_op_symbol = NULL;
|
|
}
|
|
}
|
|
}
|
|
return opcode;
|
|
}
|
|
|
|
/* if while processing a fixup, a reloc really needs to be created */
|
|
/* then it is done here */
|
|
|
|
arelent *
|
|
tc_gen_reloc (seg, fixp)
|
|
asection *seg;
|
|
fixS *fixp;
|
|
{
|
|
arelent *reloc;
|
|
reloc = (arelent *) xmalloc (sizeof (arelent));
|
|
reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym;
|
|
reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
|
|
reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
|
|
if (reloc->howto == (reloc_howto_type *) NULL)
|
|
{
|
|
as_bad_where (fixp->fx_file, fixp->fx_line,
|
|
"reloc %d not supported by object file format", (int)fixp->fx_r_type);
|
|
return NULL;
|
|
}
|
|
reloc->addend = fixp->fx_addnumber;
|
|
return reloc;
|
|
}
|
|
|
|
int
|
|
md_estimate_size_before_relax (fragp, seg)
|
|
fragS *fragp;
|
|
asection *seg;
|
|
{
|
|
abort ();
|
|
return 0;
|
|
}
|
|
|
|
long
|
|
md_pcrel_from_section (fixp, sec)
|
|
fixS *fixp;
|
|
segT sec;
|
|
{
|
|
if (fixp->fx_addsy != (symbolS *)NULL && (!S_IS_DEFINED (fixp->fx_addsy) ||
|
|
(S_GET_SEGMENT (fixp->fx_addsy) != sec)))
|
|
return 0;
|
|
return fixp->fx_frag->fr_address + fixp->fx_where;
|
|
}
|
|
|
|
int
|
|
md_apply_fix3 (fixp, valuep, seg)
|
|
fixS *fixp;
|
|
valueT *valuep;
|
|
segT seg;
|
|
{
|
|
char *where;
|
|
unsigned long insn;
|
|
long value;
|
|
int op_type;
|
|
int left=0;
|
|
|
|
if (fixp->fx_addsy == (symbolS *) NULL)
|
|
{
|
|
value = *valuep;
|
|
fixp->fx_done = 1;
|
|
}
|
|
else if (fixp->fx_pcrel)
|
|
value = *valuep;
|
|
else
|
|
{
|
|
value = fixp->fx_offset;
|
|
if (fixp->fx_subsy != (symbolS *) NULL)
|
|
{
|
|
if (S_GET_SEGMENT (fixp->fx_subsy) == absolute_section)
|
|
value -= S_GET_VALUE (fixp->fx_subsy);
|
|
else
|
|
{
|
|
/* We don't actually support subtracting a symbol. */
|
|
as_bad_where (fixp->fx_file, fixp->fx_line,
|
|
"expression too complex");
|
|
}
|
|
}
|
|
}
|
|
|
|
op_type = fixp->fx_r_type;
|
|
if (op_type & 2048)
|
|
{
|
|
op_type -= 2048;
|
|
if (op_type & 1024)
|
|
{
|
|
op_type -= 1024;
|
|
fixp->fx_r_type = BFD_RELOC_D10V_10_PCREL_L;
|
|
left = 1;
|
|
}
|
|
else if (op_type & 4096)
|
|
{
|
|
op_type -= 4096;
|
|
fixp->fx_r_type = BFD_RELOC_D10V_18;
|
|
}
|
|
else
|
|
fixp->fx_r_type = get_reloc((struct d10v_operand *)&d10v_operands[op_type]);
|
|
}
|
|
|
|
/* Fetch the instruction, insert the fully resolved operand
|
|
value, and stuff the instruction back again. */
|
|
where = fixp->fx_frag->fr_literal + fixp->fx_where;
|
|
insn = bfd_getb32 ((unsigned char *) where);
|
|
|
|
switch (fixp->fx_r_type)
|
|
{
|
|
case BFD_RELOC_D10V_10_PCREL_L:
|
|
case BFD_RELOC_D10V_10_PCREL_R:
|
|
case BFD_RELOC_D10V_18_PCREL:
|
|
case BFD_RELOC_D10V_18:
|
|
/* instruction addresses are always right-shifted by 2 */
|
|
value >>= AT_WORD_RIGHT_SHIFT;
|
|
if (fixp->fx_size == 2)
|
|
bfd_putb16 ((bfd_vma) value, (unsigned char *) where);
|
|
else
|
|
{
|
|
insn = d10v_insert_operand (insn, op_type, (offsetT)value, left, fixp);
|
|
bfd_putb32 ((bfd_vma) insn, (unsigned char *) where);
|
|
}
|
|
break;
|
|
case BFD_RELOC_32:
|
|
bfd_putb32 ((bfd_vma) value, (unsigned char *) where);
|
|
break;
|
|
case BFD_RELOC_16:
|
|
bfd_putb16 ((bfd_vma) value, (unsigned char *) where);
|
|
break;
|
|
default:
|
|
as_fatal ("line %d: unknown relocation type: 0x%x",fixp->fx_line,fixp->fx_r_type);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
/* d10v_cleanup() is called after the assembler has finished parsing the input
|
|
file or after a label is defined. Because the D10V assembler sometimes saves short
|
|
instructions to see if it can package them with the next instruction, there may
|
|
be a short instruction that still needs written. */
|
|
int
|
|
d10v_cleanup ()
|
|
{
|
|
segT seg;
|
|
subsegT subseg;
|
|
|
|
if (prev_opcode)
|
|
{
|
|
seg = now_seg;
|
|
subseg = now_subseg;
|
|
subseg_set (prev_seg, prev_subseg);
|
|
write_1_short (prev_opcode, prev_insn, fixups->next);
|
|
subseg_set (seg, subseg);
|
|
prev_opcode = NULL;
|
|
}
|
|
return 1;
|
|
}
|
|
|
|
/* Like normal .word, except support @word */
|
|
/* clobbers input_line_pointer, checks end-of-line. */
|
|
static void
|
|
d10v_dot_word (nbytes)
|
|
register int nbytes; /* 1=.byte, 2=.word, 4=.long */
|
|
{
|
|
expressionS exp;
|
|
bfd_reloc_code_real_type reloc;
|
|
char *p;
|
|
int offset;
|
|
|
|
if (is_it_end_of_statement ())
|
|
{
|
|
demand_empty_rest_of_line ();
|
|
return;
|
|
}
|
|
|
|
do
|
|
{
|
|
expression (&exp);
|
|
if (!strncasecmp (input_line_pointer, "@word", 5))
|
|
{
|
|
exp.X_add_number = 0;
|
|
input_line_pointer += 5;
|
|
|
|
p = frag_more (2);
|
|
fix_new_exp (frag_now, p - frag_now->fr_literal, 2,
|
|
&exp, 0, BFD_RELOC_D10V_18);
|
|
}
|
|
else
|
|
emit_expr (&exp, 2);
|
|
}
|
|
while (*input_line_pointer++ == ',');
|
|
|
|
input_line_pointer--; /* Put terminator back into stream. */
|
|
demand_empty_rest_of_line ();
|
|
}
|
|
|
|
|
|
/* Mitsubishi asked that we support some old syntax that apparently */
|
|
/* had immediate operands starting with '#'. This is in some of their */
|
|
/* sample code but is not documented (although it appears in some */
|
|
/* examples in their assembler manual). For now, we'll solve this */
|
|
/* compatibility problem by simply ignoring any '#' at the beginning */
|
|
/* of an operand. */
|
|
|
|
/* operands that begin with '#' should fall through to here */
|
|
/* from expr.c */
|
|
|
|
void
|
|
md_operand (expressionP)
|
|
expressionS *expressionP;
|
|
{
|
|
if (*input_line_pointer == '#')
|
|
{
|
|
input_line_pointer++;
|
|
expression (expressionP);
|
|
}
|
|
}
|
|
|