mirror of
https://github.com/darlinghq/darling-gdb.git
synced 2024-11-26 05:20:30 +00:00
88b38f0c3c
to *info->symbols.
* mips-dis.c (print_insn_{big,little}_mips): Likewise.
* tic30-dis.c (print_branch): Likewise.
start-sanitize-sky
* mips-dis.c (print_insn_little_mips): Call dvp_info_mach_type.
* dvp-dis.c (dvp_info_mach_type): New function.
(print_insn_dvp): Call it.
(print_vif): Return length of 4 if mpg or direct insn so following
insns get properly disabled.
* dvp-opc.c (vif_insn_len): New argument `pcpu'. All callers updated.
end-sanitize-sky
821 lines
21 KiB
C
821 lines
21 KiB
C
/* Instruction printing code for the ARM
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Copyright (C) 1994, 95, 96, 1997 Free Software Foundation, Inc.
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Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
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Modification by James G. Smith (jsmith@cygnus.co.uk)
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This file is part of libopcodes.
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This program is free software; you can redistribute it and/or modify it under
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the terms of the GNU General Public License as published by the Free
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Software Foundation; either version 2 of the License, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#include "dis-asm.h"
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#define DEFINE_TABLE
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#include "arm-opc.h"
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#include "coff/internal.h"
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#include "libcoff.h"
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static char *arm_conditional[] =
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{"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
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"hi", "ls", "ge", "lt", "gt", "le", "", "nv"};
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static char *arm_regnames[] =
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{"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
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"r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc"};
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static char *arm_fp_const[] =
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{"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
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static char *arm_shift[] =
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{"lsl", "lsr", "asr", "ror"};
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static int print_insn_arm PARAMS ((bfd_vma, struct disassemble_info *,
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long));
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static void
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arm_decode_shift (given, func, stream)
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long given;
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fprintf_ftype func;
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void *stream;
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{
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func (stream, "%s", arm_regnames[given & 0xf]);
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if ((given & 0xff0) != 0)
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{
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if ((given & 0x10) == 0)
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{
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int amount = (given & 0xf80) >> 7;
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int shift = (given & 0x60) >> 5;
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if (amount == 0)
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{
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if (shift == 3)
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{
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func (stream, ", rrx");
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return;
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}
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amount = 32;
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}
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func (stream, ", %s #%d", arm_shift[shift], amount);
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}
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else
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func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
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arm_regnames[(given & 0xf00) >> 8]);
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}
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}
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/* Print one instruction from PC on INFO->STREAM.
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Return the size of the instruction (always 4 on ARM). */
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static int
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print_insn_arm (pc, info, given)
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bfd_vma pc;
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struct disassemble_info *info;
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long given;
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{
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struct arm_opcode *insn;
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void *stream = info->stream;
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fprintf_ftype func = info->fprintf_func;
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for (insn = arm_opcodes; insn->assembler; insn++)
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{
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if ((given & insn->mask) == insn->value)
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{
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char *c;
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for (c = insn->assembler; *c; c++)
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{
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if (*c == '%')
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{
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switch (*++c)
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{
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case '%':
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func (stream, "%%");
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break;
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case 'a':
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if (((given & 0x000f0000) == 0x000f0000)
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&& ((given & 0x02000000) == 0))
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{
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int offset = given & 0xfff;
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if ((given & 0x00800000) == 0)
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offset = -offset;
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(*info->print_address_func)
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(offset + pc + 8, info);
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}
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else
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{
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func (stream, "[%s",
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arm_regnames[(given >> 16) & 0xf]);
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if ((given & 0x01000000) != 0)
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{
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if ((given & 0x02000000) == 0)
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{
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int offset = given & 0xfff;
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if (offset)
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func (stream, ", %s#%d",
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(((given & 0x00800000) == 0)
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? "-" : ""), offset);
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}
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else
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{
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func (stream, ", %s",
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(((given & 0x00800000) == 0)
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? "-" : ""));
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arm_decode_shift (given, func, stream);
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}
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func (stream, "]%s",
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((given & 0x00200000) != 0) ? "!" : "");
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}
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else
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{
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if ((given & 0x02000000) == 0)
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{
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int offset = given & 0xfff;
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if (offset)
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func (stream, "], %s#%d",
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(((given & 0x00800000) == 0)
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? "-" : ""), offset);
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else
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func (stream, "]");
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}
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else
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{
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func (stream, "], %s",
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(((given & 0x00800000) == 0)
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? "-" : ""));
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arm_decode_shift (given, func, stream);
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}
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}
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}
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break;
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case 's':
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if ((given & 0x004f0000) == 0x004f0000)
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{
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/* PC relative with immediate offset */
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int offset = ((given & 0xf00) >> 4) | (given & 0xf);
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if ((given & 0x00800000) == 0)
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offset = -offset;
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(*info->print_address_func)
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(offset + pc + 8, info);
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}
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else
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{
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func (stream, "[%s",
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arm_regnames[(given >> 16) & 0xf]);
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if ((given & 0x01000000) != 0)
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{
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/* pre-indexed */
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if ((given & 0x00400000) == 0x00400000)
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{
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/* immediate */
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int offset = ((given & 0xf00) >> 4) | (given & 0xf);
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if (offset)
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func (stream, ", %s#%d",
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(((given & 0x00800000) == 0)
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? "-" : ""), offset);
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}
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else
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{
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/* register */
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func (stream, ", %s%s",
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(((given & 0x00800000) == 0)
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? "-" : ""),
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arm_regnames[given & 0xf]);
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}
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func (stream, "]%s",
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((given & 0x00200000) != 0) ? "!" : "");
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}
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else
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{
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/* post-indexed */
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if ((given & 0x00400000) == 0x00400000)
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{
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/* immediate */
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int offset = ((given & 0xf00) >> 4) | (given & 0xf);
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if (offset)
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func (stream, "], %s#%d",
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(((given & 0x00800000) == 0)
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? "-" : ""), offset);
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else
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func (stream, "]");
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}
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else
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{
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/* register */
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func (stream, "], %s%s",
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(((given & 0x00800000) == 0)
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? "-" : ""),
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arm_regnames[given & 0xf]);
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}
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}
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}
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break;
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case 'b':
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(*info->print_address_func)
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(BDISP (given) * 4 + pc + 8, info);
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break;
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case 'c':
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func (stream, "%s",
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arm_conditional [(given >> 28) & 0xf]);
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break;
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case 'm':
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{
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int started = 0;
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int reg;
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func (stream, "{");
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for (reg = 0; reg < 16; reg++)
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if ((given & (1 << reg)) != 0)
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{
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if (started)
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func (stream, ", ");
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started = 1;
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func (stream, "%s", arm_regnames[reg]);
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}
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func (stream, "}");
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}
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break;
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case 'o':
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if ((given & 0x02000000) != 0)
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{
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int rotate = (given & 0xf00) >> 7;
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int immed = (given & 0xff);
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func (stream, "#%d",
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((immed << (32 - rotate))
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| (immed >> rotate)) & 0xffffffff);
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}
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else
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arm_decode_shift (given, func, stream);
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break;
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case 'p':
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if ((given & 0x0000f000) == 0x0000f000)
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func (stream, "p");
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break;
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case 't':
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if ((given & 0x01200000) == 0x00200000)
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func (stream, "t");
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break;
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case 'h':
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if ((given & 0x00000020) == 0x00000020)
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func (stream, "h");
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else
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func (stream, "b");
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break;
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case 'A':
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func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
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if ((given & 0x01000000) != 0)
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{
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int offset = given & 0xff;
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if (offset)
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func (stream, ", %s#%d]%s",
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((given & 0x00800000) == 0 ? "-" : ""),
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offset * 4,
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((given & 0x00200000) != 0 ? "!" : ""));
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else
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func (stream, "]");
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}
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else
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{
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int offset = given & 0xff;
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if (offset)
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func (stream, "], %s#%d",
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((given & 0x00800000) == 0 ? "-" : ""),
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offset * 4);
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else
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func (stream, "]");
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}
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break;
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case 'C':
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switch (given & 0x00090000)
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{
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case 0:
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func (stream, "_???");
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break;
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case 0x10000:
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func (stream, "_ctl");
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break;
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case 0x80000:
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func (stream, "_flg");
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break;
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}
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break;
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case 'F':
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switch (given & 0x00408000)
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{
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case 0:
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func (stream, "4");
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break;
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case 0x8000:
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func (stream, "1");
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break;
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case 0x00400000:
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func (stream, "2");
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break;
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default:
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func (stream, "3");
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}
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break;
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case 'P':
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switch (given & 0x00080080)
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{
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case 0:
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func (stream, "s");
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break;
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case 0x80:
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func (stream, "d");
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break;
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case 0x00080000:
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func (stream, "e");
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break;
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default:
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func (stream, "<illegal precision>");
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break;
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}
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break;
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case 'Q':
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switch (given & 0x00408000)
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{
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case 0:
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func (stream, "s");
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break;
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case 0x8000:
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func (stream, "d");
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break;
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case 0x00400000:
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func (stream, "e");
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break;
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default:
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func (stream, "p");
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break;
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}
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break;
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case 'R':
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switch (given & 0x60)
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{
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case 0:
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break;
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case 0x20:
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func (stream, "p");
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break;
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case 0x40:
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func (stream, "m");
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break;
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default:
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func (stream, "z");
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break;
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}
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break;
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case '0': case '1': case '2': case '3': case '4':
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case '5': case '6': case '7': case '8': case '9':
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{
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int bitstart = *c++ - '0';
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int bitend = 0;
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while (*c >= '0' && *c <= '9')
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bitstart = (bitstart * 10) + *c++ - '0';
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switch (*c)
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{
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case '-':
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c++;
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while (*c >= '0' && *c <= '9')
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bitend = (bitend * 10) + *c++ - '0';
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if (!bitend)
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abort ();
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switch (*c)
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{
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case 'r':
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{
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long reg;
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reg = given >> bitstart;
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reg &= (2 << (bitend - bitstart)) - 1;
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func (stream, "%s", arm_regnames[reg]);
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}
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break;
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case 'd':
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{
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long reg;
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reg = given >> bitstart;
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reg &= (2 << (bitend - bitstart)) - 1;
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func (stream, "%d", reg);
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}
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break;
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case 'x':
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{
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long reg;
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reg = given >> bitstart;
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reg &= (2 << (bitend - bitstart)) - 1;
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func (stream, "0x%08x", reg);
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}
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break;
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case 'f':
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|
{
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long reg;
|
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reg = given >> bitstart;
|
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reg &= (2 << (bitend - bitstart)) - 1;
|
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if (reg > 7)
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func (stream, "#%s",
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arm_fp_const[reg & 7]);
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else
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func (stream, "f%d", reg);
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|
}
|
|
break;
|
|
default:
|
|
abort ();
|
|
}
|
|
break;
|
|
case '`':
|
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c++;
|
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if ((given & (1 << bitstart)) == 0)
|
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func (stream, "%c", *c);
|
|
break;
|
|
case '\'':
|
|
c++;
|
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if ((given & (1 << bitstart)) != 0)
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|
func (stream, "%c", *c);
|
|
break;
|
|
case '?':
|
|
++c;
|
|
if ((given & (1 << bitstart)) != 0)
|
|
func (stream, "%c", *c++);
|
|
else
|
|
func (stream, "%c", *++c);
|
|
break;
|
|
default:
|
|
abort ();
|
|
}
|
|
break;
|
|
|
|
default:
|
|
abort ();
|
|
}
|
|
}
|
|
}
|
|
else
|
|
func (stream, "%c", *c);
|
|
}
|
|
return 4;
|
|
}
|
|
}
|
|
abort ();
|
|
}
|
|
|
|
/* Print one instruction from PC on INFO->STREAM.
|
|
Return the size of the instruction. */
|
|
|
|
static int
|
|
print_insn_thumb (pc, info, given)
|
|
bfd_vma pc;
|
|
struct disassemble_info *info;
|
|
long given;
|
|
{
|
|
struct thumb_opcode *insn;
|
|
void *stream = info->stream;
|
|
fprintf_ftype func = info->fprintf_func;
|
|
|
|
for (insn = thumb_opcodes; insn->assembler; insn++)
|
|
{
|
|
if ((given & insn->mask) == insn->value)
|
|
{
|
|
char *c = insn->assembler;
|
|
|
|
/* Special processing for Thumb 2 instruction BL sequence: */
|
|
if (!*c) /* check for empty (not NULL) assembler string */
|
|
{
|
|
info->bytes_per_chunk = 4;
|
|
info->bytes_per_line = 4;
|
|
|
|
func (stream, "%04x\tbl\t", given & 0xffff);
|
|
(*info->print_address_func)
|
|
(BDISP23 (given) * 2 + pc + 4, info);
|
|
return 4;
|
|
}
|
|
else
|
|
{
|
|
info->bytes_per_chunk = 2;
|
|
info->bytes_per_line = 4;
|
|
|
|
given &= 0xffff;
|
|
func (stream, "%04x\t", given);
|
|
for (; *c; c++)
|
|
{
|
|
if (*c == '%')
|
|
{
|
|
int domaskpc = 0;
|
|
int domasklr = 0;
|
|
switch (*++c)
|
|
{
|
|
case '%':
|
|
func (stream, "%%");
|
|
break;
|
|
|
|
case 'S':
|
|
{
|
|
long reg;
|
|
reg = (given >> 3) & 0x7;
|
|
if (given & (1 << 6))
|
|
reg += 8;
|
|
func (stream, "%s", arm_regnames[reg]);
|
|
}
|
|
break;
|
|
|
|
case 'D':
|
|
{
|
|
long reg;
|
|
reg = given & 0x7;
|
|
if (given & (1 << 7))
|
|
reg += 8;
|
|
func (stream, "%s", arm_regnames[reg]);
|
|
}
|
|
break;
|
|
|
|
case 'T':
|
|
func (stream, "%s",
|
|
arm_conditional [(given >> 8) & 0xf]);
|
|
break;
|
|
|
|
case 'N':
|
|
if (given & (1 << 8))
|
|
domasklr = 1;
|
|
/* fall through */
|
|
case 'O':
|
|
if (*c == 'O' && (given & (1 << 8)))
|
|
domaskpc = 1;
|
|
/* fall through */
|
|
case 'M':
|
|
{
|
|
int started = 0;
|
|
int reg;
|
|
func (stream, "{");
|
|
/* It would be nice if we could spot
|
|
ranges, and generate the rS-rE format: */
|
|
for (reg = 0; (reg < 8); reg++)
|
|
if ((given & (1 << reg)) != 0)
|
|
{
|
|
if (started)
|
|
func (stream, ", ");
|
|
started = 1;
|
|
func (stream, "%s", arm_regnames[reg]);
|
|
}
|
|
|
|
if (domasklr)
|
|
{
|
|
if (started)
|
|
func (stream, ", ");
|
|
started = 1;
|
|
func (stream, "lr");
|
|
}
|
|
|
|
if (domaskpc)
|
|
{
|
|
if (started)
|
|
func (stream, ", ");
|
|
func (stream, "pc");
|
|
}
|
|
|
|
func (stream, "}");
|
|
}
|
|
break;
|
|
|
|
|
|
case '0': case '1': case '2': case '3': case '4':
|
|
case '5': case '6': case '7': case '8': case '9':
|
|
{
|
|
int bitstart = *c++ - '0';
|
|
int bitend = 0;
|
|
while (*c >= '0' && *c <= '9')
|
|
bitstart = (bitstart * 10) + *c++ - '0';
|
|
|
|
switch (*c)
|
|
{
|
|
case '-':
|
|
{
|
|
long reg;
|
|
c++;
|
|
while (*c >= '0' && *c <= '9')
|
|
bitend = (bitend * 10) + *c++ - '0';
|
|
if (!bitend)
|
|
abort ();
|
|
reg = given >> bitstart;
|
|
reg &= (2 << (bitend - bitstart)) - 1;
|
|
switch (*c)
|
|
{
|
|
case 'r':
|
|
func (stream, "%s", arm_regnames[reg]);
|
|
break;
|
|
|
|
case 'd':
|
|
func (stream, "%d", reg);
|
|
break;
|
|
|
|
case 'H':
|
|
func (stream, "%d", reg << 1);
|
|
break;
|
|
|
|
case 'W':
|
|
func (stream, "%d", reg << 2);
|
|
break;
|
|
|
|
case 'a':
|
|
info->print_address_func (((pc + 4) & ~1) + (reg << 2), info);
|
|
break;
|
|
|
|
case 'x':
|
|
func (stream, "0x%04x", reg);
|
|
break;
|
|
|
|
case 'I':
|
|
reg = ((reg ^ (1 << bitend)) - (1 << bitend));
|
|
func (stream, "%d", reg);
|
|
break;
|
|
|
|
case 'B':
|
|
reg = ((reg ^ (1 << bitend)) - (1 << bitend));
|
|
(*info->print_address_func)
|
|
(reg * 2 + pc + 4, info);
|
|
break;
|
|
|
|
default:
|
|
abort();
|
|
}
|
|
}
|
|
break;
|
|
|
|
case '\'':
|
|
c++;
|
|
if ((given & (1 << bitstart)) != 0)
|
|
func (stream, "%c", *c);
|
|
break;
|
|
|
|
case '?':
|
|
++c;
|
|
if ((given & (1 << bitstart)) != 0)
|
|
func (stream, "%c", *c++);
|
|
else
|
|
func (stream, "%c", *++c);
|
|
break;
|
|
|
|
default:
|
|
abort();
|
|
}
|
|
}
|
|
break;
|
|
|
|
default:
|
|
abort ();
|
|
}
|
|
}
|
|
else
|
|
func (stream, "%c", *c);
|
|
}
|
|
}
|
|
return 2;
|
|
}
|
|
}
|
|
|
|
/* no match */
|
|
abort ();
|
|
}
|
|
|
|
/* NOTE: There are no checks in these routines that the relevant number of data bytes exist */
|
|
|
|
int
|
|
print_insn_big_arm (pc, info)
|
|
bfd_vma pc;
|
|
struct disassemble_info *info;
|
|
{
|
|
unsigned char b[4];
|
|
long given;
|
|
int status;
|
|
coff_symbol_type * cs;
|
|
int is_thumb;
|
|
|
|
cs = coffsymbol (*info->symbols);
|
|
is_thumb = (cs != NULL) &&
|
|
( cs->native->u.syment.n_sclass == C_THUMBEXT
|
|
|| cs->native->u.syment.n_sclass == C_THUMBSTAT
|
|
|| cs->native->u.syment.n_sclass == C_THUMBLABEL
|
|
|| cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
|
|
|| cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
|
|
|
|
info->bytes_per_chunk = 4;
|
|
info->display_endian = BFD_ENDIAN_BIG;
|
|
|
|
/* Always fetch word aligned values. */
|
|
|
|
status = (*info->read_memory_func) (pc & ~ 0x3, (bfd_byte *) &b[0], 4, info);
|
|
if (status != 0)
|
|
{
|
|
(*info->memory_error_func) (status, pc, info);
|
|
return -1;
|
|
}
|
|
|
|
if (is_thumb)
|
|
{
|
|
if (pc & 0x2)
|
|
{
|
|
given = (b[2] << 8) | b[3];
|
|
|
|
status = info->read_memory_func ((pc + 4) & ~ 0x3, (bfd_byte *) b, 4, info);
|
|
if (status != 0)
|
|
{
|
|
info->memory_error_func (status, pc + 4, info);
|
|
return -1;
|
|
}
|
|
|
|
given |= (b[0] << 24) | (b[1] << 16);
|
|
}
|
|
else
|
|
{
|
|
given = (b[0] << 8) | b[1] | (b[2] << 24) | (b[3] << 16);
|
|
}
|
|
}
|
|
else
|
|
{
|
|
given = (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | (b[3]);
|
|
}
|
|
|
|
if (is_thumb)
|
|
{
|
|
status = print_insn_thumb (pc, info, given);
|
|
}
|
|
else
|
|
{
|
|
status = print_insn_arm (pc, info, given);
|
|
}
|
|
|
|
return status;
|
|
}
|
|
|
|
int
|
|
print_insn_little_arm (pc, info)
|
|
bfd_vma pc;
|
|
struct disassemble_info * info;
|
|
{
|
|
unsigned char b[4];
|
|
long given;
|
|
int status;
|
|
coff_symbol_type * cs;
|
|
int is_thumb;
|
|
|
|
cs = coffsymbol (*info->symbols);
|
|
is_thumb = (cs != NULL) &&
|
|
( cs->native->u.syment.n_sclass == C_THUMBEXT
|
|
|| cs->native->u.syment.n_sclass == C_THUMBSTAT
|
|
|| cs->native->u.syment.n_sclass == C_THUMBLABEL
|
|
|| cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
|
|
|| cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
|
|
|
|
info->bytes_per_chunk = 4;
|
|
info->display_endian = BFD_ENDIAN_LITTLE;
|
|
|
|
status = (*info->read_memory_func) (pc, (bfd_byte *) &b[0], 4, info);
|
|
if (status != 0 && is_thumb)
|
|
{
|
|
info->bytes_per_chunk = 2;
|
|
|
|
status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
|
|
b[3] = b[2] = 0;
|
|
}
|
|
if (status != 0)
|
|
{
|
|
(*info->memory_error_func) (status, pc, info);
|
|
return -1;
|
|
}
|
|
|
|
given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
|
|
|
|
if (is_thumb)
|
|
{
|
|
status = print_insn_thumb (pc, info, given);
|
|
}
|
|
else
|
|
{
|
|
status = print_insn_arm (pc, info, given);
|
|
}
|
|
|
|
return status;
|
|
}
|