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8a3fe4f86c
Mark up all error and warning messages. * ada-lang.c, amd64-tdep.c, arch-utils.c, breakpoint.c: Update. * bsd-kvm.c, bsd-uthread.c, coff-solib.h, coffread.c: Update. * core-aout.c, core-regset.c, corefile.c, corelow.c: Update. * cp-abi.c, cp-support.c, cp-valprint.c, cris-tdep.c: Update. * dbxread.c, demangle.c, doublest.c, dsrec.c: Update. * dve3900-rom.c, dwarf2expr.c, dwarf2loc.c: Update. * dwarf2read.c, dwarfread.c, elfread.c, eval.c: Update. * event-top.c, exec.c, expprint.c, f-lang.c: Update. * f-typeprint.c, f-valprint.c, fbsd-nat.c, findvar.c: Update. * frame.c, frv-linux-tdep.c, gcore.c, gdbtypes.c: Update. * gnu-nat.c, gnu-v2-abi.c, gnu-v3-abi.c, go32-nat.c: Update. * hpacc-abi.c, hppa-hpux-nat.c, hppa-hpux-tdep.c: Update. * hppa-linux-nat.c, hppa-linux-tdep.c, hppa-tdep.c: Update. * hpread.c, hpux-thread.c, i386-linux-nat.c: Update. * i386-linux-tdep.c, i386-tdep.c, i386bsd-nat.c: Update. * i386gnu-nat.c, i387-tdep.c, ia64-linux-nat.c: Update. * ia64-tdep.c, inf-child.c, inf-ptrace.c, inf-ttrace.c: Update. * infcall.c, infcmd.c, inflow.c, infptrace.c, infrun.c: Update. * inftarg.c, interps.c, irix5-nat.c, jv-lang.c: Update. * kod-cisco.c, kod.c, language.c, libunwind-frame.c: Update. * linespec.c, linux-nat.c, linux-thread-db.c, m2-lang.c: Update. * m32r-rom.c, m68hc11-tdep.c, m68k-tdep.c: Update. * m68klinux-nat.c, macrocmd.c, macroexp.c, main.c: Update. * maint.c, mdebugread.c, mem-break.c, memattr.c: Update. * mips-linux-tdep.c, mips-tdep.c, mipsread.c, monitor.c: Update. * nlmread.c, nto-procfs.c, objc-lang.c, objfiles.c: Update. * observer.c, ocd.c, p-lang.c, p-typeprint.c: Update. * p-valprint.c, pa64solib.c, parse.c, ppc-linux-tdep.c: Update. * ppcnbsd-tdep.c, printcmd.c, procfs.c, remote-e7000.c: Update. * remote-fileio.c, remote-m32r-sdi.c, remote-rdi.c: Update. * remote-rdp.c, remote-sim.c, remote-st.c: Update. * remote-utils.c, remote-utils.h, remote.c: Update. * rom68k-rom.c, rs6000-nat.c, s390-tdep.c, scm-lang.c: Update. * ser-e7kpc.c, ser-tcp.c, ser-unix.c, sh-tdep.c: Update. * sh3-rom.c, shnbsd-tdep.c, sol-thread.c, solib-aix5.c: Update. * solib-frv.c, solib-irix.c, solib-osf.c, solib-pa64.c: Update. * solib-som.c, solib-sunos.c, solib-svr4.c, solib.c: Update. * somread.c, somsolib.c, source.c, stabsread.c: Update. * stack.c, std-regs.c, symfile-mem.c, symfile.c: Update. * symmisc.c, symtab.c, target.c, thread.c, top.c: Update. * tracepoint.c, trad-frame.c, typeprint.c, utils.c: Update. * uw-thread.c, valarith.c, valops.c, valprint.c: Update. * value.c, varobj.c, version.in, win32-nat.c, wince.c: Update. * xcoffread.c, xcoffsolib.c, cli/cli-cmds.c: Update. * cli/cli-decode.c, cli/cli-dump.c, cli/cli-logging.c: Update. * cli/cli-script.c, cli/cli-setshow.c, mi/mi-cmd-break.c: Update. * mi/mi-cmd-disas.c, mi/mi-cmd-env.c, mi/mi-cmd-file.c: Update. * mi/mi-cmd-stack.c, mi/mi-cmd-var.c, mi/mi-getopt.c: Update. * mi/mi-symbol-cmds.c, tui/tui-layout.c, tui/tui-stack.c: Update. * tui/tui-win.c: Update.
277 lines
8.0 KiB
C
277 lines
8.0 KiB
C
/* Native support for the SGI Iris running IRIX version 5, for GDB.
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Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996,
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1998, 1999, 2000, 2001, 2002, 2004 Free Software Foundation, Inc.
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Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
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and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
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Implemented for Irix 4.x by Garrett A. Wollman.
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Modified for Irix 5.x by Ian Lance Taylor.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330,
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Boston, MA 02111-1307, USA. */
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#include "defs.h"
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#include "inferior.h"
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#include "gdbcore.h"
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#include "target.h"
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#include "regcache.h"
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#include "gdb_string.h"
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#include <sys/time.h>
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#include <sys/procfs.h>
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#include <setjmp.h> /* For JB_XXX. */
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/* Prototypes for supply_gregset etc. */
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#include "gregset.h"
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#include "mips-tdep.h"
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static void fetch_core_registers (char *, unsigned int, int, CORE_ADDR);
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/* Size of elements in jmpbuf */
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#define JB_ELEMENT_SIZE 4
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/*
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* See the comment in m68k-tdep.c regarding the utility of these functions.
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*
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* These definitions are from the MIPS SVR4 ABI, so they may work for
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* any MIPS SVR4 target.
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*/
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void
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supply_gregset (gregset_t *gregsetp)
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{
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int regi;
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greg_t *regp = &(*gregsetp)[0];
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int gregoff = sizeof (greg_t) - mips_isa_regsize (current_gdbarch);
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static char zerobuf[32] = {0};
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for (regi = 0; regi <= CTX_RA; regi++)
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regcache_raw_supply (current_regcache, regi,
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(char *) (regp + regi) + gregoff);
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regcache_raw_supply (current_regcache, mips_regnum (current_gdbarch)->pc,
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(char *) (regp + CTX_EPC) + gregoff);
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regcache_raw_supply (current_regcache, mips_regnum (current_gdbarch)->hi,
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(char *) (regp + CTX_MDHI) + gregoff);
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regcache_raw_supply (current_regcache, mips_regnum (current_gdbarch)->lo,
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(char *) (regp + CTX_MDLO) + gregoff);
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regcache_raw_supply (current_regcache, mips_regnum (current_gdbarch)->cause,
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(char *) (regp + CTX_CAUSE) + gregoff);
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/* Fill inaccessible registers with zero. */
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regcache_raw_supply (current_regcache, mips_regnum (current_gdbarch)->badvaddr, zerobuf);
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}
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void
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fill_gregset (gregset_t *gregsetp, int regno)
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{
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int regi;
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greg_t *regp = &(*gregsetp)[0];
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LONGEST regval;
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/* Under Irix6, if GDB is built with N32 ABI and is debugging an O32
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executable, we have to sign extend the registers to 64 bits before
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filling in the gregset structure. */
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for (regi = 0; regi <= CTX_RA; regi++)
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if ((regno == -1) || (regno == regi))
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{
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regcache_raw_read_signed (current_regcache, regi, ®val);
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*(regp + regi) = regval;
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}
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if ((regno == -1) || (regno == PC_REGNUM))
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{
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regcache_raw_read_signed
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(current_regcache, mips_regnum (current_gdbarch)->pc, ®val);
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*(regp + CTX_EPC) = regval;
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}
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if ((regno == -1) || (regno == mips_regnum (current_gdbarch)->cause))
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{
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regcache_raw_read_signed
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(current_regcache, mips_regnum (current_gdbarch)->cause, ®val);
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*(regp + CTX_CAUSE) = regval;
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}
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if ((regno == -1)
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|| (regno == mips_regnum (current_gdbarch)->hi))
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{
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regcache_raw_read_signed
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(current_regcache, mips_regnum (current_gdbarch)->hi, ®val);
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*(regp + CTX_MDHI) = regval;
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}
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if ((regno == -1) || (regno == mips_regnum (current_gdbarch)->lo))
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{
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regcache_raw_read_signed
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(current_regcache, mips_regnum (current_gdbarch)->lo, ®val);
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*(regp + CTX_MDLO) = regval;
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}
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}
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/*
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* Now we do the same thing for floating-point registers.
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* We don't bother to condition on FP0_REGNUM since any
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* reasonable MIPS configuration has an R3010 in it.
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*
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* Again, see the comments in m68k-tdep.c.
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*/
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void
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supply_fpregset (fpregset_t *fpregsetp)
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{
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int regi;
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static char zerobuf[32] = {0};
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/* FIXME, this is wrong for the N32 ABI which has 64 bit FP regs. */
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for (regi = 0; regi < 32; regi++)
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regcache_raw_supply (current_regcache, FP0_REGNUM + regi,
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(char *) &fpregsetp->fp_r.fp_regs[regi]);
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regcache_raw_supply (current_regcache,
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mips_regnum (current_gdbarch)->fp_control_status,
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(char *) &fpregsetp->fp_csr);
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/* FIXME: how can we supply FCRIR? SGI doesn't tell us. */
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regcache_raw_supply (current_regcache,
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mips_regnum (current_gdbarch)->fp_implementation_revision,
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zerobuf);
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}
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void
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fill_fpregset (fpregset_t *fpregsetp, int regno)
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{
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int regi;
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char *from, *to;
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/* FIXME, this is wrong for the N32 ABI which has 64 bit FP regs. */
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for (regi = FP0_REGNUM; regi < FP0_REGNUM + 32; regi++)
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{
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if ((regno == -1) || (regno == regi))
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{
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to = (char *) &(fpregsetp->fp_r.fp_regs[regi - FP0_REGNUM]);
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regcache_raw_read (current_regcache, regi, to);
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}
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}
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if ((regno == -1)
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|| (regno == mips_regnum (current_gdbarch)->fp_control_status))
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regcache_raw_read (current_regcache,
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mips_regnum (current_gdbarch)->fp_control_status,
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&fpregsetp->fp_csr);
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}
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/* Figure out where the longjmp will land.
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We expect the first arg to be a pointer to the jmp_buf structure from which
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we extract the pc (JB_PC) that we will land at. The pc is copied into PC.
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This routine returns true on success. */
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int
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get_longjmp_target (CORE_ADDR *pc)
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{
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char *buf;
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CORE_ADDR jb_addr;
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buf = alloca (TARGET_PTR_BIT / TARGET_CHAR_BIT);
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jb_addr = read_register (MIPS_A0_REGNUM);
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if (target_read_memory (jb_addr + JB_PC * JB_ELEMENT_SIZE, buf,
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TARGET_PTR_BIT / TARGET_CHAR_BIT))
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return 0;
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*pc = extract_unsigned_integer (buf, TARGET_PTR_BIT / TARGET_CHAR_BIT);
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return 1;
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}
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/* Provide registers to GDB from a core file.
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CORE_REG_SECT points to an array of bytes, which were obtained from
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a core file which BFD thinks might contain register contents.
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CORE_REG_SIZE is its size.
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Normally, WHICH says which register set corelow suspects this is:
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0 --- the general-purpose register set
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2 --- the floating-point register set
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However, for Irix 5, WHICH isn't used.
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REG_ADDR is also unused. */
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static void
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fetch_core_registers (char *core_reg_sect, unsigned core_reg_size,
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int which, CORE_ADDR reg_addr)
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{
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char *srcp = core_reg_sect;
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int regno;
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if (core_reg_size == deprecated_register_bytes ())
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{
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for (regno = 0; regno < NUM_REGS; regno++)
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{
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regcache_raw_write (current_regcache, regno, srcp);
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srcp += register_size (current_gdbarch, regno);
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}
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}
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else if (mips_isa_regsize (current_gdbarch) == 4 &&
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core_reg_size == (2 * mips_isa_regsize (current_gdbarch)) * NUM_REGS)
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{
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/* This is a core file from a N32 executable, 64 bits are saved
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for all registers. */
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for (regno = 0; regno < NUM_REGS; regno++)
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{
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if (regno >= FP0_REGNUM && regno < (FP0_REGNUM + 32))
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{
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regcache_raw_write (current_regcache, regno, srcp);
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}
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else
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{
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regcache_raw_write (current_regcache, regno, srcp + 4);
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}
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srcp += 8;
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}
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}
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else
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{
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warning (_("wrong size gregset struct in core file"));
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return;
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}
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}
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/* Register that we are able to handle irix5 core file formats.
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This really is bfd_target_unknown_flavour */
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static struct core_fns irix5_core_fns =
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{
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bfd_target_unknown_flavour, /* core_flavour */
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default_check_format, /* check_format */
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default_core_sniffer, /* core_sniffer */
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fetch_core_registers, /* core_read_registers */
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NULL /* next */
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};
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void
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_initialize_core_irix5 (void)
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{
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deprecated_add_core_fns (&irix5_core_fns);
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}
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