mirror of
https://github.com/darlinghq/darling-gdb.git
synced 2024-11-28 22:40:24 +00:00
187 lines
3.7 KiB
Plaintext
187 lines
3.7 KiB
Plaintext
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// Integer Instructions
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// --------------------
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//
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// MulAcc is the Multiply Accumulator.
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// This register is mapped on the the HI and LO registers.
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// Upper 32 bits of MulAcc is mapped on to lower 32 bits of HI register.
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// Lower 32 bits of MulAcc is mapped on to lower 32 bits of LO register.
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:function:::unsigned64:MulAcc:
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{
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unsigned64 result = U8_4 (HI, LO);
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return result;
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}
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:function:::void:SET_MulAcc:unsigned64 value
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{
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*AL4_8 (&HI) = VH4_8 (value);
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*AL4_8 (&LO) = VL4_8 (value);
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}
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:function:::signed64:SignedMultiply:signed32 l, signed32 r
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{
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signed64 result = (signed64) l * (signed64) r;
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return result;
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}
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:function:::unsigned64:UnsignedMultiply:unsigned32 l, unsigned32 r
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{
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unsigned64 result = (unsigned64) l * (unsigned64) r;
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return result;
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}
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:function:::unsigned64:Low32Bits:unsigned64 value
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{
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unsigned64 result = (signed64) (signed32) VL4_8 (value);
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return result;
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}
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:function:::unsigned64:High32Bits:unsigned64 value
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{
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unsigned64 result = (signed64) (signed32) VH4_8 (value);
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return result;
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}
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// Multiply, Accumulate
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000000,5.RS,5.RT,00000,00000,101000::::MAC
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"mac r<RS>, r<RT>"
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*vr4320:
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{
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SET_MulAcc (SD_, MulAcc (SD_) + SignedMultiply (SD_, GPR[RS], GPR[RT]));
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}
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// D-Multiply, Accumulate
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000000,5.RS,5.RT,00000,00000,101001::::DMAC
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"dmac r<RS>, r<RT>"
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*vr4320:
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{
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LO = LO + SignedMultiply (SD_, GPR[RS], GPR[RT]);
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}
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// Count Leading Zeros
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000000,5.RS,00000,5.RD,00000,110101::::CLZ
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"clz r<RD>, r<RS>"
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*vr4320:
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{
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unsigned32 t = Low32Bits (SD_, GPR[RS]);
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signed64 c = 0;
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while (! (t & ( 1 << 31))
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&& c < 32)
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{
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c++;
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t <<= 1;
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}
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GPR[RD] = c;
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}
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// D-Count Leading Zeros
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000000,5.RS,00000,5.RD,00000,111101::::DCLZ
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"dclz r<RD>, r<RS>"
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*vr4320:
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{
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unsigned64 t = GPR[RS];
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signed64 c = 0;
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while (! (t & ( (unsigned64)1 << 63))
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&& c < 64)
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{
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c++;
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t <<= 1;
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}
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printf("lo %d\n", (int) c);
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GPR[RD] = c;
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}
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// Multiply and Move LO.
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000000,5.RS,5.RT,5.RD,00100,101000::::MUL
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"mul r<RD>, r<RS>, r<RT>"
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*vr4320:
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{
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SET_MulAcc (SD_, 0 + SignedMultiply (SD_, GPR[RS], GPR[RT]));
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GPR[RD] = Low32Bits (SD_, MulAcc (SD_));
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}
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// Unsigned Multiply and Move LO.
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000000,5.RS,5.RT,5.RD,00101,101000::::MULU
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"mulu r<RD>, r<RS>, r<RT>"
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*vr4320:
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{
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SET_MulAcc (SD_, 0 + UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
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GPR[RD] = Low32Bits (SD_, MulAcc (SD_));
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}
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// Multiply and Move HI.
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000000,5.RS,5.RT,5.RD,01100,101000::::MULHI
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"mulhi r<RD>, r<RS>, r<RT>"
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*vr4320:
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{
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SET_MulAcc (SD_, 0 + SignedMultiply (SD_, GPR[RS], GPR[RT]));
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GPR[RD] = High32Bits (SD_, MulAcc (SD_));
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}
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// Unsigned Multiply and Move HI.
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000000,5.RS,5.RT,5.RD,01101,101000::::MULHIU
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"mulhiu r<RD>, r<RS>, r<RT>"
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*vr4320:
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{
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SET_MulAcc (SD_, 0 + UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
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GPR[RD] = High32Bits (SD_, MulAcc (SD_));
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}
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// Multiply, Accumulate and Move LO.
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000000,5.RS,5.RT,5.RD,00010,101000::::MACC
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"macc r<RD>, r<RS>, r<RT>"
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*vr4320:
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{
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SET_MulAcc (SD_, MulAcc (SD_) + SignedMultiply (SD_, GPR[RS], GPR[RT]));
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GPR[RD] = Low32Bits (SD_, MulAcc (SD_));
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}
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// Unsigned Multiply, Accumulate and Move LO.
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000000,5.RS,5.RT,5.RD,00011,101000::::MACCU
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"maccu r<RD>, r<RS>, r<RT>"
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*vr4320:
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{
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SET_MulAcc (SD_, MulAcc (SD_) + UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
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GPR[RD] = Low32Bits (SD_, MulAcc (SD_));
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}
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// Multiply, Accumulate and Move HI.
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000000,5.RS,5.RT,5.RD,01010,101000::::MACCHI
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"macchi r<RD>, r<RS>, r<RT>"
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*vr4320:
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{
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SET_MulAcc (SD_, MulAcc (SD_) + SignedMultiply (SD_, GPR[RS], GPR[RT]));
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GPR[RD] = High32Bits (SD_, MulAcc (SD_));
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}
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// Unsigned Multiply, Accumulate and Move HI.
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000000,5.RS,5.RT,5.RD,01011,101000::::MACCHIU
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"macchiu r<RD>, r<RS>, r<RT>"
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*vr4320:
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{
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SET_MulAcc (SD_, MulAcc (SD_) + UnsignedMultiply (SD_, GPR[RS], GPR[RT]));
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GPR[RD] = High32Bits (SD_, MulAcc (SD_));
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}
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