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357 lines
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357 lines
13 KiB
Plaintext
@c Copyright (C) 1991-2014 Free Software Foundation, Inc.
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@c This is part of the GAS manual.
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@c For copying conditions, see the file as.texinfo.
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@ifset GENERIC
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@page
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@node M32R-Dependent
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@chapter M32R Dependent Features
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@end ifset
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@ifclear GENERIC
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@node Machine Dependencies
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@chapter M32R Dependent Features
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@end ifclear
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@cindex M32R support
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@menu
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* M32R-Opts:: M32R Options
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* M32R-Directives:: M32R Directives
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* M32R-Warnings:: M32R Warnings
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@end menu
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@node M32R-Opts
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@section M32R Options
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@cindex options, M32R
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@cindex M32R options
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The Renease M32R version of @code{@value{AS}} has a few machine
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dependent options:
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@table @code
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@item -m32rx
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@cindex @samp{-m32rx} option, M32RX
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@cindex architecture options, M32RX
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@cindex M32R architecture options
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@code{@value{AS}} can assemble code for several different members of the
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Renesas M32R family. Normally the default is to assemble code for
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the M32R microprocessor. This option may be used to change the default
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to the M32RX microprocessor, which adds some more instructions to the
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basic M32R instruction set, and some additional parameters to some of
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the original instructions.
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@item -m32r2
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@cindex @samp{-m32rx} option, M32R2
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@cindex architecture options, M32R2
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@cindex M32R architecture options
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This option changes the target processor to the M32R2
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microprocessor.
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@item -m32r
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@cindex @samp{-m32r} option, M32R
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@cindex architecture options, M32R
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@cindex M32R architecture options
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This option can be used to restore the assembler's default behaviour of
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assembling for the M32R microprocessor. This can be useful if the
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default has been changed by a previous command line option.
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@item -little
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@cindex @code{-little} option, M32R
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This option tells the assembler to produce little-endian code and
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data. The default is dependent upon how the toolchain was
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configured.
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@item -EL
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@cindex @code{-EL} option, M32R
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This is a synonym for @emph{-little}.
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@item -big
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@cindex @code{-big} option, M32R
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This option tells the assembler to produce big-endian code and
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data.
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@item -EB
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@cindex @code{-EB} option, M32R
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This is a synonum for @emph{-big}.
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@item -KPIC
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@cindex @code{-KPIC} option, M32R
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@cindex PIC code generation for M32R
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This option specifies that the output of the assembler should be
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marked as position-independent code (PIC).
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@item -parallel
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@cindex @code{-parallel} option, M32RX
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This option tells the assembler to attempts to combine two sequential
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instructions into a single, parallel instruction, where it is legal to
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do so.
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@item -no-parallel
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@cindex @code{-no-parallel} option, M32RX
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This option disables a previously enabled @emph{-parallel} option.
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@item -no-bitinst
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@cindex @samp{-no-bitinst}, M32R2
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This option disables the support for the extended bit-field
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instructions provided by the M32R2. If this support needs to be
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re-enabled the @emph{-bitinst} switch can be used to restore it.
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@item -O
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@cindex @code{-O} option, M32RX
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This option tells the assembler to attempt to optimize the
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instructions that it produces. This includes filling delay slots and
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converting sequential instructions into parallel ones. This option
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implies @emph{-parallel}.
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@item -warn-explicit-parallel-conflicts
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@cindex @samp{-warn-explicit-parallel-conflicts} option, M32RX
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Instructs @code{@value{AS}} to produce warning messages when
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questionable parallel instructions are encountered. This option is
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enabled by default, but @code{@value{GCC}} disables it when it invokes
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@code{@value{AS}} directly. Questionable instructions are those whose
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behaviour would be different if they were executed sequentially. For
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example the code fragment @samp{mv r1, r2 || mv r3, r1} produces a
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different result from @samp{mv r1, r2 \n mv r3, r1} since the former
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moves r1 into r3 and then r2 into r1, whereas the later moves r2 into r1
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and r3.
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@item -Wp
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@cindex @samp{-Wp} option, M32RX
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This is a shorter synonym for the @emph{-warn-explicit-parallel-conflicts}
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option.
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@item -no-warn-explicit-parallel-conflicts
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@cindex @samp{-no-warn-explicit-parallel-conflicts} option, M32RX
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Instructs @code{@value{AS}} not to produce warning messages when
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questionable parallel instructions are encountered.
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@item -Wnp
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@cindex @samp{-Wnp} option, M32RX
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This is a shorter synonym for the @emph{-no-warn-explicit-parallel-conflicts}
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option.
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@item -ignore-parallel-conflicts
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@cindex @samp{-ignore-parallel-conflicts} option, M32RX
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This option tells the assembler's to stop checking parallel
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instructions for constraint violations. This ability is provided for
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hardware vendors testing chip designs and should not be used under
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normal circumstances.
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@item -no-ignore-parallel-conflicts
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@cindex @samp{-no-ignore-parallel-conflicts} option, M32RX
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This option restores the assembler's default behaviour of checking
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parallel instructions to detect constraint violations.
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@item -Ip
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@cindex @samp{-Ip} option, M32RX
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This is a shorter synonym for the @emph{-ignore-parallel-conflicts}
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option.
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@item -nIp
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@cindex @samp{-nIp} option, M32RX
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This is a shorter synonym for the @emph{-no-ignore-parallel-conflicts}
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option.
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@item -warn-unmatched-high
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@cindex @samp{-warn-unmatched-high} option, M32R
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This option tells the assembler to produce a warning message if a
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@code{.high} pseudo op is encountered without a matching @code{.low}
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pseudo op. The presence of such an unmatched pseudo op usually
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indicates a programming error.
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@item -no-warn-unmatched-high
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@cindex @samp{-no-warn-unmatched-high} option, M32R
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Disables a previously enabled @emph{-warn-unmatched-high} option.
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@item -Wuh
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@cindex @samp{-Wuh} option, M32RX
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This is a shorter synonym for the @emph{-warn-unmatched-high} option.
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@item -Wnuh
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@cindex @samp{-Wnuh} option, M32RX
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This is a shorter synonym for the @emph{-no-warn-unmatched-high} option.
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@end table
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@node M32R-Directives
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@section M32R Directives
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@cindex directives, M32R
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@cindex M32R directives
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The Renease M32R version of @code{@value{AS}} has a few architecture
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specific directives:
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@table @code
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@cindex @code{low} directive, M32R
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@item low @var{expression}
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The @code{low} directive computes the value of its expression and
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places the lower 16-bits of the result into the immediate-field of the
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instruction. For example:
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@smallexample
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or3 r0, r0, #low(0x12345678) ; compute r0 = r0 | 0x5678
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add3, r0, r0, #low(fred) ; compute r0 = r0 + low 16-bits of address of fred
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@end smallexample
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@item high @var{expression}
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@cindex @code{high} directive, M32R
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The @code{high} directive computes the value of its expression and
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places the upper 16-bits of the result into the immediate-field of the
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instruction. For example:
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@smallexample
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seth r0, #high(0x12345678) ; compute r0 = 0x12340000
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seth, r0, #high(fred) ; compute r0 = upper 16-bits of address of fred
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@end smallexample
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@item shigh @var{expression}
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@cindex @code{shigh} directive, M32R
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The @code{shigh} directive is very similar to the @code{high}
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directive. It also computes the value of its expression and places
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the upper 16-bits of the result into the immediate-field of the
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instruction. The difference is that @code{shigh} also checks to see
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if the lower 16-bits could be interpreted as a signed number, and if
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so it assumes that a borrow will occur from the upper-16 bits. To
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compensate for this the @code{shigh} directive pre-biases the upper
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16 bit value by adding one to it. For example:
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For example:
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@smallexample
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seth r0, #shigh(0x12345678) ; compute r0 = 0x12340000
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seth r0, #shigh(0x00008000) ; compute r0 = 0x00010000
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@end smallexample
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In the second example the lower 16-bits are 0x8000. If these are
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treated as a signed value and sign extended to 32-bits then the value
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becomes 0xffff8000. If this value is then added to 0x00010000 then
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the result is 0x00008000.
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This behaviour is to allow for the different semantics of the
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@code{or3} and @code{add3} instructions. The @code{or3} instruction
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treats its 16-bit immediate argument as unsigned whereas the
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@code{add3} treats its 16-bit immediate as a signed value. So for
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example:
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@smallexample
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seth r0, #shigh(0x00008000)
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add3 r0, r0, #low(0x00008000)
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@end smallexample
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Produces the correct result in r0, whereas:
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@smallexample
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seth r0, #shigh(0x00008000)
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or3 r0, r0, #low(0x00008000)
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@end smallexample
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Stores 0xffff8000 into r0.
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Note - the @code{shigh} directive does not know where in the assembly
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source code the lower 16-bits of the value are going set, so it cannot
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check to make sure that an @code{or3} instruction is being used rather
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than an @code{add3} instruction. It is up to the programmer to make
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sure that correct directives are used.
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@cindex @code{.m32r} directive, M32R
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@item .m32r
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The directive performs a similar thing as the @emph{-m32r} command
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line option. It tells the assembler to only accept M32R instructions
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from now on. An instructions from later M32R architectures are
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refused.
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@cindex @code{.m32rx} directive, M32RX
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@item .m32rx
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The directive performs a similar thing as the @emph{-m32rx} command
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line option. It tells the assembler to start accepting the extra
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instructions in the M32RX ISA as well as the ordinary M32R ISA.
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@cindex @code{.m32r2} directive, M32R2
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@item .m32r2
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The directive performs a similar thing as the @emph{-m32r2} command
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line option. It tells the assembler to start accepting the extra
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instructions in the M32R2 ISA as well as the ordinary M32R ISA.
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@cindex @code{.little} directive, M32RX
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@item .little
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The directive performs a similar thing as the @emph{-little} command
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line option. It tells the assembler to start producing little-endian
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code and data. This option should be used with care as producing
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mixed-endian binary files is fraught with danger.
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@cindex @code{.big} directive, M32RX
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@item .big
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The directive performs a similar thing as the @emph{-big} command
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line option. It tells the assembler to start producing big-endian
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code and data. This option should be used with care as producing
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mixed-endian binary files is fraught with danger.
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@end table
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@node M32R-Warnings
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@section M32R Warnings
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@cindex warnings, M32R
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@cindex M32R warnings
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There are several warning and error messages that can be produced by
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@code{@value{AS}} which are specific to the M32R:
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@table @code
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@item output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?
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This message is only produced if warnings for explicit parallel
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conflicts have been enabled. It indicates that the assembler has
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encountered a parallel instruction in which the destination register of
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the left hand instruction is used as an input register in the right hand
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instruction. For example in this code fragment
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@samp{mv r1, r2 || neg r3, r1} register r1 is the destination of the
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move instruction and the input to the neg instruction.
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@item output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?
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This message is only produced if warnings for explicit parallel
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conflicts have been enabled. It indicates that the assembler has
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encountered a parallel instruction in which the destination register of
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the right hand instruction is used as an input register in the left hand
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instruction. For example in this code fragment
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@samp{mv r1, r2 || neg r2, r3} register r2 is the destination of the
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neg instruction and the input to the move instruction.
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@item instruction @samp{...} is for the M32RX only
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This message is produced when the assembler encounters an instruction
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which is only supported by the M32Rx processor, and the @samp{-m32rx}
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command line flag has not been specified to allow assembly of such
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instructions.
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@item unknown instruction @samp{...}
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This message is produced when the assembler encounters an instruction
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which it does not recognize.
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@item only the NOP instruction can be issued in parallel on the m32r
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This message is produced when the assembler encounters a parallel
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instruction which does not involve a NOP instruction and the
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@samp{-m32rx} command line flag has not been specified. Only the M32Rx
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processor is able to execute two instructions in parallel.
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@item instruction @samp{...} cannot be executed in parallel.
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This message is produced when the assembler encounters a parallel
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instruction which is made up of one or two instructions which cannot be
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executed in parallel.
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@item Instructions share the same execution pipeline
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This message is produced when the assembler encounters a parallel
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instruction whoes components both use the same execution pipeline.
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@item Instructions write to the same destination register.
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This message is produced when the assembler encounters a parallel
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instruction where both components attempt to modify the same register.
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For example these code fragments will produce this message:
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@samp{mv r1, r2 || neg r1, r3}
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@samp{jl r0 || mv r14, r1}
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@samp{st r2, @@-r1 || mv r1, r3}
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@samp{mv r1, r2 || ld r0, @@r1+}
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@samp{cmp r1, r2 || addx r3, r4} (Both write to the condition bit)
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@end table
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