darling-gdb/sim/mips/vr.igen

// -*- C -*-
//
// NEC specific instructions
//

// Integer Instructions
// --------------------
//
// MulAcc is the Multiply Accumulator.
//     This register is mapped on the the HI and LO registers.
//     Upper 32 bits of MulAcc is mapped on to lower 32 bits of HI register.
//     Lower 32 bits of MulAcc is mapped on to lower 32 bits of LO register.


:function:::unsigned64:MulAcc:
*vr4100:
{
  unsigned64 result = U8_4 (HI, LO);
  return result;
}

:function:::void:SET_MulAcc:unsigned64 value
*vr4100:
{
  /* 64 bit specific */
  *AL4_8 (&HI) = VH4_8 (value);
  *AL4_8 (&LO) = VL4_8 (value);
}

:function:::signed64:SignedMultiply:signed32 l, signed32 r
*vr4100:
{
  signed64 result = (signed64) l * (signed64) r;
  return result;
}

:function:::unsigned64:UnsignedMultiply:unsigned32 l, unsigned32 r
*vr4100:
{
  unsigned64 result = (unsigned64) l * (unsigned64) r;
  return result;
}

:function:::unsigned64:Low32Bits:unsigned64 value
*vr4100:
{
  unsigned64 result = (signed64) (signed32) VL4_8 (value);
  return result;
}

:function:::unsigned64:High32Bits:unsigned64 value
*vr4100:
{
  unsigned64 result = (signed64) (signed32) VH4_8 (value);
  return result;
}



// Multiply, Accumulate
000000,5.RS,5.RT,00000,00000,101000::64::MAC
"mac r<RS>, r<RT>"
*vr4100:
{
  SET_MulAcc (SD_, MulAcc (SD_) + SignedMultiply (SD_, GPR[RS], GPR[RT]));
}


// D-Multiply, Accumulate
000000,5.RS,5.RT,00000,00000,101001::64::DMAC
"dmac r<RS>, r<RT>"
*vr4100:
{
  LO = LO + SignedMultiply (SD_, GPR[RS], GPR[RT]);
}