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268 lines
6.7 KiB
C
268 lines
6.7 KiB
C
/* Print Acorn Risc Machine instructions for GDB, the GNU debugger.
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Copyright 1986, 1989, 1991, 1992 Free Software Foundation, Inc.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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#include "defs.h"
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#include <ctype.h>
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#include <assert.h>
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#include "symtab.h"
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#include "opcode/arm.h"
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static char *shift_names[] = {
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"lsl", "lsr", "asr", "ror",
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};
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static char *cond_names[] = {
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"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
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"hi", "ls", "ge", "lt", "gt", "le", "", "nv"
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};
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static char float_precision[] = "sdep";
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static char float_rounding[] = " pmz";
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static float float_immed[] = { 0.0, 1.0, 2.0, 3.0, 4.0, 5.0, 0.5, 10.0 };
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static void print_ldr_str_offset();
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static void print_ldc_stc_offset();
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static long immediate_value();
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/* Print the ARM instruction at address MEMADDR in debugged memory,
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on STREAM. Returns length of the instruction, in bytes. */
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int
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print_insn (memaddr, stream)
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CORE_ADDR memaddr;
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FILE *stream;
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{
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unsigned long ins;
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register struct opcode *op;
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register char *p;
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register int i, c;
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int s, e, val;
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ins = read_memory_integer(memaddr, 4);
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for (i = 0, op = opcodes; i < N_OPCODES; i++, op++)
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if ((ins & op->mask) == op->value) break;
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assert(i != N_OPCODES);
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for (p = op->assembler; *p;) {
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c = *p++;
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if (c == '%') {
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s = e = 0;
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while (isdigit(*p))
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s = s*10 + (*p++ - '0');
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if (*p == '-') {
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p++;
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while (isdigit(*p))
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e = e*10 + (*p++ - '0');
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} else
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e = s;
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assert(s >= 0 && s <= 31 && e >= 0 && e <= 31);
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val = (ins >> s) & ((1 << (e + 1 - s)) - 1);
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switch (*p++) {
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case '%' :
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putc('%', stream);
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break;
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case 'd' :
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fprintf(stream, "%d", val);
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break;
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case 'x' :
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fprintf(stream, "%x", val);
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break;
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case 'r' :
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assert(val >= 0 && val <= 15);
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fprintf(stream, "%s", reg_names[val]);
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break;
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case 'c' :
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fprintf(stream, "%s", cond_names[ins >> 28]);
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break;
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case '\'' :
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assert(*p);
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c = *p++;
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if (val)
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putc(c, stream);
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break;
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case '`' :
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assert(*p);
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c = *p++;
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if (!val)
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putc(c, stream);
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break;
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case '?' :
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assert(*p);
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c = *p++;
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assert(*p);
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if (val)
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p++;
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else
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c = *p++;
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putc(c, stream);
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break;
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case 'p' :
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if (((ins >> 12) & 0xf) == 0xf)
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putc('p', stream);
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break;
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case 'o' :
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if (ins & (1<<25)) {
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int immed = immediate_value(ins & 0xfff);
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fprintf (stream, "#%d (0x%x)", immed, immed);
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} else {
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int operand2 = ins & 0xfff;
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/* in operand2 :
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bits 0-3 are the base register
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bits 5-6 are the shift (0=lsl, 1=lsr, 2=asr, 3=ror)
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if bit 4 is zero then bits 7-11 are an immediate shift count
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else bit 7 must be zero and bits 8-11 are the register
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to be used as a shift count.
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Note: no shift at all is encoded as "reg lsl #0" */
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fprintf (stream, "%s", reg_names[operand2 & 0xf]);
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if (operand2 & 0xff0) {
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/* ror #0 is really rrx (rotate right extend) */
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if ((operand2 & 0xff0) == 0x060)
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fprintf (stream, ", rrx");
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else {
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fprintf (stream, ", %s ",
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shift_names[(operand2 >> 5) & 3]);
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if (operand2 & (1<<4)) /* register shift */
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fprintf (stream, "%s",
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reg_names[operand2 >> 8]);
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else /* immediate shift */
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fprintf (stream, "#%d",
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operand2 >> 7);
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}
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}
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}
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break;
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case 'a' :
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fprintf (stream, "[%s", reg_names[(ins >> 16) & 0xf]);
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if (ins & (1<<24)) {
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fprintf (stream, ", ");
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print_ldr_str_offset (ins, stream);
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putc (']', stream);
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if (ins & (1<<21)) putc('!', stream);
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/* If it is a pc relative load, then it is probably
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a constant so print it */
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if (((ins >> 16) & 0xf) == 15 &&
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(ins & (1<<25)) == 0 &&
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(ins & (1<<20))) {
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int addr = memaddr + 8 +
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(ins & 0xfff) * ((ins & (1<<23)) ? 1 : -1);
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fprintf (stream, " (contents=");
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print_address (read_memory_integer(addr, 4), stream);
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fprintf (stream, ")");
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}
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} else {
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fprintf (stream, "]," );
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print_ldr_str_offset (ins, stream);
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}
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break;
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case 'b' :
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print_address (memaddr + 8 + (((int)ins << 8) >> 6), stream);
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break;
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case 'A' :
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fprintf (stream, "[%s", reg_names[(ins >> 16) & 0xf]);
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if (ins & (1<<24)) {
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fprintf (stream, ", ");
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print_ldc_stc_offset (ins, stream);
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putc(']', stream);
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if (ins & (1<<21))
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putc('!', stream);
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} else {
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fprintf (stream, "], ");
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print_ldc_stc_offset (ins, stream);
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}
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break;
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case 'm' :
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{
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int regnum, first = 1;
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putc('{', stream);
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for (regnum = 0; regnum < 16; regnum++)
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if (ins & (1<<regnum)) {
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if (!first)
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putc (',', stream);
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first = 0;
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fprintf (stream, "%s", reg_names[regnum]);
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}
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putc('}', stream);
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}
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break;
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case 'P' :
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val = ((ins >> 18) & 2) | ((ins >> 7) & 1);
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putc(float_precision[val], stream);
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break;
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case 'Q' :
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val = ((ins >> 21) & 2) | ((ins >> 15) & 1);
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putc(float_precision[val], stream);
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break;
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case 'R' :
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val = ((ins >> 5) & 3);
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if (val) putc(float_rounding[val], stream);
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break;
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case 'f' :
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assert(val >= 0 && val <= 15);
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if (val > 7)
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fprintf (stream, "#%3.1f", float_immed[val - 8]);
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else
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fprintf (stream, "f%d", val);
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break;
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default:
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abort();
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}
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} else
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putc(c, stream);
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}
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return 4;
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}
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static long
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immediate_value(operand)
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int operand;
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{
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int val = operand & 0xff;
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int shift = 2*(operand >> 8);
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/* immediate value is (val ror shift) */
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return (val >> shift) | (val << (32 - shift));
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}
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static void
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print_ldr_str_offset(ins, stream)
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unsigned long ins;
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FILE *stream;
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{
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if ((ins & (1<<25)) == 0)
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fprintf (stream, "#%d",
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(ins & 0xfff) * ((ins & (1<<23)) ? 1 : -1));
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else {
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fprintf (stream, "%s%s", reg_names[ins & 0xf],
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(ins & (1<<23)) ? "" : "-");
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if (ins & 0xff0)
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fprintf (stream, ", %s #%d",
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shift_names[(ins >> 5) & 3],
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(ins >> 7) & 0x1f);
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}
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}
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static void
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print_ldc_stc_offset(ins, stream)
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unsigned long ins;
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FILE *stream;
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{
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fprintf (stream, "#%d",
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4 * (ins & 0xff) * ((ins & (1<<23)) ? 1 : -1));
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}
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