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c10d9d8fc3
bfd/ChangeLog * cpu-ia64-opc.c: Add operand constant "ar.csd". gas/ChangeLog * config/tc-ia64.c (pseudo_func): Add "@pause" constant for "hint" instruction. (emit_one_bundle): Handle "hint" instruction. (operand_match): Match IA64_OPND_AR_CSD. gas/testsuite/ChangeLog * gas/ia64/opc-b.d: Update for instructions added by SDM2.1. * gas/ia64/opc-b.s: Ditto. * gas/ia64/opc-f.d: Ditto. * gas/ia64/opc-f.s: Ditto. * gas/ia64/opc-i.d: Ditto. * gas/ia64/opc-i.s: Ditto. * gas/ia64/opc-m.d: Ditto. * gas/ia64/opc-m.s: Ditto. * gas/ia64/opc-x.d: Ditto. * gas/ia64/opc-x.s: Ditto. include/opcode/ChangeLog * ia64.h: Fix copyright message. (IA64_OPND_AR_CSD): New operand kind. opcodes/ChangeLog * ia64-opc-d.c (ia64_opcodes_d): Add "hint" instruction. * ia64-opc-b.c: Add "hint.b" instruction. * ia64-opc-f.c: Add "hint.f" instruction. * ia64-opc-i.c: Add "hint.i" instruction. * ia64-opc-m.c: Add "hint.m", "fc.i", "ld16", "st16", and "cmp8xchg16" instructions. * ia64-opc-x.c: Add "hint.x" instruction. * ia64-opc.h (AR_CSD): New macro. * ia64-ic.tbl: Update according to SDM2.1. * ia64-raw.tbl: Ditto. * ia64-waw.tbl: Ditto. * ia64-gen.c (in_iclass): Handle "hint" like "nop". (lookup_regindex): Recognize AR[FCR], AR[EFLAG], AR[CSD], AR[SSD], AR[CFLG], AR[FSR], AR[FIR], and AR[FDR]. * ia64-asmtab.c: Regenerate.
305 lines
12 KiB
C
305 lines
12 KiB
C
/* ia64-opc-i.c -- IA-64 `I' opcode table.
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Copyright 1998, 1999, 2000, 2002 Free Software Foundation, Inc.
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Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
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This file is part of GDB, GAS, and the GNU binutils.
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GDB, GAS, and the GNU binutils are free software; you can redistribute
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them and/or modify them under the terms of the GNU General Public
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License as published by the Free Software Foundation; either version
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2, or (at your option) any later version.
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GDB, GAS, and the GNU binutils are distributed in the hope that they
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will be useful, but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
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the GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this file; see the file COPYING. If not, write to the
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Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA
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02111-1307, USA. */
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#include "ia64-opc.h"
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#define I0 IA64_TYPE_I, 0
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#define I IA64_TYPE_I, 1
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#define I2 IA64_TYPE_I, 2
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/* instruction bit fields: */
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#define bC(x) (((ia64_insn) ((x) & 0x1)) << 12)
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#define bIh(x) (((ia64_insn) ((x) & 0x1)) << 23)
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#define bTa(x) (((ia64_insn) ((x) & 0x1)) << 33)
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#define bTag13(x) (((ia64_insn) ((x) & 0x1)) << 33)
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#define bTb(x) (((ia64_insn) ((x) & 0x1)) << 36)
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#define bVc(x) (((ia64_insn) ((x) & 0x1)) << 20)
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#define bVe(x) (((ia64_insn) ((x) & 0x1)) << 32)
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#define bWh(x) (((ia64_insn) ((x) & 0x3)) << 20)
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#define bX(x) (((ia64_insn) ((x) & 0x1)) << 33)
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#define bXb(x) (((ia64_insn) ((x) & 0x1)) << 22)
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#define bX2(x) (((ia64_insn) ((x) & 0x3)) << 34)
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#define bX2a(x) (((ia64_insn) ((x) & 0x3)) << 34)
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#define bX2b(x) (((ia64_insn) ((x) & 0x3)) << 28)
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#define bX2c(x) (((ia64_insn) ((x) & 0x3)) << 30)
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#define bX3(x) (((ia64_insn) ((x) & 0x7)) << 33)
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#define bX6(x) (((ia64_insn) ((x) & 0x3f)) << 27)
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#define bYa(x) (((ia64_insn) ((x) & 0x1)) << 13)
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#define bYb(x) (((ia64_insn) ((x) & 0x1)) << 26)
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#define bZa(x) (((ia64_insn) ((x) & 0x1)) << 36)
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#define bZb(x) (((ia64_insn) ((x) & 0x1)) << 33)
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/* instruction bit masks: */
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#define mC bC (-1)
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#define mIh bIh (-1)
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#define mTa bTa (-1)
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#define mTag13 bTag13 (-1)
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#define mTb bTb (-1)
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#define mVc bVc (-1)
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#define mVe bVe (-1)
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#define mWh bWh (-1)
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#define mX bX (-1)
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#define mXb bXb (-1)
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#define mX2 bX2 (-1)
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#define mX2a bX2a (-1)
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#define mX2b bX2b (-1)
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#define mX2c bX2c (-1)
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#define mX3 bX3 (-1)
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#define mX6 bX6 (-1)
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#define mYa bYa (-1)
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#define mYb bYb (-1)
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#define mZa bZa (-1)
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#define mZb bZb (-1)
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#define OpZaZbVeX2aX2b(a,b,c,d,e,f) \
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(bOp (a) | bZa (b) | bZb (c) | bVe (d) | bX2a (e) | bX2b (f)), \
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(mOp | mZa | mZb | mVe | mX2a | mX2b)
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#define OpZaZbVeX2aX2bX2c(a,b,c,d,e,f,g) \
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(bOp (a) | bZa (b) | bZb (c) | bVe (d) | bX2a (e) | bX2b (f) | bX2c (g)), \
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(mOp | mZa | mZb | mVe | mX2a | mX2b | mX2c)
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#define OpX2X(a,b,c) (bOp (a) | bX2 (b) | bX (c)), (mOp | mX2 | mX)
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#define OpX2XYa(a,b,c,d) (bOp (a) | bX2 (b) | bX (c) | bYa (d)), \
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(mOp | mX2 | mX | mYa)
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#define OpX2XYb(a,b,c,d) (bOp (a) | bX2 (b) | bX (c) | bYb (d)), \
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(mOp | mX2 | mX | mYb)
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#define OpX2TaTbYaC(a,b,c,d,e,f) \
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(bOp (a) | bX2 (b) | bTa (c) | bTb (d) | bYa (e) | bC (f)), \
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(mOp | mX2 | mTa | mTb | mYa | mC)
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#define OpX3(a,b) (bOp (a) | bX3 (b)), (mOp | mX3)
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#define OpX3X6(a,b,c) (bOp (a) | bX3 (b) | bX6(c)), \
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(mOp | mX3 | mX6)
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#define OpX3X6Yb(a,b,c,d) (bOp (a) | bX3 (b) | bX6(c) | bYb(d)), \
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(mOp | mX3 | mX6 | mYb)
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#define OpX3XbIhWh(a,b,c,d,e) \
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(bOp (a) | bX3 (b) | bXb (c) | bIh (d) | bWh (e)), \
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(mOp | mX3 | mXb | mIh | mWh)
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#define OpX3XbIhWhTag13(a,b,c,d,e,f) \
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(bOp (a) | bX3 (b) | bXb (c) | bIh (d) | bWh (e) | bTag13 (f)), \
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(mOp | mX3 | mXb | mIh | mWh | mTag13)
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/* Used to initialise unused fields in ia64_opcode struct,
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in order to stop gcc from complaining. */
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#define EMPTY 0,0,NULL
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struct ia64_opcode ia64_opcodes_i[] =
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{
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/* I-type instruction encodings (sorted according to major opcode). */
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{"break.i", I0, OpX3X6 (0, 0, 0x00), {IMMU21}, X_IN_MLX, 0, NULL},
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{"nop.i", I0, OpX3X6Yb (0, 0, 0x01, 0), {IMMU21}, X_IN_MLX, 0, NULL},
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{"hint.i", I0, OpX3X6Yb (0, 0, 0x01, 1), {IMMU21}, X_IN_MLX, 0, NULL},
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{"chk.s.i", I0, OpX3 (0, 1), {R2, TGT25b}, EMPTY},
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{"mov", I, OpX3XbIhWhTag13 (0, 7, 0, 0, 1, 0), {B1, R2}, PSEUDO, 0, NULL},
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#define MOV(a,b,c,d) \
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I, OpX3XbIhWh (0, a, b, c, d), {B1, R2, TAG13b}, EMPTY
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{"mov.sptk", MOV (7, 0, 0, 0)},
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{"mov.sptk.imp", MOV (7, 0, 1, 0)},
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{"mov", MOV (7, 0, 0, 1)},
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{"mov.imp", MOV (7, 0, 1, 1)},
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{"mov.dptk", MOV (7, 0, 0, 2)},
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{"mov.dptk.imp", MOV (7, 0, 1, 2)},
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{"mov.ret.sptk", MOV (7, 1, 0, 0)},
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{"mov.ret.sptk.imp", MOV (7, 1, 1, 0)},
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{"mov.ret", MOV (7, 1, 0, 1)},
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{"mov.ret.imp", MOV (7, 1, 1, 1)},
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{"mov.ret.dptk", MOV (7, 1, 0, 2)},
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{"mov.ret.dptk.imp", MOV (7, 1, 1, 2)},
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#undef MOV
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{"mov", I, OpX3X6 (0, 0, 0x31), {R1, B2}, EMPTY},
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{"mov", I, OpX3 (0, 3), {PR, R2, IMM17}, EMPTY},
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{"mov", I, OpX3 (0, 2), {PR_ROT, IMM44}, EMPTY},
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{"mov", I, OpX3X6 (0, 0, 0x30), {R1, IP}, EMPTY},
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{"mov", I, OpX3X6 (0, 0, 0x33), {R1, PR}, EMPTY},
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{"mov.i", I, OpX3X6 (0, 0, 0x2a), {AR3, R2}, EMPTY},
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{"mov.i", I, OpX3X6 (0, 0, 0x0a), {AR3, IMM8}, EMPTY},
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{"mov.i", I, OpX3X6 (0, 0, 0x32), {R1, AR3}, EMPTY},
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{"zxt1", I, OpX3X6 (0, 0, 0x10), {R1, R3}, EMPTY},
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{"zxt2", I, OpX3X6 (0, 0, 0x11), {R1, R3}, EMPTY},
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{"zxt4", I, OpX3X6 (0, 0, 0x12), {R1, R3}, EMPTY},
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{"sxt1", I, OpX3X6 (0, 0, 0x14), {R1, R3}, EMPTY},
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{"sxt2", I, OpX3X6 (0, 0, 0x15), {R1, R3}, EMPTY},
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{"sxt4", I, OpX3X6 (0, 0, 0x16), {R1, R3}, EMPTY},
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{"czx1.l", I, OpX3X6 (0, 0, 0x18), {R1, R3}, EMPTY},
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{"czx2.l", I, OpX3X6 (0, 0, 0x19), {R1, R3}, EMPTY},
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{"czx1.r", I, OpX3X6 (0, 0, 0x1c), {R1, R3}, EMPTY},
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{"czx2.r", I, OpX3X6 (0, 0, 0x1d), {R1, R3}, EMPTY},
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{"dep", I, Op (4), {R1, R2, R3, CPOS6c, LEN4}, EMPTY},
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{"shrp", I, OpX2X (5, 3, 0), {R1, R2, R3, CNT6}, EMPTY},
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{"shr.u", I, OpX2XYa (5, 1, 0, 0), {R1, R3, POS6},
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PSEUDO | LEN_EQ_64MCNT, 0, NULL},
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{"extr.u", I, OpX2XYa (5, 1, 0, 0), {R1, R3, POS6, LEN6}, EMPTY},
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{"shr", I, OpX2XYa (5, 1, 0, 1), {R1, R3, POS6},
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PSEUDO | LEN_EQ_64MCNT, 0, NULL},
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{"extr", I, OpX2XYa (5, 1, 0, 1), {R1, R3, POS6, LEN6}, EMPTY},
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{"shl", I, OpX2XYb (5, 1, 1, 0), {R1, R2, CPOS6a},
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PSEUDO | LEN_EQ_64MCNT, 0, NULL},
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{"dep.z", I, OpX2XYb (5, 1, 1, 0), {R1, R2, CPOS6a, LEN6}, EMPTY},
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{"dep.z", I, OpX2XYb (5, 1, 1, 1), {R1, IMM8, CPOS6a, LEN6}, EMPTY},
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{"dep", I, OpX2X (5, 3, 1), {R1, IMM1, R3, CPOS6b, LEN6}, EMPTY},
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#define TBIT(a,b,c,d) \
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I2, OpX2TaTbYaC (5, 0, a, b, c, d), {P1, P2, R3, POS6}, EMPTY
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#define TBITCM(a,b,c,d) \
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I2, OpX2TaTbYaC (5, 0, a, b, c, d), {P2, P1, R3, POS6}, PSEUDO, 0, NULL
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{"tbit.z", TBIT (0, 0, 0, 0)},
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{"tbit.nz", TBITCM (0, 0, 0, 0)},
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{"tbit.z.unc", TBIT (0, 0, 0, 1)},
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{"tbit.nz.unc", TBITCM (0, 0, 0, 1)},
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{"tbit.z.and", TBIT (0, 1, 0, 0)},
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{"tbit.nz.andcm", TBITCM (0, 1, 0, 0)},
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{"tbit.nz.and", TBIT (0, 1, 0, 1)},
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{"tbit.z.andcm", TBITCM (0, 1, 0, 1)},
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{"tbit.z.or", TBIT (1, 0, 0, 0)},
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{"tbit.nz.orcm", TBITCM (1, 0, 0, 0)},
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{"tbit.nz.or", TBIT (1, 0, 0, 1)},
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{"tbit.z.orcm", TBITCM (1, 0, 0, 1)},
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{"tbit.z.or.andcm", TBIT (1, 1, 0, 0)},
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{"tbit.nz.and.orcm", TBITCM (1, 1, 0, 0)},
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{"tbit.nz.or.andcm", TBIT (1, 1, 0, 1)},
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{"tbit.z.and.orcm", TBITCM (1, 1, 0, 1)},
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#undef TBIT
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#define TNAT(a,b,c,d) \
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I2, OpX2TaTbYaC (5, 0, a, b, c, d), {P1, P2, R3}, EMPTY
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#define TNATCM(a,b,c,d) \
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I2, OpX2TaTbYaC (5, 0, a, b, c, d), {P2, P1, R3}, PSEUDO, 0, NULL
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{"tnat.z", TNAT (0, 0, 1, 0)},
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{"tnat.nz", TNATCM (0, 0, 1, 0)},
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{"tnat.z.unc", TNAT (0, 0, 1, 1)},
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{"tnat.nz.unc", TNATCM (0, 0, 1, 1)},
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{"tnat.z.and", TNAT (0, 1, 1, 0)},
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{"tnat.nz.andcm", TNATCM (0, 1, 1, 0)},
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{"tnat.nz.and", TNAT (0, 1, 1, 1)},
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{"tnat.z.andcm", TNATCM (0, 1, 1, 1)},
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{"tnat.z.or", TNAT (1, 0, 1, 0)},
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{"tnat.nz.orcm", TNATCM (1, 0, 1, 0)},
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{"tnat.nz.or", TNAT (1, 0, 1, 1)},
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{"tnat.z.orcm", TNATCM (1, 0, 1, 1)},
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{"tnat.z.or.andcm", TNAT (1, 1, 1, 0)},
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{"tnat.nz.and.orcm", TNATCM (1, 1, 1, 0)},
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{"tnat.nz.or.andcm", TNAT (1, 1, 1, 1)},
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{"tnat.z.and.orcm", TNATCM (1, 1, 1, 1)},
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#undef TNAT
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{"pmpyshr2", I, OpZaZbVeX2aX2b (7, 0, 1, 0, 0, 3), {R1, R2, R3, CNT2c}, EMPTY},
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{"pmpyshr2.u", I, OpZaZbVeX2aX2b (7, 0, 1, 0, 0, 1), {R1, R2, R3, CNT2c}, EMPTY},
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{"pmpy2.r", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 1, 3), {R1, R2, R3}, EMPTY},
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{"pmpy2.l", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 3, 3), {R1, R2, R3}, EMPTY},
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{"mix1.r", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 0, 2), {R1, R2, R3}, EMPTY},
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{"mix2.r", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 0, 2), {R1, R2, R3}, EMPTY},
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{"mix4.r", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 0, 2), {R1, R2, R3}, EMPTY},
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{"mix1.l", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 2, 2), {R1, R2, R3}, EMPTY},
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{"mix2.l", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 2, 2), {R1, R2, R3}, EMPTY},
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{"mix4.l", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 2, 2), {R1, R2, R3}, EMPTY},
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{"pack2.uss", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 0, 0), {R1, R2, R3}, EMPTY},
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{"pack2.sss", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 2, 0), {R1, R2, R3}, EMPTY},
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{"pack4.sss", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 2, 0), {R1, R2, R3}, EMPTY},
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{"unpack1.h", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 0, 1), {R1, R2, R3}, EMPTY},
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{"unpack2.h", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 0, 1), {R1, R2, R3}, EMPTY},
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{"unpack4.h", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 0, 1), {R1, R2, R3}, EMPTY},
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{"unpack1.l", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 2, 1), {R1, R2, R3}, EMPTY},
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{"unpack2.l", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 2, 1), {R1, R2, R3}, EMPTY},
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{"unpack4.l", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 2, 1), {R1, R2, R3}, EMPTY},
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{"pmin1.u", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 1, 0), {R1, R2, R3}, EMPTY},
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{"pmax1.u", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 1, 1), {R1, R2, R3}, EMPTY},
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{"pmin2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 3, 0), {R1, R2, R3}, EMPTY},
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{"pmax2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 3, 1), {R1, R2, R3}, EMPTY},
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{"psad1", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 3, 2), {R1, R2, R3}, EMPTY},
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{"mux1", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 3, 2, 2), {R1, R2, MBTYPE4}, EMPTY},
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{"mux2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 3, 2, 2), {R1, R2, MHTYPE8}, EMPTY},
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{"pshr2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 0, 2, 0), {R1, R3, R2}, EMPTY},
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{"pshr4", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 0, 2, 0), {R1, R3, R2}, EMPTY},
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{"shr", I, OpZaZbVeX2aX2bX2c (7, 1, 1, 0, 0, 2, 0), {R1, R3, R2}, EMPTY},
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{"pshr2.u", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 0, 0, 0), {R1, R3, R2}, EMPTY},
|
|
{"pshr4.u", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 0, 0, 0), {R1, R3, R2}, EMPTY},
|
|
{"shr.u", I, OpZaZbVeX2aX2bX2c (7, 1, 1, 0, 0, 0, 0), {R1, R3, R2}, EMPTY},
|
|
{"pshr2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 1, 3, 0), {R1, R3, CNT5}, EMPTY},
|
|
{"pshr4", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 1, 3, 0), {R1, R3, CNT5}, EMPTY},
|
|
{"pshr2.u", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 1, 1, 0), {R1, R3, CNT5}, EMPTY},
|
|
{"pshr4.u", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 1, 1, 0), {R1, R3, CNT5}, EMPTY},
|
|
{"pshl2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 0, 0, 1), {R1, R2, R3}, EMPTY},
|
|
{"pshl4", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 0, 0, 1), {R1, R2, R3}, EMPTY},
|
|
{"shl", I, OpZaZbVeX2aX2bX2c (7, 1, 1, 0, 0, 0, 1), {R1, R2, R3}, EMPTY},
|
|
{"pshl2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 3, 1, 1), {R1, R2, CCNT5}, EMPTY},
|
|
{"pshl4", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 3, 1, 1), {R1, R2, CCNT5}, EMPTY},
|
|
{"popcnt", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 1, 1, 2), {R1, R3}, EMPTY},
|
|
|
|
{NULL, 0, 0, 0, 0, {0}, 0, 0, NULL}
|
|
};
|
|
|
|
#undef I0
|
|
#undef I
|
|
#undef I2
|
|
#undef L
|
|
#undef bC
|
|
#undef bIh
|
|
#undef bTa
|
|
#undef bTag13
|
|
#undef bTb
|
|
#undef bVc
|
|
#undef bVe
|
|
#undef bWh
|
|
#undef bX
|
|
#undef bXb
|
|
#undef bX2
|
|
#undef bX2a
|
|
#undef bX2b
|
|
#undef bX2c
|
|
#undef bX3
|
|
#undef bX6
|
|
#undef bY
|
|
#undef bZa
|
|
#undef bZb
|
|
#undef mC
|
|
#undef mIh
|
|
#undef mTa
|
|
#undef mTag13
|
|
#undef mTb
|
|
#undef mVc
|
|
#undef mVe
|
|
#undef mWh
|
|
#undef mX
|
|
#undef mXb
|
|
#undef mX2
|
|
#undef mX2a
|
|
#undef mX2b
|
|
#undef mX2c
|
|
#undef mX3
|
|
#undef mX6
|
|
#undef mY
|
|
#undef mZa
|
|
#undef mZb
|
|
#undef OpZaZbVeX2aX2b
|
|
#undef OpZaZbVeX2aX2bX2c
|
|
#undef OpX2X
|
|
#undef OpX2XYa
|
|
#undef OpX2XYb
|
|
#undef OpX2TaTbYaC
|
|
#undef OpX3
|
|
#undef OpX3X6
|
|
#undef OpX3XbIhWh
|
|
#undef OpX3XbIhWhTag13
|
|
#undef EMPTY
|