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c10d9d8fc3
bfd/ChangeLog * cpu-ia64-opc.c: Add operand constant "ar.csd". gas/ChangeLog * config/tc-ia64.c (pseudo_func): Add "@pause" constant for "hint" instruction. (emit_one_bundle): Handle "hint" instruction. (operand_match): Match IA64_OPND_AR_CSD. gas/testsuite/ChangeLog * gas/ia64/opc-b.d: Update for instructions added by SDM2.1. * gas/ia64/opc-b.s: Ditto. * gas/ia64/opc-f.d: Ditto. * gas/ia64/opc-f.s: Ditto. * gas/ia64/opc-i.d: Ditto. * gas/ia64/opc-i.s: Ditto. * gas/ia64/opc-m.d: Ditto. * gas/ia64/opc-m.s: Ditto. * gas/ia64/opc-x.d: Ditto. * gas/ia64/opc-x.s: Ditto. include/opcode/ChangeLog * ia64.h: Fix copyright message. (IA64_OPND_AR_CSD): New operand kind. opcodes/ChangeLog * ia64-opc-d.c (ia64_opcodes_d): Add "hint" instruction. * ia64-opc-b.c: Add "hint.b" instruction. * ia64-opc-f.c: Add "hint.f" instruction. * ia64-opc-i.c: Add "hint.i" instruction. * ia64-opc-m.c: Add "hint.m", "fc.i", "ld16", "st16", and "cmp8xchg16" instructions. * ia64-opc-x.c: Add "hint.x" instruction. * ia64-opc.h (AR_CSD): New macro. * ia64-ic.tbl: Update according to SDM2.1. * ia64-raw.tbl: Ditto. * ia64-waw.tbl: Ditto. * ia64-gen.c (in_iclass): Handle "hint" like "nop". (lookup_regindex): Recognize AR[FCR], AR[EFLAG], AR[CSD], AR[SSD], AR[CFLG], AR[FSR], AR[FIR], and AR[FDR]. * ia64-asmtab.c: Regenerate.
594 lines
19 KiB
C
594 lines
19 KiB
C
/* Copyright 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
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Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
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This file is part of BFD, the Binary File Descriptor library.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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/* Logically, this code should be part of libopcode but since some of
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the operand insertion/extraction functions help bfd to implement
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relocations, this code is included as part of cpu-ia64.c. This
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avoids circular dependencies between libopcode and libbfd and also
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obviates the need for applications to link in libopcode when all
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they really want is libbfd.
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--davidm Mon Apr 13 22:14:02 1998 */
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#include "../opcodes/ia64-opc.h"
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#define NELEMS(a) ((int) (sizeof (a) / sizeof ((a)[0])))
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static const char*
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ins_rsvd (const struct ia64_operand *self ATTRIBUTE_UNUSED,
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ia64_insn value ATTRIBUTE_UNUSED, ia64_insn *code ATTRIBUTE_UNUSED)
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{
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return "internal error---this shouldn't happen";
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}
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static const char*
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ext_rsvd (const struct ia64_operand *self ATTRIBUTE_UNUSED,
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ia64_insn code ATTRIBUTE_UNUSED, ia64_insn *valuep ATTRIBUTE_UNUSED)
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{
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return "internal error---this shouldn't happen";
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}
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static const char*
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ins_const (const struct ia64_operand *self ATTRIBUTE_UNUSED,
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ia64_insn value ATTRIBUTE_UNUSED, ia64_insn *code ATTRIBUTE_UNUSED)
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{
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return 0;
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}
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static const char*
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ext_const (const struct ia64_operand *self ATTRIBUTE_UNUSED,
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ia64_insn code ATTRIBUTE_UNUSED, ia64_insn *valuep ATTRIBUTE_UNUSED)
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{
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return 0;
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}
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static const char*
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ins_reg (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
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{
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if (value >= 1u << self->field[0].bits)
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return "register number out of range";
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*code |= value << self->field[0].shift;
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return 0;
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}
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static const char*
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ext_reg (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
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{
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*valuep = ((code >> self->field[0].shift)
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& ((1u << self->field[0].bits) - 1));
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return 0;
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}
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static const char*
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ins_immu (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
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{
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ia64_insn new = 0;
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int i;
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for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i)
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{
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new |= ((value & ((((ia64_insn) 1) << self->field[i].bits) - 1))
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<< self->field[i].shift);
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value >>= self->field[i].bits;
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}
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if (value)
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return "integer operand out of range";
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*code |= new;
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return 0;
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}
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static const char*
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ext_immu (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
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{
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BFD_HOST_U_64_BIT value = 0;
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int i, bits = 0, total = 0;
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for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i)
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{
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bits = self->field[i].bits;
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value |= ((code >> self->field[i].shift)
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& ((((BFD_HOST_U_64_BIT) 1) << bits) - 1)) << total;
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total += bits;
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}
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*valuep = value;
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return 0;
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}
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static const char*
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ins_immus8 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
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{
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if (value & 0x7)
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return "value not an integer multiple of 8";
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return ins_immu (self, value >> 3, code);
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}
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static const char*
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ext_immus8 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
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{
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const char *result;
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result = ext_immu (self, code, valuep);
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if (result)
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return result;
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*valuep = *valuep << 3;
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return 0;
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}
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static const char*
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ins_imms_scaled (const struct ia64_operand *self, ia64_insn value,
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ia64_insn *code, int scale)
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{
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BFD_HOST_64_BIT svalue = value, sign_bit = 0;
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ia64_insn new = 0;
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int i;
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svalue >>= scale;
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for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i)
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{
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new |= ((svalue & ((((ia64_insn) 1) << self->field[i].bits) - 1))
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<< self->field[i].shift);
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sign_bit = (svalue >> (self->field[i].bits - 1)) & 1;
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svalue >>= self->field[i].bits;
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}
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if ((!sign_bit && svalue != 0) || (sign_bit && svalue != -1))
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return "integer operand out of range";
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*code |= new;
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return 0;
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}
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static const char*
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ext_imms_scaled (const struct ia64_operand *self, ia64_insn code,
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ia64_insn *valuep, int scale)
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{
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int i, bits = 0, total = 0, shift;
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BFD_HOST_64_BIT val = 0;
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for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i)
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{
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bits = self->field[i].bits;
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val |= ((code >> self->field[i].shift)
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& ((((BFD_HOST_U_64_BIT) 1) << bits) - 1)) << total;
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total += bits;
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}
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/* sign extend: */
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shift = 8*sizeof (val) - total;
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val = (val << shift) >> shift;
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*valuep = (val << scale);
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return 0;
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}
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static const char*
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ins_imms (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
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{
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return ins_imms_scaled (self, value, code, 0);
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}
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static const char*
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ins_immsu4 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
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{
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if (value == (BFD_HOST_U_64_BIT) 0x100000000)
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value = 0;
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else
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value = (((BFD_HOST_64_BIT)value << 32) >> 32);
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return ins_imms_scaled (self, value, code, 0);
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}
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static const char*
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ext_imms (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
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{
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return ext_imms_scaled (self, code, valuep, 0);
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}
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static const char*
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ins_immsm1 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
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{
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--value;
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return ins_imms_scaled (self, value, code, 0);
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}
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static const char*
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ins_immsm1u4 (const struct ia64_operand *self, ia64_insn value,
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ia64_insn *code)
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{
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if (value == (BFD_HOST_U_64_BIT) 0x100000000)
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value = 0;
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else
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value = (((BFD_HOST_64_BIT)value << 32) >> 32);
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--value;
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return ins_imms_scaled (self, value, code, 0);
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}
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static const char*
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ext_immsm1 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
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{
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const char *res = ext_imms_scaled (self, code, valuep, 0);
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++*valuep;
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return res;
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}
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static const char*
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ins_imms1 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
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{
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return ins_imms_scaled (self, value, code, 1);
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}
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static const char*
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ext_imms1 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
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{
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return ext_imms_scaled (self, code, valuep, 1);
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}
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static const char*
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ins_imms4 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
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{
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return ins_imms_scaled (self, value, code, 4);
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}
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static const char*
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ext_imms4 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
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{
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return ext_imms_scaled (self, code, valuep, 4);
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}
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static const char*
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ins_imms16 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
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{
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return ins_imms_scaled (self, value, code, 16);
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}
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static const char*
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ext_imms16 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
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{
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return ext_imms_scaled (self, code, valuep, 16);
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}
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static const char*
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ins_cimmu (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
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{
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ia64_insn mask = (((ia64_insn) 1) << self->field[0].bits) - 1;
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return ins_immu (self, value ^ mask, code);
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}
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static const char*
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ext_cimmu (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
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{
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const char *result;
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ia64_insn mask;
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mask = (((ia64_insn) 1) << self->field[0].bits) - 1;
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result = ext_immu (self, code, valuep);
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if (!result)
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{
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mask = (((ia64_insn) 1) << self->field[0].bits) - 1;
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*valuep ^= mask;
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}
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return result;
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}
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static const char*
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ins_cnt (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
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{
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--value;
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if (value >= ((BFD_HOST_U_64_BIT) 1) << self->field[0].bits)
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return "count out of range";
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*code |= value << self->field[0].shift;
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return 0;
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}
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static const char*
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ext_cnt (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
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{
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*valuep = ((code >> self->field[0].shift)
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& ((((BFD_HOST_U_64_BIT) 1) << self->field[0].bits) - 1)) + 1;
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return 0;
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}
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static const char*
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ins_cnt2b (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
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{
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--value;
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if (value > 2)
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return "count must be in range 1..3";
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*code |= value << self->field[0].shift;
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return 0;
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}
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static const char*
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ext_cnt2b (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
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{
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*valuep = ((code >> self->field[0].shift) & 0x3) + 1;
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return 0;
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}
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static const char*
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ins_cnt2c (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
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{
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switch (value)
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{
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case 0: value = 0; break;
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case 7: value = 1; break;
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case 15: value = 2; break;
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case 16: value = 3; break;
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default: return "count must be 0, 7, 15, or 16";
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}
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*code |= value << self->field[0].shift;
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return 0;
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}
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static const char*
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ext_cnt2c (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
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{
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ia64_insn value;
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value = (code >> self->field[0].shift) & 0x3;
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switch (value)
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{
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case 0: value = 0; break;
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case 1: value = 7; break;
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case 2: value = 15; break;
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case 3: value = 16; break;
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}
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*valuep = value;
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return 0;
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}
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static const char*
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ins_inc3 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
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{
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BFD_HOST_64_BIT val = value;
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BFD_HOST_U_64_BIT sign = 0;
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if (val < 0)
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{
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sign = 0x4;
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value = -value;
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}
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switch (value)
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{
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case 1: value = 3; break;
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case 4: value = 2; break;
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case 8: value = 1; break;
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case 16: value = 0; break;
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default: return "count must be +/- 1, 4, 8, or 16";
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}
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*code |= (sign | value) << self->field[0].shift;
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return 0;
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}
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static const char*
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ext_inc3 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
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{
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BFD_HOST_64_BIT val;
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int negate;
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val = (code >> self->field[0].shift) & 0x7;
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negate = val & 0x4;
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switch (val & 0x3)
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{
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case 0: val = 16; break;
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case 1: val = 8; break;
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case 2: val = 4; break;
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case 3: val = 1; break;
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}
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if (negate)
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val = -val;
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*valuep = val;
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return 0;
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}
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#define CST IA64_OPND_CLASS_CST
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#define REG IA64_OPND_CLASS_REG
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#define IND IA64_OPND_CLASS_IND
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#define ABS IA64_OPND_CLASS_ABS
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#define REL IA64_OPND_CLASS_REL
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#define SDEC IA64_OPND_FLAG_DECIMAL_SIGNED
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#define UDEC IA64_OPND_FLAG_DECIMAL_UNSIGNED
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const struct ia64_operand elf64_ia64_operands[IA64_OPND_COUNT] =
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{
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/* constants: */
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{ CST, ins_const, ext_const, "NIL", {{ 0, 0}}, 0, "<none>" },
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{ CST, ins_const, ext_const, "ar.csd", {{ 0, 0}}, 0, "ar.csd" },
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{ CST, ins_const, ext_const, "ar.ccv", {{ 0, 0}}, 0, "ar.ccv" },
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{ CST, ins_const, ext_const, "ar.pfs", {{ 0, 0}}, 0, "ar.pfs" },
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{ CST, ins_const, ext_const, "1", {{ 0, 0}}, 0, "1" },
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{ CST, ins_const, ext_const, "8", {{ 0, 0}}, 0, "8" },
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{ CST, ins_const, ext_const, "16", {{ 0, 0}}, 0, "16" },
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{ CST, ins_const, ext_const, "r0", {{ 0, 0}}, 0, "r0" },
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{ CST, ins_const, ext_const, "ip", {{ 0, 0}}, 0, "ip" },
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{ CST, ins_const, ext_const, "pr", {{ 0, 0}}, 0, "pr" },
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{ CST, ins_const, ext_const, "pr.rot", {{ 0, 0}}, 0, "pr.rot" },
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{ CST, ins_const, ext_const, "psr", {{ 0, 0}}, 0, "psr" },
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{ CST, ins_const, ext_const, "psr.l", {{ 0, 0}}, 0, "psr.l" },
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{ CST, ins_const, ext_const, "psr.um", {{ 0, 0}}, 0, "psr.um" },
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/* register operands: */
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{ REG, ins_reg, ext_reg, "ar", {{ 7, 20}}, 0, /* AR3 */
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"an application register" },
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{ REG, ins_reg, ext_reg, "b", {{ 3, 6}}, 0, /* B1 */
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"a branch register" },
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{ REG, ins_reg, ext_reg, "b", {{ 3, 13}}, 0, /* B2 */
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"a branch register"},
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{ REG, ins_reg, ext_reg, "cr", {{ 7, 20}}, 0, /* CR */
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"a control register"},
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{ REG, ins_reg, ext_reg, "f", {{ 7, 6}}, 0, /* F1 */
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"a floating-point register" },
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{ REG, ins_reg, ext_reg, "f", {{ 7, 13}}, 0, /* F2 */
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"a floating-point register" },
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{ REG, ins_reg, ext_reg, "f", {{ 7, 20}}, 0, /* F3 */
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"a floating-point register" },
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{ REG, ins_reg, ext_reg, "f", {{ 7, 27}}, 0, /* F4 */
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"a floating-point register" },
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{ REG, ins_reg, ext_reg, "p", {{ 6, 6}}, 0, /* P1 */
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"a predicate register" },
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{ REG, ins_reg, ext_reg, "p", {{ 6, 27}}, 0, /* P2 */
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"a predicate register" },
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{ REG, ins_reg, ext_reg, "r", {{ 7, 6}}, 0, /* R1 */
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"a general register" },
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{ REG, ins_reg, ext_reg, "r", {{ 7, 13}}, 0, /* R2 */
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"a general register" },
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{ REG, ins_reg, ext_reg, "r", {{ 7, 20}}, 0, /* R3 */
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"a general register" },
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{ REG, ins_reg, ext_reg, "r", {{ 2, 20}}, 0, /* R3_2 */
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"a general register r0-r3" },
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|
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/* indirect operands: */
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{ IND, ins_reg, ext_reg, "cpuid", {{7, 20}}, 0, /* CPUID_R3 */
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"a cpuid register" },
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{ IND, ins_reg, ext_reg, "dbr", {{7, 20}}, 0, /* DBR_R3 */
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"a dbr register" },
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{ IND, ins_reg, ext_reg, "dtr", {{7, 20}}, 0, /* DTR_R3 */
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"a dtr register" },
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{ IND, ins_reg, ext_reg, "itr", {{7, 20}}, 0, /* ITR_R3 */
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"an itr register" },
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{ IND, ins_reg, ext_reg, "ibr", {{7, 20}}, 0, /* IBR_R3 */
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"an ibr register" },
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{ IND, ins_reg, ext_reg, "", {{7, 20}}, 0, /* MR3 */
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|
"an indirect memory address" },
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{ IND, ins_reg, ext_reg, "msr", {{7, 20}}, 0, /* MSR_R3 */
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|
"an msr register" },
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{ IND, ins_reg, ext_reg, "pkr", {{7, 20}}, 0, /* PKR_R3 */
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"a pkr register" },
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{ IND, ins_reg, ext_reg, "pmc", {{7, 20}}, 0, /* PMC_R3 */
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|
"a pmc register" },
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{ IND, ins_reg, ext_reg, "pmd", {{7, 20}}, 0, /* PMD_R3 */
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|
"a pmd register" },
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{ IND, ins_reg, ext_reg, "rr", {{7, 20}}, 0, /* RR_R3 */
|
|
"an rr register" },
|
|
|
|
/* immediate operands: */
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{ ABS, ins_cimmu, ext_cimmu, 0, {{ 5, 20 }}, UDEC, /* CCNT5 */
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|
"a 5-bit count (0-31)" },
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{ ABS, ins_cnt, ext_cnt, 0, {{ 2, 27 }}, UDEC, /* CNT2a */
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"a 2-bit count (1-4)" },
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{ ABS, ins_cnt2b, ext_cnt2b, 0, {{ 2, 27 }}, UDEC, /* CNT2b */
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"a 2-bit count (1-3)" },
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{ ABS, ins_cnt2c, ext_cnt2c, 0, {{ 2, 30 }}, UDEC, /* CNT2c */
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"a count (0, 7, 15, or 16)" },
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{ ABS, ins_immu, ext_immu, 0, {{ 5, 14}}, UDEC, /* CNT5 */
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"a 5-bit count (0-31)" },
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{ ABS, ins_immu, ext_immu, 0, {{ 6, 27}}, UDEC, /* CNT6 */
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"a 6-bit count (0-63)" },
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{ ABS, ins_cimmu, ext_cimmu, 0, {{ 6, 20}}, UDEC, /* CPOS6a */
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"a 6-bit bit pos (0-63)" },
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{ ABS, ins_cimmu, ext_cimmu, 0, {{ 6, 14}}, UDEC, /* CPOS6b */
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|
"a 6-bit bit pos (0-63)" },
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{ ABS, ins_cimmu, ext_cimmu, 0, {{ 6, 31}}, UDEC, /* CPOS6c */
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|
"a 6-bit bit pos (0-63)" },
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{ ABS, ins_imms, ext_imms, 0, {{ 1, 36}}, SDEC, /* IMM1 */
|
|
"a 1-bit integer (-1, 0)" },
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{ ABS, ins_immu, ext_immu, 0, {{ 2, 13}}, UDEC, /* IMMU2 */
|
|
"a 2-bit unsigned (0-3)" },
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{ ABS, ins_immu, ext_immu, 0, {{ 7, 13}}, 0, /* IMMU7a */
|
|
"a 7-bit unsigned (0-127)" },
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{ ABS, ins_immu, ext_immu, 0, {{ 7, 20}}, 0, /* IMMU7b */
|
|
"a 7-bit unsigned (0-127)" },
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{ ABS, ins_immu, ext_immu, 0, {{ 7, 13}}, UDEC, /* SOF */
|
|
"a frame size (register count)" },
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{ ABS, ins_immu, ext_immu, 0, {{ 7, 20}}, UDEC, /* SOL */
|
|
"a local register count" },
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{ ABS, ins_immus8,ext_immus8,0, {{ 4, 27}}, UDEC, /* SOR */
|
|
"a rotating register count (integer multiple of 8)" },
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|
{ ABS, ins_imms, ext_imms, 0, /* IMM8 */
|
|
{{ 7, 13}, { 1, 36}}, SDEC,
|
|
"an 8-bit integer (-128-127)" },
|
|
{ ABS, ins_immsu4, ext_imms, 0, /* IMM8U4 */
|
|
{{ 7, 13}, { 1, 36}}, SDEC,
|
|
"an 8-bit signed integer for 32-bit unsigned compare (-128-127)" },
|
|
{ ABS, ins_immsm1, ext_immsm1, 0, /* IMM8M1 */
|
|
{{ 7, 13}, { 1, 36}}, SDEC,
|
|
"an 8-bit integer (-127-128)" },
|
|
{ ABS, ins_immsm1u4, ext_immsm1, 0, /* IMM8M1U4 */
|
|
{{ 7, 13}, { 1, 36}}, SDEC,
|
|
"an 8-bit integer for 32-bit unsigned compare (-127-(-1),1-128,0x100000000)" },
|
|
{ ABS, ins_immsm1, ext_immsm1, 0, /* IMM8M1U8 */
|
|
{{ 7, 13}, { 1, 36}}, SDEC,
|
|
"an 8-bit integer for 64-bit unsigned compare (-127-(-1),1-128,0x10000000000000000)" },
|
|
{ ABS, ins_immu, ext_immu, 0, {{ 2, 33}, { 7, 20}}, 0, /* IMMU9 */
|
|
"a 9-bit unsigned (0-511)" },
|
|
{ ABS, ins_imms, ext_imms, 0, /* IMM9a */
|
|
{{ 7, 6}, { 1, 27}, { 1, 36}}, SDEC,
|
|
"a 9-bit integer (-256-255)" },
|
|
{ ABS, ins_imms, ext_imms, 0, /* IMM9b */
|
|
{{ 7, 13}, { 1, 27}, { 1, 36}}, SDEC,
|
|
"a 9-bit integer (-256-255)" },
|
|
{ ABS, ins_imms, ext_imms, 0, /* IMM14 */
|
|
{{ 7, 13}, { 6, 27}, { 1, 36}}, SDEC,
|
|
"a 14-bit integer (-8192-8191)" },
|
|
{ ABS, ins_imms1, ext_imms1, 0, /* IMM17 */
|
|
{{ 7, 6}, { 8, 24}, { 1, 36}}, 0,
|
|
"a 17-bit integer (-65536-65535)" },
|
|
{ ABS, ins_immu, ext_immu, 0, {{20, 6}, { 1, 36}}, 0, /* IMMU21 */
|
|
"a 21-bit unsigned" },
|
|
{ ABS, ins_imms, ext_imms, 0, /* IMM22 */
|
|
{{ 7, 13}, { 9, 27}, { 5, 22}, { 1, 36}}, SDEC,
|
|
"a 22-bit signed integer" },
|
|
{ ABS, ins_immu, ext_immu, 0, /* IMMU24 */
|
|
{{21, 6}, { 2, 31}, { 1, 36}}, 0,
|
|
"a 24-bit unsigned" },
|
|
{ ABS, ins_imms16,ext_imms16,0, {{27, 6}, { 1, 36}}, 0, /* IMM44 */
|
|
"a 44-bit unsigned (least 16 bits ignored/zeroes)" },
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|
{ ABS, ins_rsvd, ext_rsvd, 0, {{0, 0}}, 0, /* IMMU62 */
|
|
"a 62-bit unsigned" },
|
|
{ ABS, ins_rsvd, ext_rsvd, 0, {{0, 0}}, 0, /* IMMU64 */
|
|
"a 64-bit unsigned" },
|
|
{ ABS, ins_inc3, ext_inc3, 0, {{ 3, 13}}, SDEC, /* INC3 */
|
|
"an increment (+/- 1, 4, 8, or 16)" },
|
|
{ ABS, ins_cnt, ext_cnt, 0, {{ 4, 27}}, UDEC, /* LEN4 */
|
|
"a 4-bit length (1-16)" },
|
|
{ ABS, ins_cnt, ext_cnt, 0, {{ 6, 27}}, UDEC, /* LEN6 */
|
|
"a 6-bit length (1-64)" },
|
|
{ ABS, ins_immu, ext_immu, 0, {{ 4, 20}}, 0, /* MBTYPE4 */
|
|
"a mix type (@rev, @mix, @shuf, @alt, or @brcst)" },
|
|
{ ABS, ins_immu, ext_immu, 0, {{ 8, 20}}, 0, /* MBTYPE8 */
|
|
"an 8-bit mix type" },
|
|
{ ABS, ins_immu, ext_immu, 0, {{ 6, 14}}, UDEC, /* POS6 */
|
|
"a 6-bit bit pos (0-63)" },
|
|
{ REL, ins_imms4, ext_imms4, 0, {{ 7, 6}, { 2, 33}}, 0, /* TAG13 */
|
|
"a branch tag" },
|
|
{ REL, ins_imms4, ext_imms4, 0, {{ 9, 24}}, 0, /* TAG13b */
|
|
"a branch tag" },
|
|
{ REL, ins_imms4, ext_imms4, 0, {{20, 6}, { 1, 36}}, 0, /* TGT25 */
|
|
"a branch target" },
|
|
{ REL, ins_imms4, ext_imms4, 0, /* TGT25b */
|
|
{{ 7, 6}, {13, 20}, { 1, 36}}, 0,
|
|
"a branch target" },
|
|
{ REL, ins_imms4, ext_imms4, 0, {{20, 13}, { 1, 36}}, 0, /* TGT25c */
|
|
"a branch target" },
|
|
{ REL, ins_rsvd, ext_rsvd, 0, {{0, 0}}, 0, /* TGT64 */
|
|
"a branch target" },
|
|
|
|
{ ABS, ins_const, ext_const, 0, {{0, 0}}, 0, /* LDXMOV */
|
|
"ldxmov target" },
|
|
};
|