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b955f68067
sparcl-tdep.c sparcl-stub.c Removed Files: sparclite-tdep.c sparclite-stub.c * change file name because fisrt 8 chars has to be unique.
211 lines
5.0 KiB
C
211 lines
5.0 KiB
C
/* Target-dependent code for the Fujitsu SPARCLITE for GDB, the GNU debugger.
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Copyright 1994 Free Software Foundation, Inc.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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#include "defs.h"
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#include "gdbcore.h"
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#include "breakpoint.h"
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#define DDA2_SUP_ASI 0xb000000
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#define DDA1_SUP_ASI 0xb0000
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#define DDA2_ASI_MASK 0xff000000
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#define DDA1_ASI_MASK 0xff0000
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#define DIA2_SUP_MODE 0x8000
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#define DIA1_SUP_MODE 0x4000
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#define DDA2_ENABLE 0x100
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#define DDA1_ENABLE 0x80
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#define DIA2_ENABLE 0x40
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#define DIA1_ENABLE 0x20
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#define DSINGLE_STEP 0x10
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#define DDV_TYPE_MASK 0xc
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#define DDV_TYPE_LOAD 0x0
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#define DDV_TYPE_STORE 0x4
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#define DDV_TYPE_ACCESS 0x8
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#define DDV_TYPE_ALWAYS 0xc
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#define DDV_COND 0x2
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#define DDV_MASK 0x1
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int
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sparclite_insert_watchpoint(addr, len, type)
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CORE_ADDR addr;
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int len;
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int type;
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{
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CORE_ADDR dcr;
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dcr = read_register (DCR_REGNUM);
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if (!(dcr & DDA1_ENABLE))
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{
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write_register (DDA1_REGNUM, addr);
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dcr &= ~(DDA1_ASI_MASK | DDV_TYPE_MASK);
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dcr |= (DDA1_SUP_ASI | DDA1_ENABLE);
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if (type == 1)
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{
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write_register (DDV1_REGNUM, 0);
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write_register (DDV2_REGNUM, 0xffffffff);
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dcr |= (DDV_TYPE_LOAD & (~DDV_COND & ~DDV_MASK));
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}
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else if (type == 0)
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{
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write_register (DDV1_REGNUM, 0);
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write_register (DDV2_REGNUM, 0xffffffff);
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dcr |= (DDV_TYPE_STORE & (~DDV_COND & ~DDV_MASK));
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}
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else
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{
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write_register (DDV1_REGNUM, 0);
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write_register (DDV2_REGNUM, 0xffffffff);
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dcr |= (DDV_TYPE_ACCESS);
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}
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write_register (DCR_REGNUM, dcr);
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}
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else if (!(dcr & DDA2_ENABLE))
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{
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write_register (DDA2_REGNUM, addr);
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dcr &= ~(DDA2_ASI_MASK & DDV_TYPE_MASK);
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dcr |= (DDA2_SUP_ASI | DDA2_ENABLE);
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if (type == 1)
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{
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write_register (DDV1_REGNUM, 0);
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write_register (DDV2_REGNUM, 0xffffffff);
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dcr |= (DDV_TYPE_LOAD & ~DDV_COND & ~DDV_MASK);
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}
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else if (type == 0)
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{
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write_register (DDV1_REGNUM, 0);
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write_register (DDV2_REGNUM, 0xffffffff);
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dcr |= (DDV_TYPE_STORE & ~DDV_COND & ~DDV_MASK);
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}
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else
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{
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write_register (DDV1_REGNUM, 0);
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write_register (DDV2_REGNUM, 0xffffffff);
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dcr |= (DDV_TYPE_ACCESS);
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}
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write_register (DCR_REGNUM, dcr);
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}
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else
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return -1;
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return 0;
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}
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int
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sparclite_remove_watchpoint(addr, len, type)
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CORE_ADDR addr;
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int len;
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int type;
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{
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CORE_ADDR dcr, dda1, dda2;
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dcr = read_register (DCR_REGNUM);
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dda1 = read_register (DDA1_REGNUM);
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dda2 = read_register (DDA2_REGNUM);
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if ((dcr & DDA1_ENABLE) && addr == dda1) {
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write_register (DCR_REGNUM, (dcr & ~DDA1_ENABLE));
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}
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else if ((dcr & DDA2_ENABLE) && addr == dda2) {
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write_register (DCR_REGNUM, (dcr & ~DDA2_ENABLE));
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}
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else
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return -1;
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return 0;
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}
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int
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sparclite_insert_hw_breakpoint(addr, len)
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CORE_ADDR addr;
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int len;
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{
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CORE_ADDR dcr;
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dcr = read_register (DCR_REGNUM);
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if (!(dcr & DIA1_ENABLE)) {
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write_register (DIA1_REGNUM, addr);
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write_register (DCR_REGNUM, (dcr | DIA1_ENABLE | DIA1_SUP_MODE));
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}
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else if (!(dcr & DIA2_ENABLE)) {
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write_register (DIA2_REGNUM, addr);
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write_register (DCR_REGNUM, (dcr | DIA2_ENABLE | DIA2_SUP_MODE));
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}
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else
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return -1;
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return 0;
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}
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int
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sparclite_remove_hw_breakpoint(addr, shadow)
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CORE_ADDR addr;
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int shadow;
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{
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CORE_ADDR dcr, dia1, dia2;
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dcr = read_register (DCR_REGNUM);
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dia1 = read_register (DIA1_REGNUM);
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dia2 = read_register (DIA2_REGNUM);
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if ((dcr & DIA1_ENABLE) && addr == dia1) {
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write_register (DCR_REGNUM, (dcr & ~DIA1_ENABLE));
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}
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else if ((dcr & DIA2_ENABLE) && addr == dia2) {
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write_register (DCR_REGNUM, (dcr & ~DIA2_ENABLE));
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}
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else
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return -1;
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return 0;
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}
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int
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sparclite_check_watch_resources(type, cnt, ot)
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int type;
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int cnt;
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int ot;
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{
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if (type == bp_hardware_breakpoint) {
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if (TARGET_HW_BREAK_LIMIT == 0) return 0;
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else if (cnt <= TARGET_HW_BREAK_LIMIT) return 1;
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}
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else {
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if (TARGET_HW_WATCH_LIMIT == 0) return 0;
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else if (ot) return -1;
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else if (cnt <= TARGET_HW_WATCH_LIMIT) return 1;
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}
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return -1;
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}
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CORE_ADDR
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sparclite_stopped_data_address()
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{
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CORE_ADDR dsr, dda1, dda2;
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dsr = read_register (DSR_REGNUM);
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dda1 = read_register (DDA1_REGNUM);
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dda2 = read_register (DDA2_REGNUM);
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if (dsr & 0x10) return dda1;
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else if (dsr & 0x20) return dda2;
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else return 0;
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}
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