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These files are source files and have no business being +x. We couldn't easily fix it in CVS (you need login+write access to the raw rcs files), but we can fix this w/git. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
417 lines
10 KiB
C
417 lines
10 KiB
C
/* Adapteva epiphany opcode support. -*- C -*-
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Copyright 2009, 2011 Free Software Foundation, Inc.
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Contributed by Embecosm on behalf of Adapteva, Inc.
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This file is part of the GNU Binutils and of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
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MA 02110-1301, USA. */
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/*
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Each section is delimited with start and end markers.
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<arch>-opc.h additions use: "-- opc.h"
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<arch>-opc.c additions use: "-- opc.c"
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<arch>-asm.c additions use: "-- asm.c"
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<arch>-dis.c additions use: "-- dis.c"
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<arch>-ibd.h additions use: "-- ibd.h". */
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/* -- opc.h */
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/* enumerate relaxation types for gas. */
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typedef enum epiphany_relax_types
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{
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EPIPHANY_RELAX_NONE=0,
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EPIPHANY_RELAX_NEED_RELAXING,
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EPIPHANY_RELAX_BRANCH_SHORT, /* Fits into +127..-128 */
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EPIPHANY_RELAX_BRANCH_LONG, /* b/bl/b<cond> +-2*16 */
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EPIPHANY_RELAX_ARITH_SIMM3, /* add/sub -7..3 */
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EPIPHANY_RELAX_ARITH_SIMM11, /* add/sub -2**11-1 .. 2**10-1 */
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EPIPHANY_RELAX_MOV_IMM8, /* mov r,imm8 */
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EPIPHANY_RELAX_MOV_IMM16, /* mov r,imm16 */
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EPIPHANY_RELAX_LDST_IMM3, /* (ldr|str)* r,[r,disp3] */
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EPIPHANY_RELAX_LDST_IMM11 /* (ldr|str)* r,[r,disp11] */
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} EPIPHANY_RELAX_TYPES;
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/* Override disassembly hashing... */
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/* Can only depend on instruction having 4 decode bits which gets us to the
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major groups of 16/32 instructions. */
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#undef CGEN_DIS_HASH_SIZE
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#if 1
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/* hash code on the 4 LSBs */
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#define CGEN_DIS_HASH_SIZE 16
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#define CGEN_DIS_HASH(buf, value) ((*buf) & 0xf)
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#else
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#define CGEN_DIS_HASH_SIZE 1
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#define CGEN_DIS_HASH(buf, value) 0
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#endif
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extern const char * parse_shortregs (CGEN_CPU_DESC cd,
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const char ** strp,
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CGEN_KEYWORD * keywords,
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long * valuep);
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extern const char * parse_branch_addr (CGEN_CPU_DESC cd,
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const char ** strp,
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int opindex,
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int opinfo,
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enum cgen_parse_operand_result * resultp,
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bfd_vma *valuep);
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/* Allows reason codes to be output when assembler errors occur. */
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#define CGEN_VERBOSE_ASSEMBLER_ERRORS
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/* -- opc.c */
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/* -- asm.c */
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const char *
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parse_shortregs (CGEN_CPU_DESC cd,
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const char ** strp,
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CGEN_KEYWORD * keywords,
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long * regno)
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{
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const char * errmsg;
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/* Parse register. */
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errmsg = cgen_parse_keyword (cd, strp, keywords, regno);
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if (errmsg)
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return errmsg;
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if (*regno > 7)
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errmsg = _("register unavailable for short instructions");
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return errmsg;
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}
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static const char * parse_simm_not_reg (CGEN_CPU_DESC, const char **, int,
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long *);
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static const char *
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parse_uimm_not_reg (CGEN_CPU_DESC cd,
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const char ** strp,
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int opindex,
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unsigned long * valuep)
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{
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long * svalp = (void *) valuep;
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return parse_simm_not_reg (cd, strp, opindex, svalp);
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}
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/* Handle simm3/simm11/imm3/imm12. */
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static const char *
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parse_simm_not_reg (CGEN_CPU_DESC cd,
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const char ** strp,
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int opindex,
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long * valuep)
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{
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const char * errmsg;
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int sign = 0;
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int bits = 0;
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switch (opindex)
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{
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case EPIPHANY_OPERAND_SIMM3:
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sign = 1; bits = 3; break;
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case EPIPHANY_OPERAND_SIMM11:
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sign = 1; bits = 11; break;
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case EPIPHANY_OPERAND_DISP3:
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sign = 0; bits = 3; break;
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case EPIPHANY_OPERAND_DISP11:
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/* Load/store displacement is a sign-magnitude 12 bit value. */
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sign = 0; bits = 11; break;
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}
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/* First try to parse as a register name and reject the operand. */
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errmsg = cgen_parse_keyword (cd, strp, & epiphany_cgen_opval_gr_names,valuep);
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if (!errmsg)
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return _("register name used as immediate value");
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errmsg = (sign ? cgen_parse_signed_integer (cd, strp, opindex, valuep)
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: cgen_parse_unsigned_integer (cd, strp, opindex,
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(unsigned long *) valuep));
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if (errmsg)
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return errmsg;
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if (sign)
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errmsg = cgen_validate_signed_integer (*valuep,
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-((1L << bits) - 1), (1 << (bits - 1)) - 1);
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else
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errmsg = cgen_validate_unsigned_integer (*valuep, 0, (1L << bits) - 1);
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return errmsg;
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}
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static const char *
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parse_postindex (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
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const char ** strp,
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int opindex ATTRIBUTE_UNUSED,
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unsigned long *valuep)
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{
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if (**strp == '#')
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++*strp; /* Skip leading hashes. */
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if (**strp == '-')
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{
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*valuep = 1;
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++*strp;
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}
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else if (**strp == '+')
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{
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*valuep = 0;
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++*strp;
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}
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else
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*valuep = 0;
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return NULL;
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}
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static const char *
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parse_imm8 (CGEN_CPU_DESC cd,
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const char ** strp,
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int opindex,
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bfd_reloc_code_real_type code,
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enum cgen_parse_operand_result * result_type,
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bfd_vma * valuep)
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{
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const char * errmsg;
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enum cgen_parse_operand_result rt;
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long dummyval;
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if (!result_type)
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result_type = &rt;
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code = BFD_RELOC_NONE;
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if (!cgen_parse_keyword (cd, strp, &epiphany_cgen_opval_gr_names, &dummyval)
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|| !cgen_parse_keyword (cd, strp, &epiphany_cgen_opval_cr_names,
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&dummyval))
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/* Don't treat "mov ip,ip" as a move-immediate. */
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return _("register source in immediate move");
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errmsg = cgen_parse_address (cd, strp, opindex, code, result_type, valuep);
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if (errmsg)
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return errmsg;
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if (*result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
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errmsg = cgen_validate_unsigned_integer (*valuep, 0, 0xff);
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else
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errmsg = _("byte relocation unsupported");
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*valuep &= 0xff;
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return errmsg;
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}
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static const char * MISSING_CLOSE_PARENTHESIS = N_("missing `)'");
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static const char *
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parse_imm16 (CGEN_CPU_DESC cd,
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const char ** strp,
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int opindex,
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bfd_reloc_code_real_type code ATTRIBUTE_UNUSED,
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enum cgen_parse_operand_result * result_type,
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bfd_vma * valuep)
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{
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const char * errmsg;
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enum cgen_parse_operand_result rt;
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long dummyval;
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if (!result_type)
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result_type = &rt;
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if (strncasecmp (*strp, "%high(", 6) == 0)
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{
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*strp += 6;
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errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_EPIPHANY_HIGH,
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result_type, valuep);
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if (**strp != ')')
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return MISSING_CLOSE_PARENTHESIS;
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++*strp;
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*valuep >>= 16;
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}
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else if (strncasecmp (*strp, "%low(", 5) == 0)
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{
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*strp += 5;
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errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_EPIPHANY_LOW,
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result_type, valuep);
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if (**strp != ')')
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return MISSING_CLOSE_PARENTHESIS;
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++*strp;
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}
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else if (!cgen_parse_keyword (cd, strp, &epiphany_cgen_opval_gr_names,
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&dummyval)
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|| !cgen_parse_keyword (cd, strp, &epiphany_cgen_opval_cr_names,
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&dummyval))
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/* Don't treat "mov ip,ip" as a move-immediate. */
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return _("register source in immediate move");
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else
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errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_16,
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result_type, valuep);
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if (!errmsg && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
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errmsg = cgen_validate_unsigned_integer (*valuep, 0, 0xffff);
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*valuep &= 0xffff;
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return errmsg;
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}
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const char *
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parse_branch_addr (CGEN_CPU_DESC cd,
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const char ** strp,
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int opindex,
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int opinfo ATTRIBUTE_UNUSED,
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enum cgen_parse_operand_result * resultp ATTRIBUTE_UNUSED,
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bfd_vma *valuep ATTRIBUTE_UNUSED)
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{
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const char * errmsg;
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enum cgen_parse_operand_result result_type;
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bfd_reloc_code_real_type code = BFD_RELOC_NONE;
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bfd_vma value;
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switch (opindex)
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{
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case EPIPHANY_OPERAND_SIMM24:
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code = BFD_RELOC_EPIPHANY_SIMM24;
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break;
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case EPIPHANY_OPERAND_SIMM8:
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code = BFD_RELOC_EPIPHANY_SIMM8;
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break;
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default:
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errmsg = _("ABORT: unknown operand");
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return errmsg;
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}
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errmsg = cgen_parse_address (cd, strp, opindex, code,
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&result_type, &value);
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if (errmsg == NULL)
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{
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if (result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
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{
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/* Act as if we had done a PC-relative branch, ala .+num. */
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char buf[20];
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const char * bufp = (const char *) buf;
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sprintf (buf, ".+%ld", (long) value);
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errmsg = cgen_parse_address (cd, &bufp, opindex, code, &result_type,
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&value);
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}
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if (result_type == CGEN_PARSE_OPERAND_RESULT_QUEUED)
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{
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/* This will happen for things like (s2-s1) where s2 and s1
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are labels. */
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/* Nothing further to be done. */
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}
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else
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errmsg = _("Not a pc-relative address.");
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}
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return errmsg;
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}
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/* -- dis.c */
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#define CGEN_PRINT_INSN epiphany_print_insn
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static int
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epiphany_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
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{
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bfd_byte buf[CGEN_MAX_INSN_SIZE];
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int buflen;
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int status;
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info->bytes_per_chunk = 2;
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/* Attempt to read the base part of the insn. */
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info->bytes_per_line = buflen = cd->base_insn_bitsize / 8;
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status = (*info->read_memory_func) (pc, buf, buflen, info);
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/* Try again with the minimum part, if min < base. */
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if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize))
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{
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info->bytes_per_line = buflen = cd->min_insn_bitsize / 8;
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status = (*info->read_memory_func) (pc, buf, buflen, info);
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}
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if (status != 0)
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{
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(*info->memory_error_func) (status, pc, info);
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return -1;
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}
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return print_insn (cd, pc, info, buf, buflen);
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}
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static void
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print_postindex (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
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void * dis_info,
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long value,
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unsigned int attrs ATTRIBUTE_UNUSED,
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bfd_vma pc ATTRIBUTE_UNUSED,
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int length ATTRIBUTE_UNUSED)
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{
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disassemble_info *info = (disassemble_info *) dis_info;
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(*info->fprintf_func) (info->stream, value ? "-" : "+");
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}
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static void
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print_simm_not_reg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
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void * dis_info,
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long value,
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unsigned int attrs ATTRIBUTE_UNUSED,
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bfd_vma pc ATTRIBUTE_UNUSED,
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int length ATTRIBUTE_UNUSED)
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{
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print_address (cd, dis_info, value, attrs, pc, length);
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}
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static void
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print_uimm_not_reg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
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void * dis_info,
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unsigned long value,
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unsigned int attrs ATTRIBUTE_UNUSED,
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bfd_vma pc ATTRIBUTE_UNUSED,
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int length ATTRIBUTE_UNUSED)
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{
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disassemble_info *info = (disassemble_info *)dis_info;
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if (value & 0x800)
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(*info->fprintf_func) (info->stream, "-");
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value &= 0x7ff;
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print_address (cd, dis_info, value, attrs, pc, length);
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}
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/* -- */
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