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435 lines
8.6 KiB
C
435 lines
8.6 KiB
C
/* Support code for various pieces of CGEN simulators.
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Copyright (C) 1996, 1997 Free Software Foundation, Inc.
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Contributed by Cygnus Support.
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This file is part of GDB, the GNU debugger.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License along
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with this program; if not, write to the Free Software Foundation, Inc.,
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59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#include "sim-main.h"
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#include <signal.h>
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#include "dis-asm.h"
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#include "cpu-opc.h"
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#include "decode.h"
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#define MEMOPS_DEFINE_INLINE
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#include "mem-ops.h"
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#define SEMOPS_DEFINE_INLINE
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#include "sem-ops.h"
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const char *mode_names[] = {
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"VM",
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"BI",
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"QI",
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"HI",
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"SI",
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"DI",
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"UBI",
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"UQI",
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"UHI",
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"USI",
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"UDI",
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"SF",
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"DF",
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"XF",
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"TF",
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};
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/* Initialize cgen things.
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This is called after sim_post_argv_init. */
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void
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cgen_init (SIM_DESC sd)
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{
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int i, c;
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int run_fast_p = 1;
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/* If no profiling or tracing has been enabled, run in fast mode. */
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for (c = 0; c < MAX_NR_PROCESSORS; ++c)
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{
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sim_cpu *cpu = STATE_CPU (sd, c);
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for (i = 0; i < MAX_PROFILE_VALUES; ++i)
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if (CPU_PROFILE_FLAGS (cpu) [i])
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{
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run_fast_p = 0;
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break;
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}
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for (i = 0; i < MAX_TRACE_VALUES; ++i)
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if (CPU_TRACE_FLAGS (cpu) [i])
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{
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run_fast_p = 0;
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break;
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}
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if (! run_fast_p)
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break;
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}
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STATE_RUN_FAST_P (sd) = run_fast_p;
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}
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void
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engine_halt (cpu, reason, sigrc)
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sim_cpu *cpu;
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enum exec_state reason;
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int sigrc;
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{
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CPU_EXEC_STATE (cpu) = reason;
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CPU_HALT_SIGRC (cpu) = sigrc;
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longjmp (STATE_HALT_JMP_BUF (CPU_STATE (cpu)), 1);
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}
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void
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engine_signal (cpu, sig)
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sim_cpu *cpu;
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enum sim_signal_type sig;
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{
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engine_halt (cpu, EXEC_STATE_STOPPED, sig);
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}
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/* Convert SIM_SIGFOO to SIGFOO. */
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int
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sim_signal_to_host (sig)
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int sig;
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{
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switch (sig)
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{
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case SIM_SIGILL :
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#ifdef SIGILL
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return SIGILL;
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#endif
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break;
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case SIM_SIGTRAP :
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#ifdef SIGTRAP
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return SIGTRAP;
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#else
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#ifdef _MSC_VER
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/* Wingdb uses this value. */
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return 5;
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#endif
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#endif
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break;
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case SIM_SIGALIGN :
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case SIM_SIGACCESS :
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#ifdef SIGSEGV
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return SIGSEGV;
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#endif
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break;
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case SIM_SIGXCPU :
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#ifdef SIGXCPU
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return SIGXCPU;
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#endif
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break;
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}
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return 1;
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}
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/* FIXME: Add "no return" attribute to illegal insn handlers.
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They all call longjmp. */
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/* FIXME: May wish to call a target supplied routine which can then call
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sim_halt if it wants: to allow target to gain control for moment. */
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void
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ex_illegal (SIM_CPU *cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
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{
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abuf->length = CGEN_BASE_INSN_SIZE;
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abuf->addr = pc;
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/* Leave signalling to semantic fn. */
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}
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void
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exc_illegal (SIM_CPU *cpu, PCADDR pc, insn_t insn, ARGBUF *abuf)
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{
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abuf->length = CGEN_BASE_INSN_SIZE;
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abuf->addr = pc;
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/* Leave signalling to semantic fn. */
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}
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PCADDR
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sem_illegal (current_cpu, sem_arg)
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SIM_CPU *current_cpu;
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struct argbuf *sem_arg;
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{
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engine_halt (current_cpu, EXEC_STATE_SIGNALLED, SIM_SIGILL);
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return 0;
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}
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PCADDR
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semc_illegal (current_cpu, sem_arg)
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SIM_CPU *current_cpu;
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struct scache *sem_arg;
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{
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engine_halt (current_cpu, EXEC_STATE_SIGNALLED, SIM_SIGILL);
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return 0;
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}
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/* Disassembly support.
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??? While executing an instruction, the insn has been decoded and all its
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fields have been extracted. It is certainly possible to do the disassembly
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with that data. This seems simpler, but maybe in the future the already
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extracted fields will be used. */
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/* Pseudo FILE object for strings. */
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typedef struct {
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char *buffer;
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char *current;
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} SFILE;
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/* sprintf to a "stream" */
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static int
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disasm_sprintf VPARAMS ((SFILE *f, const char *format, ...))
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{
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#ifndef __STDC__
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SFILE *f;
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const char *format;
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#endif
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int n;
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va_list args;
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VA_START (args, format);
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#ifndef __STDC__
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f = va_arg (args, SFILE *);
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format = va_arg (args, char *);
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#endif
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vsprintf (f->current, format, args);
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f->current += n = strlen (f->current);
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va_end (args);
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return n;
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}
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void
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sim_disassemble_insn (SIM_CPU *cpu, const struct cgen_insn *insn,
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const struct argbuf *abuf, PCADDR pc, char *buf)
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{
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int length;
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unsigned long insn_value;
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struct disassemble_info disasm_info;
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struct cgen_fields fields;
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SFILE sfile;
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char insn_buf[20];
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SIM_DESC sd = CPU_STATE (cpu);
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sfile.buffer = sfile.current = buf;
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INIT_DISASSEMBLE_INFO (disasm_info, (FILE *) &sfile,
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(fprintf_ftype) disasm_sprintf);
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disasm_info.endian =
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(bfd_big_endian (STATE_PROG_BFD (sd)) ? BFD_ENDIAN_BIG
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: bfd_little_endian (STATE_PROG_BFD (sd)) ? BFD_ENDIAN_LITTLE
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: BFD_ENDIAN_UNKNOWN);
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switch (abuf->length)
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{
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case 1 :
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insn_value = sim_core_read_1 (CPU_STATE (cpu), sim_core_read_map, pc, NULL, NULL_CIA);
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break;
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case 2 :
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insn_value = sim_core_read_2 (CPU_STATE (cpu), sim_core_read_map, pc, NULL, NULL_CIA);
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break;
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case 4 :
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insn_value = sim_core_read_4 (CPU_STATE (cpu), sim_core_read_map, pc, NULL, NULL_CIA);
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break;
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default:
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abort ();
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}
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length = (*CGEN_EXTRACT_FN (insn)) (insn, NULL, insn_value, &fields);
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if (length != abuf->length)
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{
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(*CGEN_PRINT_FN (insn)) (&disasm_info, insn, &fields, pc, length);
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}
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else
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{
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/* This shouldn't happen, but aborting is too drastic. */
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strcpy (buf, "***unknown***");
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}
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}
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#ifdef DI_FN_SUPPORT
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DI
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make_struct_di (hi, lo)
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SI hi, lo;
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{
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DI result;
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result.hi = hi;
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result.lo = lo;
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return result;
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}
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DI
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ANDDI (a, b)
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DI a, b;
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{
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SI ahi = GETHIDI (a);
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SI alo = GETLODI (a);
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SI bhi = GETHIDI (b);
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SI blo = GETLODI (b);
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return MAKEDI (ahi & bhi, alo & blo);
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}
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DI
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ORDI (a, b)
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DI a, b;
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{
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SI ahi = GETHIDI (a);
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SI alo = GETLODI (a);
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SI bhi = GETHIDI (b);
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SI blo = GETLODI (b);
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return MAKEDI (ahi | bhi, alo | blo);
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}
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DI
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ADDDI (a, b)
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DI a, b;
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{
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USI ahi = GETHIDI (a);
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USI alo = GETLODI (a);
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USI bhi = GETHIDI (b);
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USI blo = GETLODI (b);
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USI x = alo + blo;
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return MAKEDI (ahi + bhi + (x < alo), x);
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}
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DI
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MULDI (a, b)
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DI a, b;
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{
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USI ahi = GETHIDI (a);
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USI alo = GETLODI (a);
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USI bhi = GETHIDI (b);
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USI blo = GETLODI (b);
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USI rhi,rlo;
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USI x0, x1, x2, x3;
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x0 = alo * blo;
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x1 = alo * bhi;
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x2 = ahi * blo;
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x3 = ahi * bhi;
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#define SI_TYPE_SIZE 32
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#define BITS4 (SI_TYPE_SIZE / 4)
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#define ll_B (1L << (SI_TYPE_SIZE / 2))
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#define ll_lowpart(t) ((USI) (t) % ll_B)
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#define ll_highpart(t) ((USI) (t) / ll_B)
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x1 += ll_highpart (x0); /* this can't give carry */
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x1 += x2; /* but this indeed can */
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if (x1 < x2) /* did we get it? */
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x3 += ll_B; /* yes, add it in the proper pos. */
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rhi = x3 + ll_highpart (x1);
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rlo = ll_lowpart (x1) * ll_B + ll_lowpart (x0);
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return MAKEDI (rhi + (alo * bhi) + (ahi * blo), rlo);
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}
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DI
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SHLDI (val, shift)
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DI val;
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SI shift;
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{
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USI hi = GETHIDI (val);
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USI lo = GETLODI (val);
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/* FIXME: Need to worry about shift < 0 || shift >= 32. */
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return MAKEDI ((hi << shift) | (lo >> (32 - shift)), lo << shift);
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}
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DI
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SLADI (val, shift)
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DI val;
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SI shift;
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{
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SI hi = GETHIDI (val);
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USI lo = GETLODI (val);
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/* FIXME: Need to worry about shift < 0 || shift >= 32. */
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return MAKEDI ((hi << shift) | (lo >> (32 - shift)), lo << shift);
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}
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DI
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SRADI (val, shift)
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DI val;
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SI shift;
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{
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SI hi = GETHIDI (val);
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USI lo = GETLODI (val);
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/* We use SRASI because the result is implementation defined if hi < 0. */
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/* FIXME: Need to worry about shift < 0 || shift >= 32. */
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return MAKEDI (SRASI (hi, shift), (hi << (32 - shift)) | (lo >> shift));
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}
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int
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GEDI (a, b)
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DI a, b;
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{
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SI ahi = GETHIDI (a);
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USI alo = GETLODI (a);
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SI bhi = GETHIDI (b);
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USI blo = GETLODI (b);
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if (ahi > bhi)
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return 1;
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if (ahi == bhi)
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return alo >= blo;
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return 0;
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}
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int
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LEDI (a, b)
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DI a, b;
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{
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SI ahi = GETHIDI (a);
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USI alo = GETLODI (a);
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SI bhi = GETHIDI (b);
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USI blo = GETLODI (b);
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if (ahi < bhi)
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return 1;
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if (ahi == bhi)
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return alo <= blo;
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return 0;
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}
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DI
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CONVHIDI (val)
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HI val;
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{
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if (val < 0)
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return MAKEDI (-1, val);
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else
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return MAKEDI (0, val);
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}
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DI
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CONVSIDI (val)
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SI val;
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{
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if (val < 0)
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return MAKEDI (-1, val);
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else
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return MAKEDI (0, val);
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}
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SI
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CONVDISI (val)
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DI val;
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{
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return GETLODI (val);
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}
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#endif /* DI_FN_SUPPORT */
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