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50b81f1903
gas/ * config/tc-ia64.c (specify_resource, case IA64_RS_GR): Handle postincrement modified registers. Handle IA64_OPND_R3_2 addl source registers. (note_register_values): Handle IA64_OPND_R3_2 operands. gas/testsuite/ * gas/ia64/dv-raw-err.s: Add new tests for addl and postinc. * gas/ia64/dv-raw-err.l: Likewise. * gas/ia64/dv-waw-err.l: Update sed pattern. * gas/ia64/opc-f.pl: Delete fpsub, and fpadd comment. * gas/ia64/opc-f.s, gas/ia64/opc-f.d: Regenerate. include/opcode/ * ia64.h (IA64_OPCODE_POSTINC): New. opcodes/ * ia64-ic.tbl (pr-readers-nobr-nomovpr): Add addl, adds. Delete break, mov-immediate, nop. * ia64-opc-f.c: Delete fpsub instructions. * ia64-opc-m.c: Add POSTINC to all instructions with postincrement address operand. Rewrite using macros to avoid long lines. * ia64-opc.h (POSTINC): Define. * ia64-asmtab.c: Regenerate.
131 lines
3.9 KiB
C
131 lines
3.9 KiB
C
/* ia64-opc.h -- IA-64 opcode table.
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Copyright (C) 1998, 1999 Free Software Foundation, Inc.
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Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
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This file is part of GDB, GAS, and the GNU binutils.
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GDB, GAS, and the GNU binutils are free software; you can redistribute
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them and/or modify them under the terms of the GNU General Public
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License as published by the Free Software Foundation; either version
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2, or (at your option) any later version.
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GDB, GAS, and the GNU binutils are distributed in the hope that they
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will be useful, but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
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the GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this file; see the file COPYING. If not, write to the
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Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA
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02111-1307, USA. */
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#ifndef IA64_OPC_H
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#define IA64_OPC_H
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#include "opcode/ia64.h"
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/* define a couple of abbreviations: */
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#define bOp(x) (((ia64_insn) ((x) & 0xf)) << 37)
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#define mOp bOp (-1)
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#define Op(x) bOp (x), mOp
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#define FIRST IA64_OPCODE_FIRST
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#define X_IN_MLX IA64_OPCODE_X_IN_MLX
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#define LAST IA64_OPCODE_LAST
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#define PRIV IA64_OPCODE_PRIV
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#define NO_PRED IA64_OPCODE_NO_PRED
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#define SLOT2 IA64_OPCODE_SLOT2
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#define PSEUDO IA64_OPCODE_PSEUDO
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#define F2_EQ_F3 IA64_OPCODE_F2_EQ_F3
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#define LEN_EQ_64MCNT IA64_OPCODE_LEN_EQ_64MCNT
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#define MOD_RRBS IA64_OPCODE_MOD_RRBS
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#define POSTINC IA64_OPCODE_POSTINC
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#define AR_CCV IA64_OPND_AR_CCV
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#define AR_PFS IA64_OPND_AR_PFS
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#define C1 IA64_OPND_C1
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#define C8 IA64_OPND_C8
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#define C16 IA64_OPND_C16
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#define GR0 IA64_OPND_GR0
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#define IP IA64_OPND_IP
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#define PR IA64_OPND_PR
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#define PR_ROT IA64_OPND_PR_ROT
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#define PSR IA64_OPND_PSR
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#define PSR_L IA64_OPND_PSR_L
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#define PSR_UM IA64_OPND_PSR_UM
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#define AR3 IA64_OPND_AR3
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#define B1 IA64_OPND_B1
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#define B2 IA64_OPND_B2
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#define CR3 IA64_OPND_CR3
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#define F1 IA64_OPND_F1
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#define F2 IA64_OPND_F2
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#define F3 IA64_OPND_F3
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#define F4 IA64_OPND_F4
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#define P1 IA64_OPND_P1
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#define P2 IA64_OPND_P2
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#define R1 IA64_OPND_R1
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#define R2 IA64_OPND_R2
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#define R3 IA64_OPND_R3
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#define R3_2 IA64_OPND_R3_2
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#define CPUID_R3 IA64_OPND_CPUID_R3
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#define DBR_R3 IA64_OPND_DBR_R3
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#define DTR_R3 IA64_OPND_DTR_R3
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#define ITR_R3 IA64_OPND_ITR_R3
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#define IBR_R3 IA64_OPND_IBR_R3
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#define MR3 IA64_OPND_MR3
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#define MSR_R3 IA64_OPND_MSR_R3
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#define PKR_R3 IA64_OPND_PKR_R3
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#define PMC_R3 IA64_OPND_PMC_R3
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#define PMD_R3 IA64_OPND_PMD_R3
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#define RR_R3 IA64_OPND_RR_R3
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#define CCNT5 IA64_OPND_CCNT5
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#define CNT2a IA64_OPND_CNT2a
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#define CNT2b IA64_OPND_CNT2b
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#define CNT2c IA64_OPND_CNT2c
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#define CNT5 IA64_OPND_CNT5
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#define CNT6 IA64_OPND_CNT6
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#define CPOS6a IA64_OPND_CPOS6a
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#define CPOS6b IA64_OPND_CPOS6b
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#define CPOS6c IA64_OPND_CPOS6c
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#define IMM1 IA64_OPND_IMM1
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#define IMM14 IA64_OPND_IMM14
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#define IMM17 IA64_OPND_IMM17
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#define IMM22 IA64_OPND_IMM22
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#define IMM44 IA64_OPND_IMM44
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#define SOF IA64_OPND_SOF
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#define SOL IA64_OPND_SOL
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#define SOR IA64_OPND_SOR
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#define IMM8 IA64_OPND_IMM8
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#define IMM8U4 IA64_OPND_IMM8U4
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#define IMM8M1 IA64_OPND_IMM8M1
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#define IMM8M1U4 IA64_OPND_IMM8M1U4
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#define IMM8M1U8 IA64_OPND_IMM8M1U8
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#define IMM9a IA64_OPND_IMM9a
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#define IMM9b IA64_OPND_IMM9b
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#define IMMU2 IA64_OPND_IMMU2
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#define IMMU21 IA64_OPND_IMMU21
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#define IMMU24 IA64_OPND_IMMU24
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#define IMMU62 IA64_OPND_IMMU62
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#define IMMU64 IA64_OPND_IMMU64
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#define IMMU7a IA64_OPND_IMMU7a
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#define IMMU7b IA64_OPND_IMMU7b
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#define IMMU9 IA64_OPND_IMMU9
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#define INC3 IA64_OPND_INC3
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#define LEN4 IA64_OPND_LEN4
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#define LEN6 IA64_OPND_LEN6
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#define MBTYPE4 IA64_OPND_MBTYPE4
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#define MHTYPE8 IA64_OPND_MHTYPE8
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#define POS6 IA64_OPND_POS6
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#define TAG13 IA64_OPND_TAG13
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#define TAG13b IA64_OPND_TAG13b
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#define TGT25 IA64_OPND_TGT25
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#define TGT25b IA64_OPND_TGT25b
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#define TGT25c IA64_OPND_TGT25c
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#define TGT64 IA64_OPND_TGT64
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#endif
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