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6c95a37f64
(ALL_MACHINES): Add cris-dis.lo and cris-opc.lo. (cris-dis.lo, cris-opc.lo): New rules. * Makefile.in: Rebuild. * configure.in (bfd_cris_arch): New target. * configure: Rebuild. * disassemble.c (ARCH_cris): Define. (disassembler): Support ARCH_cris. * cris-dis.c, cris-opc.c: New files. * po/POTFILES.in, po/opcodes.pot: Regenerate.
886 lines
27 KiB
C
886 lines
27 KiB
C
/* cris-opc.c -- Table of opcodes for the CRIS processor.
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Copyright (C) 2000 Free Software Foundation, Inc.
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Contributed by Axis Communications AB, Lund, Sweden.
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Originally written for GAS 1.38.1 by Mikael Asker.
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Reorganized by Hans-Peter Nilsson.
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This file is part of GAS, GDB and the GNU binutils.
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GAS, GDB, and GNU binutils is free software; you can redistribute it
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and/or modify it under the terms of the GNU General Public License as
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published by the Free Software Foundation; either version 2, or (at your
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option) any later version.
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GAS, GDB, and GNU binutils are distributed in the hope that they will be
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useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#include "opcode/cris.h"
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#ifndef NULL
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#define NULL (0)
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#endif
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const struct cris_spec_reg
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cris_spec_regs[] =
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{
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{"p0", 0, 1, 0, NULL},
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{"vr", 1, 1, 0, NULL},
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{"p1", 1, 1, 0, NULL},
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{"p2", 2, 1, cris_ver_warning, NULL},
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{"p3", 3, 1, cris_ver_warning, NULL},
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{"p4", 4, 2, 0, NULL},
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{"ccr", 5, 2, 0, NULL},
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{"p5", 5, 2, 0, NULL},
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{"dcr0",6, 2, cris_ver_v0_3, NULL},
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{"p6", 6, 2, cris_ver_v0_3, NULL},
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{"dcr1/mof", 7, 4, cris_ver_v10p,
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"Register `dcr1/mof' with ambiguous size specified. Guessing 4 bytes"},
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{"dcr1/mof", 7, 2, cris_ver_v0_3,
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"Register `dcr1/mof' with ambiguous size specified. Guessing 2 bytes"},
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{"mof", 7, 4, cris_ver_v10p, NULL},
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{"dcr1",7, 2, cris_ver_v0_3, NULL},
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{"p7", 7, 4, cris_ver_v10p, NULL},
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{"p7", 7, 2, cris_ver_v0_3, NULL},
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{"p8", 8, 4, 0, NULL},
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{"ibr", 9, 4, 0, NULL},
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{"p9", 9, 4, 0, NULL},
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{"irp", 10, 4, 0, NULL},
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{"p10", 10, 4, 0, NULL},
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{"srp", 11, 4, 0, NULL},
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{"p11", 11, 4, 0, NULL},
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/* For disassembly use only. Accept at assembly with a warning. */
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{"bar/dtp0", 12, 4, cris_ver_warning,
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"Ambiguous register `bar/dtp0' specified"},
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{"bar", 12, 4, cris_ver_v8p, NULL},
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{"dtp0",12, 4, cris_ver_v0_3, NULL},
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{"p12", 12, 4, 0, NULL},
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/* For disassembly use only. Accept at assembly with a warning. */
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{"dccr/dtp1",13, 4, cris_ver_warning,
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"Ambiguous register `dccr/dtp1' specified"},
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{"dccr",13, 4, cris_ver_v8p, NULL},
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{"dtp1",13, 4, cris_ver_v0_3, NULL},
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{"p13", 13, 4, 0, NULL},
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{"brp", 14, 4, cris_ver_v3p, NULL},
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{"p14", 14, 4, cris_ver_v3p, NULL},
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{"usp", 15, 4, cris_ver_v10p, NULL},
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{"p15", 15, 4, cris_ver_v10p, NULL},
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{NULL, 0, 0, NULL}
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};
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/* All CRIS opcodes are 16 bits.
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- The match component is a mask saying which bits must match a
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particular opcode in order for an instruction to be an instance
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of that opcode.
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- The args component is a string containing characters symbolically
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matching the operands of an instruction. Used for both assembly
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and disassembly.
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Operand-matching characters:
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B Not really an operand. It causes a "BDAP -size,SP" prefix to be
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output for the PUSH alias-instructions and recognizes a
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push-prefix at disassembly. Must be followed by a R or P letter.
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! Non-match pattern, will not match if there's a prefix insn.
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b Non-matching operand, used for branches with 16-bit
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displacement. Only recognized by the disassembler.
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c 5-bit unsigned immediate in bits <4:0>.
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C 4-bit unsigned immediate in bits <3:0>.
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D General register in bits <15:12> and <3:0>.
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f List of flags in bits <15:12> and <3:0>.
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i 6-bit signed immediate in bits <5:0>.
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I 6-bit unsigned immediate in bits <5:0>.
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M Size modifier (B, W or D) for CLEAR instructions.
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m Size modifier (B, W or D) in bits <5:4>
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o [-128..127] word offset in bits <7:1> and <0>. Used by 8-bit
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branch instructions.
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O [-128..127] offset in bits <7:0>. Also matches a comma and a
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general register after the expression. Used only for the BDAP
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prefix insn.
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P Special register in bits <15:12>.
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p Indicates that the insn is a prefix insn. Must be first
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character.
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R General register in bits <15:12>.
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r General register in bits <3:0>.
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S Source operand in bit <10> and a prefix; a 3-operand prefix
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without side-effect.
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s Source operand in bits <10> and <3:0>, optionally with a
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side-effect prefix.
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x Register-dot-modifier, for example "r5.w" in bits <15:12> and <5:4>.
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y Like 's' but do not allow an integer at assembly.
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z Size modifier (B or W) in bit <4>. */
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/* Please note the order of the opcodes in this table is significant.
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The assembler requires that all instances of the same mnemonic must
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be consecutive. If they aren't, the assembler might not recognize
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them, or may indicate and internal error.
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The disassembler should not normally care about the order of the
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opcodes, but will prefer an earlier alternative if the "match-score"
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(see cris-dis.c) is computed as equal.
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It should not be significant for proper execution that this table is
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in alphabetical order, but please follow that convention for an easy
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overview. */
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const struct cris_opcode
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cris_opcodes[] =
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{
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{"abs", 0x06B0, 0x0940, "r,R", 0, SIZE_NONE, 0,
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cris_abs_op},
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{"add", 0x0600, 0x09c0, "m r,R", 0, SIZE_NONE, 0,
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cris_reg_mode_add_sub_cmp_and_or_move_op},
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{"add", 0x0A00, 0x01c0, "m s,R", 0, SIZE_FIELD, 0,
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cris_none_reg_mode_add_sub_cmp_and_or_move_op},
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{"add", 0x0A00, 0x01c0, "m S,D", 0, SIZE_NONE, 0,
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cris_none_reg_mode_add_sub_cmp_and_or_move_op},
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{"add", 0x0a00, 0x05c0, "m S,R,r", 0, SIZE_NONE, 0,
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cris_three_operand_add_sub_cmp_and_or_op},
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{"addi", 0x0500, 0x0Ac0, "x,r", 0, SIZE_NONE, 0,
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cris_addi_op},
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{"addq", 0x0200, 0x0Dc0, "I,R", 0, SIZE_NONE, 0,
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cris_quick_mode_add_sub_op},
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{"adds", 0x0420, 0x0Bc0, "z r,R", 0, SIZE_NONE, 0,
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cris_reg_mode_add_sub_cmp_and_or_move_op},
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{"adds", 0x0820, 0x03c0, "z s,R", 0, SIZE_FIELD, 0,
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cris_none_reg_mode_add_sub_cmp_and_or_move_op},
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{"adds", 0x0820, 0x03c0, "z S,D", 0, SIZE_NONE, 0,
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cris_none_reg_mode_add_sub_cmp_and_or_move_op},
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{"adds", 0x0820, 0x07c0, "z S,R,r", 0, SIZE_NONE, 0,
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cris_three_operand_add_sub_cmp_and_or_op},
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{"addu", 0x0400, 0x0be0, "z r,R", 0, SIZE_NONE, 0,
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cris_reg_mode_add_sub_cmp_and_or_move_op},
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{"addu", 0x0800, 0x03e0, "z s,R", 0, SIZE_FIELD, 0,
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cris_none_reg_mode_add_sub_cmp_and_or_move_op},
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{"addu", 0x0800, 0x03e0, "z S,D", 0, SIZE_NONE, 0,
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cris_none_reg_mode_add_sub_cmp_and_or_move_op},
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{"addu", 0x0800, 0x07e0, "z S,R,r", 0, SIZE_NONE, 0,
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cris_three_operand_add_sub_cmp_and_or_op},
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{"and", 0x0700, 0x08C0, "m r,R", 0, SIZE_NONE, 0,
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cris_reg_mode_add_sub_cmp_and_or_move_op},
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{"and", 0x0B00, 0x00C0, "m s,R", 0, SIZE_FIELD, 0,
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cris_none_reg_mode_add_sub_cmp_and_or_move_op},
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{"and", 0x0B00, 0x00C0, "m S,D", 0, SIZE_NONE, 0,
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cris_none_reg_mode_add_sub_cmp_and_or_move_op},
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{"and", 0x0B00, 0x04C0, "m S,R,r", 0, SIZE_NONE, 0,
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cris_three_operand_add_sub_cmp_and_or_op},
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{"andq", 0x0300, 0x0CC0, "i,R", 0, SIZE_NONE, 0,
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cris_quick_mode_and_cmp_move_or_op},
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{"asr", 0x0780, 0x0840, "m r,R", 0, SIZE_NONE, 0,
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cris_asr_op},
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{"asrq", 0x03a0, 0x0c40, "c,R", 0, SIZE_NONE, 0,
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cris_asrq_op},
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{"ax", 0x15B0, 0xEA4F, "", 0, SIZE_NONE, 0,
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cris_ax_ei_setf_op},
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/* FIXME: Should use branch #defines. */
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{"b", 0x0dff, 0x0200, "b", 1, SIZE_NONE, 0,
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cris_sixteen_bit_offset_branch_op},
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{"ba",
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BA_QUICK_OPCODE,
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0x0F00+(0xF-CC_A)*0x1000, "o", 1, SIZE_NONE, 0,
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cris_eight_bit_offset_branch_op},
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{"bcc",
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BRANCH_QUICK_OPCODE+CC_CC*0x1000,
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0x0f00+(0xF-CC_CC)*0x1000, "o", 1, SIZE_NONE, 0,
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cris_eight_bit_offset_branch_op},
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{"bcs",
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BRANCH_QUICK_OPCODE+CC_CS*0x1000,
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0x0f00+(0xF-CC_CS)*0x1000, "o", 1, SIZE_NONE, 0,
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cris_eight_bit_offset_branch_op},
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{"bdap",
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BDAP_INDIR_OPCODE, BDAP_INDIR_Z_BITS, "pm s,R", 0, SIZE_FIELD, 0,
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cris_bdap_prefix},
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{"bdap",
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BDAP_QUICK_OPCODE, BDAP_QUICK_Z_BITS, "pO", 0, SIZE_NONE, 0,
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cris_quick_mode_bdap_prefix},
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{"beq",
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BRANCH_QUICK_OPCODE+CC_EQ*0x1000,
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0x0f00+(0xF-CC_EQ)*0x1000, "o", 1, SIZE_NONE, 0,
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cris_eight_bit_offset_branch_op},
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/* This is deliberately put before "bext" to trump it, even though not
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in alphabetical order. */
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{"bwf",
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BRANCH_QUICK_OPCODE+CC_EXT*0x1000,
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0x0f00+(0xF-CC_EXT)*0x1000, "o", 1, SIZE_NONE,
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cris_ver_v10p,
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cris_eight_bit_offset_branch_op},
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{"bext",
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BRANCH_QUICK_OPCODE+CC_EXT*0x1000,
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0x0f00+(0xF-CC_EXT)*0x1000, "o", 1, SIZE_NONE,
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cris_ver_v0_3,
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cris_eight_bit_offset_branch_op},
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{"bge",
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BRANCH_QUICK_OPCODE+CC_GE*0x1000,
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0x0f00+(0xF-CC_GE)*0x1000, "o", 1, SIZE_NONE, 0,
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cris_eight_bit_offset_branch_op},
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{"bgt",
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BRANCH_QUICK_OPCODE+CC_GT*0x1000,
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0x0f00+(0xF-CC_GT)*0x1000, "o", 1, SIZE_NONE, 0,
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cris_eight_bit_offset_branch_op},
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{"bhi",
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BRANCH_QUICK_OPCODE+CC_HI*0x1000,
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0x0f00+(0xF-CC_HI)*0x1000, "o", 1, SIZE_NONE, 0,
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cris_eight_bit_offset_branch_op},
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{"bhs",
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BRANCH_QUICK_OPCODE+CC_HS*0x1000,
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0x0f00+(0xF-CC_HS)*0x1000, "o", 1, SIZE_NONE, 0,
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cris_eight_bit_offset_branch_op},
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{"biap", BIAP_OPCODE, BIAP_Z_BITS, "pm r,R", 0, SIZE_NONE, 0,
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cris_biap_prefix},
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{"ble",
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BRANCH_QUICK_OPCODE+CC_LE*0x1000,
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0x0f00+(0xF-CC_LE)*0x1000, "o", 1, SIZE_NONE, 0,
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cris_eight_bit_offset_branch_op},
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{"blo",
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BRANCH_QUICK_OPCODE+CC_LO*0x1000,
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0x0f00+(0xF-CC_LO)*0x1000, "o", 1, SIZE_NONE, 0,
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cris_eight_bit_offset_branch_op},
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{"bls",
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BRANCH_QUICK_OPCODE+CC_LS*0x1000,
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0x0f00+(0xF-CC_LS)*0x1000, "o", 1, SIZE_NONE, 0,
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cris_eight_bit_offset_branch_op},
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{"blt",
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BRANCH_QUICK_OPCODE+CC_LT*0x1000,
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0x0f00+(0xF-CC_LT)*0x1000, "o", 1, SIZE_NONE, 0,
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cris_eight_bit_offset_branch_op},
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{"bmi",
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BRANCH_QUICK_OPCODE+CC_MI*0x1000,
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0x0f00+(0xF-CC_MI)*0x1000, "o", 1, SIZE_NONE, 0,
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cris_eight_bit_offset_branch_op},
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{"bmod", 0x0ab0, 0x0140, "s,R", 0, SIZE_FIX_32,
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cris_ver_sim,
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cris_not_implemented_op},
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{"bmod", 0x0ab0, 0x0140, "S,D", 0, SIZE_NONE,
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cris_ver_sim,
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cris_not_implemented_op},
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{"bmod", 0x0ab0, 0x0540, "S,R,r", 0, SIZE_NONE,
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cris_ver_sim,
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cris_not_implemented_op},
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{"bne",
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BRANCH_QUICK_OPCODE+CC_NE*0x1000,
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0x0f00+(0xF-CC_NE)*0x1000, "o", 1, SIZE_NONE, 0,
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cris_eight_bit_offset_branch_op},
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{"bound", 0x05c0, 0x0A00, "m r,R", 0, SIZE_NONE, 0,
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cris_two_operand_bound_op},
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{"bound", 0x09c0, 0x0200, "m s,R", 0, SIZE_FIELD, 0,
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cris_two_operand_bound_op},
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{"bound", 0x09c0, 0x0200, "m S,D", 0, SIZE_NONE, 0,
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cris_two_operand_bound_op},
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{"bound", 0x09c0, 0x0600, "m S,R,r", 0, SIZE_NONE, 0,
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cris_three_operand_bound_op},
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{"bpl",
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BRANCH_QUICK_OPCODE+CC_PL*0x1000,
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0x0f00+(0xF-CC_PL)*0x1000, "o", 1, SIZE_NONE, 0,
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cris_eight_bit_offset_branch_op},
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{"break", 0xe930, 0x16c0, "C", 0, SIZE_NONE,
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cris_ver_v3p,
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cris_break_op},
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{"bstore", 0x0af0, 0x0100, "s,R", 0, SIZE_FIX_32,
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cris_ver_warning,
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cris_not_implemented_op},
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{"bstore", 0x0af0, 0x0100, "S,D", 0, SIZE_NONE,
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cris_ver_warning,
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cris_not_implemented_op},
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{"bstore", 0x0af0, 0x0500, "S,R,r", 0, SIZE_NONE,
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cris_ver_warning,
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cris_not_implemented_op},
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{"btst", 0x04F0, 0x0B00, "r,R", 0, SIZE_NONE, 0,
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cris_btst_nop_op},
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{"btstq", 0x0380, 0x0C60, "c,R", 0, SIZE_NONE, 0,
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cris_btst_nop_op},
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{"bvc",
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BRANCH_QUICK_OPCODE+CC_VC*0x1000,
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0x0f00+(0xF-CC_VC)*0x1000, "o", 1, SIZE_NONE, 0,
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cris_eight_bit_offset_branch_op},
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{"bvs",
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BRANCH_QUICK_OPCODE+CC_VS*0x1000,
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0x0f00+(0xF-CC_VS)*0x1000, "o", 1, SIZE_NONE, 0,
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cris_eight_bit_offset_branch_op},
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{"clear", 0x0670, 0x3980, "M r", 0, SIZE_NONE, 0,
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cris_reg_mode_clear_op},
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{"clear", 0x0A70, 0x3180, "M y", 0, SIZE_NONE, 0,
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cris_none_reg_mode_clear_test_op},
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{"clear", 0x0A70, 0x3180, "M S", 0, SIZE_NONE, 0,
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cris_none_reg_mode_clear_test_op},
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{"clearf", 0x05F0, 0x0A00, "f", 0, SIZE_NONE, 0,
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cris_clearf_di_op},
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{"cmp", 0x06C0, 0x0900, "m r,R", 0, SIZE_NONE, 0,
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cris_reg_mode_add_sub_cmp_and_or_move_op},
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{"cmp", 0x0Ac0, 0x0100, "m s,R", 0, SIZE_FIELD, 0,
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cris_none_reg_mode_add_sub_cmp_and_or_move_op},
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{"cmp", 0x0Ac0, 0x0100, "m S,D", 0, SIZE_NONE, 0,
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cris_none_reg_mode_add_sub_cmp_and_or_move_op},
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{"cmpq", 0x02C0, 0x0D00, "i,R", 0, SIZE_NONE, 0,
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cris_quick_mode_and_cmp_move_or_op},
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{"cmps", 0x08e0, 0x0300, "z s,R", 0, SIZE_FIELD, 0,
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cris_none_reg_mode_add_sub_cmp_and_or_move_op},
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{"cmps", 0x08e0, 0x0300, "z S,D", 0, SIZE_NONE, 0,
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cris_none_reg_mode_add_sub_cmp_and_or_move_op},
|
|
|
|
{"cmpu", 0x08c0, 0x0320, "z s,R" , 0, SIZE_FIELD, 0,
|
|
cris_none_reg_mode_add_sub_cmp_and_or_move_op},
|
|
|
|
{"cmpu", 0x08c0, 0x0320, "z S,D", 0, SIZE_NONE, 0,
|
|
cris_none_reg_mode_add_sub_cmp_and_or_move_op},
|
|
|
|
{"di", 0x25F0, 0xDA0F, "", 0, SIZE_NONE, 0,
|
|
cris_clearf_di_op},
|
|
|
|
{"dip", DIP_OPCODE, DIP_Z_BITS, "ps", 0, SIZE_FIX_32, 0,
|
|
cris_dip_prefix},
|
|
|
|
{"div", 0x0980, 0x0640, "m R,r", 0, SIZE_FIELD, 0,
|
|
cris_not_implemented_op},
|
|
|
|
{"dstep", 0x06f0, 0x0900, "r,R", 0, SIZE_NONE, 0,
|
|
cris_dstep_logshift_mstep_neg_not_op},
|
|
|
|
{"ei", 0x25B0, 0xDA4F, "", 0, SIZE_NONE, 0,
|
|
cris_ax_ei_setf_op},
|
|
|
|
{"jbrc", 0x69b0, 0x9640, "r", 0, SIZE_NONE,
|
|
cris_ver_v8p,
|
|
cris_reg_mode_jump_op},
|
|
|
|
{"jbrc", 0x6930, 0x92c0, "s", 0, SIZE_FIX_32,
|
|
cris_ver_v8p,
|
|
cris_none_reg_mode_jump_op},
|
|
|
|
{"jbrc", 0x6930, 0x92c0, "S", 0, SIZE_NONE,
|
|
cris_ver_v8p,
|
|
cris_none_reg_mode_jump_op},
|
|
|
|
{"jir", 0xA9b0, 0x5640, "r", 0, SIZE_NONE, 0,
|
|
cris_reg_mode_jump_op},
|
|
|
|
{"jir", 0xA930, 0x52c0, "s", 0, SIZE_FIX_32, 0,
|
|
cris_none_reg_mode_jump_op},
|
|
|
|
{"jir", 0xA930, 0x52c0, "S", 0, SIZE_NONE, 0,
|
|
cris_none_reg_mode_jump_op},
|
|
|
|
{"jirc", 0x29b0, 0xd640, "r", 0, SIZE_NONE,
|
|
cris_ver_v8p,
|
|
cris_reg_mode_jump_op},
|
|
|
|
{"jirc", 0x2930, 0xd2c0, "s", 0, SIZE_FIX_32,
|
|
cris_ver_v8p,
|
|
cris_none_reg_mode_jump_op},
|
|
|
|
{"jirc", 0x2930, 0xd2c0, "S", 0, SIZE_NONE,
|
|
cris_ver_v8p,
|
|
cris_none_reg_mode_jump_op},
|
|
|
|
{"jsr", 0xB9b0, 0x4640, "r", 0, SIZE_NONE, 0,
|
|
cris_reg_mode_jump_op},
|
|
|
|
{"jsr", 0xB930, 0x42c0, "s", 0, SIZE_FIX_32, 0,
|
|
cris_none_reg_mode_jump_op},
|
|
|
|
{"jsr", 0xB930, 0x42c0, "S", 0, SIZE_NONE, 0,
|
|
cris_none_reg_mode_jump_op},
|
|
|
|
{"jsrc", 0x39b0, 0xc640, "r", 0, SIZE_NONE,
|
|
cris_ver_v8p,
|
|
cris_reg_mode_jump_op},
|
|
|
|
{"jsrc", 0x3930, 0xc2c0, "s", 0, SIZE_FIX_32,
|
|
cris_ver_v8p,
|
|
cris_none_reg_mode_jump_op},
|
|
|
|
{"jsrc", 0x3930, 0xc2c0, "S", 0, SIZE_NONE,
|
|
cris_ver_v8p,
|
|
cris_none_reg_mode_jump_op},
|
|
|
|
{"jump", 0x09b0, 0xF640, "r", 0, SIZE_NONE, 0,
|
|
cris_reg_mode_jump_op},
|
|
|
|
{"jump",
|
|
JUMP_INDIR_OPCODE, JUMP_INDIR_Z_BITS, "s", 0, SIZE_FIX_32, 0,
|
|
cris_none_reg_mode_jump_op},
|
|
|
|
{"jump",
|
|
JUMP_INDIR_OPCODE, JUMP_INDIR_Z_BITS, "S", 0, SIZE_NONE, 0,
|
|
cris_none_reg_mode_jump_op},
|
|
|
|
{"jmpu", 0x8930, 0x72c0, "s", 0, SIZE_FIX_32,
|
|
cris_ver_v10p,
|
|
cris_none_reg_mode_jump_op},
|
|
|
|
{"jmpu", 0x8930, 0x72c0, "S", 0, SIZE_NONE,
|
|
cris_ver_v10p,
|
|
cris_none_reg_mode_jump_op},
|
|
|
|
{"lsl", 0x04C0, 0x0B00, "m r,R", 0, SIZE_NONE, 0,
|
|
cris_dstep_logshift_mstep_neg_not_op},
|
|
|
|
{"lslq", 0x03c0, 0x0C20, "c,R", 0, SIZE_NONE, 0,
|
|
cris_dstep_logshift_mstep_neg_not_op},
|
|
|
|
{"lsr", 0x07C0, 0x0800, "m r,R", 0, SIZE_NONE, 0,
|
|
cris_dstep_logshift_mstep_neg_not_op},
|
|
|
|
{"lsrq", 0x03e0, 0x0C00, "c,R", 0, SIZE_NONE, 0,
|
|
cris_dstep_logshift_mstep_neg_not_op},
|
|
|
|
{"lz", 0x0730, 0x08C0, "r,R", 0, SIZE_NONE,
|
|
cris_ver_v3p,
|
|
cris_not_implemented_op},
|
|
|
|
{"move", 0x0640, 0x0980, "m r,R", 0, SIZE_NONE, 0,
|
|
cris_reg_mode_add_sub_cmp_and_or_move_op},
|
|
|
|
{"move", 0x0630, 0x09c0, "r,P", 0, SIZE_NONE, 0,
|
|
cris_move_to_preg_op},
|
|
|
|
{"move", 0x0670, 0x0980, "P,r", 0, SIZE_NONE, 0,
|
|
cris_reg_mode_move_from_preg_op},
|
|
|
|
{"move", 0x0BC0, 0x0000, "m R,y", 0, SIZE_FIELD, 0,
|
|
cris_none_reg_mode_add_sub_cmp_and_or_move_op},
|
|
|
|
{"move", 0x0BC0, 0x0000, "m D,S", 0, SIZE_NONE, 0,
|
|
cris_none_reg_mode_add_sub_cmp_and_or_move_op},
|
|
|
|
{"move", 0x0A40, 0x0180, "m s,R", 0, SIZE_FIELD, 0,
|
|
cris_none_reg_mode_add_sub_cmp_and_or_move_op},
|
|
|
|
{"move", 0x0A40, 0x0180, "m S,D", 0, SIZE_NONE, 0,
|
|
cris_none_reg_mode_add_sub_cmp_and_or_move_op},
|
|
|
|
{"move", 0x0A30, 0x01c0, "s,P", 0, SIZE_SPEC_REG, 0,
|
|
cris_move_to_preg_op},
|
|
|
|
{"move", 0x0A30, 0x01c0, "S,P", 0, SIZE_NONE, 0,
|
|
cris_move_to_preg_op},
|
|
|
|
{"move", 0x0A70, 0x0180, "P,y", 0, SIZE_SPEC_REG, 0,
|
|
cris_none_reg_mode_move_from_preg_op},
|
|
|
|
{"move", 0x0A70, 0x0180, "P,S", 0, SIZE_NONE, 0,
|
|
cris_none_reg_mode_move_from_preg_op},
|
|
|
|
{"movem", 0x0BF0, 0x0000, "R,y", 0, SIZE_FIX_32, 0,
|
|
cris_move_reg_to_mem_movem_op},
|
|
|
|
{"movem", 0x0BF0, 0x0000, "D,S", 0, SIZE_NONE, 0,
|
|
cris_move_reg_to_mem_movem_op},
|
|
|
|
{"movem", 0x0BB0, 0x0040, "s,R", 0, SIZE_FIX_32, 0,
|
|
cris_move_mem_to_reg_movem_op},
|
|
|
|
{"movem", 0x0BB0, 0x0040, "S,D", 0, SIZE_NONE, 0,
|
|
cris_move_mem_to_reg_movem_op},
|
|
|
|
{"moveq", 0x0240, 0x0D80, "i,R", 0, SIZE_NONE, 0,
|
|
cris_quick_mode_and_cmp_move_or_op},
|
|
|
|
{"movs", 0x0460, 0x0B80, "z r,R", 0, SIZE_NONE, 0,
|
|
cris_reg_mode_add_sub_cmp_and_or_move_op},
|
|
|
|
{"movs", 0x0860, 0x0380, "z s,R", 0, SIZE_FIELD, 0,
|
|
cris_none_reg_mode_add_sub_cmp_and_or_move_op},
|
|
|
|
{"movs", 0x0860, 0x0380, "z S,D", 0, SIZE_NONE, 0,
|
|
cris_none_reg_mode_add_sub_cmp_and_or_move_op},
|
|
|
|
{"movu", 0x0440, 0x0Ba0, "z r,R", 0, SIZE_NONE, 0,
|
|
cris_reg_mode_add_sub_cmp_and_or_move_op},
|
|
|
|
{"movu", 0x0840, 0x03a0, "z s,R", 0, SIZE_FIELD, 0,
|
|
cris_none_reg_mode_add_sub_cmp_and_or_move_op},
|
|
|
|
{"movu", 0x0840, 0x03a0, "z S,D", 0, SIZE_NONE, 0,
|
|
cris_none_reg_mode_add_sub_cmp_and_or_move_op},
|
|
|
|
{"mstep", 0x07f0, 0x0800, "r,R", 0, SIZE_NONE, 0,
|
|
cris_dstep_logshift_mstep_neg_not_op},
|
|
|
|
{"muls", 0x0d00, 0x02c0, "m r,R", 0, SIZE_NONE,
|
|
cris_ver_v10p,
|
|
cris_muls_op},
|
|
|
|
{"mulu", 0x0900, 0x06c0, "m r,R", 0, SIZE_NONE,
|
|
cris_ver_v10p,
|
|
cris_mulu_op},
|
|
|
|
{"neg", 0x0580, 0x0A40, "m r,R", 0, SIZE_NONE, 0,
|
|
cris_dstep_logshift_mstep_neg_not_op},
|
|
|
|
{"nop", NOP_OPCODE, NOP_Z_BITS, "", 0, SIZE_NONE, 0,
|
|
cris_btst_nop_op},
|
|
|
|
{"not", 0x8770, 0x7880, "r", 0, SIZE_NONE, 0,
|
|
cris_dstep_logshift_mstep_neg_not_op},
|
|
|
|
{"or", 0x0740, 0x0880, "m r,R", 0, SIZE_NONE, 0,
|
|
cris_reg_mode_add_sub_cmp_and_or_move_op},
|
|
|
|
{"or", 0x0B40, 0x0080, "m s,R", 0, SIZE_FIELD, 0,
|
|
cris_none_reg_mode_add_sub_cmp_and_or_move_op},
|
|
|
|
{"or", 0x0B40, 0x0080, "m S,D", 0, SIZE_NONE, 0,
|
|
cris_none_reg_mode_add_sub_cmp_and_or_move_op},
|
|
|
|
{"or", 0x0B40, 0x0480, "m S,R,r", 0, SIZE_NONE, 0,
|
|
cris_three_operand_add_sub_cmp_and_or_op},
|
|
|
|
{"orq", 0x0340, 0x0C80, "i,R", 0, SIZE_NONE, 0,
|
|
cris_quick_mode_and_cmp_move_or_op},
|
|
|
|
{"pop", 0x0E6E, 0x0191, "!R", 0, SIZE_NONE, 0,
|
|
cris_none_reg_mode_add_sub_cmp_and_or_move_op},
|
|
|
|
{"pop", 0x0e3e, 0x01c1, "!P", 0, SIZE_NONE, 0,
|
|
cris_none_reg_mode_move_from_preg_op},
|
|
|
|
{"push", 0x0FEE, 0x0011, "BR", 0, SIZE_NONE, 0,
|
|
cris_none_reg_mode_add_sub_cmp_and_or_move_op},
|
|
|
|
{"push", 0x0E7E, 0x0181, "BP", 0, SIZE_NONE, 0,
|
|
cris_move_to_preg_op},
|
|
|
|
{"rbf", 0x3b30, 0xc0c0, "y", 0, SIZE_NONE,
|
|
cris_ver_v10p,
|
|
cris_not_implemented_op},
|
|
|
|
{"rbf", 0x3b30, 0xc0c0, "S", 0, SIZE_NONE,
|
|
cris_ver_v10p,
|
|
cris_not_implemented_op},
|
|
|
|
{"ret", 0xB67F, 0x4980, "", 1, SIZE_NONE, 0,
|
|
cris_reg_mode_move_from_preg_op},
|
|
|
|
{"retb", 0xe67f, 0x1980, "", 1, SIZE_NONE, 0,
|
|
cris_reg_mode_move_from_preg_op},
|
|
|
|
{"reti", 0xA67F, 0x5980, "", 1, SIZE_NONE, 0,
|
|
cris_reg_mode_move_from_preg_op},
|
|
|
|
{"sbfs", 0x3b70, 0xc080, "y", 0, SIZE_NONE,
|
|
cris_ver_v10p,
|
|
cris_not_implemented_op},
|
|
|
|
{"sbfs", 0x3b70, 0xc080, "S", 0, SIZE_NONE,
|
|
cris_ver_v10p,
|
|
cris_not_implemented_op},
|
|
|
|
{"sa",
|
|
0x0530+CC_A*0x1000,
|
|
0x0AC0+(0xf-CC_A)*0x1000, "r", 0, SIZE_NONE, 0,
|
|
cris_scc_op},
|
|
|
|
{"scc",
|
|
0x0530+CC_CC*0x1000,
|
|
0x0AC0+(0xf-CC_CC)*0x1000, "r", 0, SIZE_NONE, 0,
|
|
cris_scc_op},
|
|
|
|
{"scs",
|
|
0x0530+CC_CS*0x1000,
|
|
0x0AC0+(0xf-CC_CS)*0x1000, "r", 0, SIZE_NONE, 0,
|
|
cris_scc_op},
|
|
|
|
{"seq",
|
|
0x0530+CC_EQ*0x1000,
|
|
0x0AC0+(0xf-CC_EQ)*0x1000, "r", 0, SIZE_NONE, 0,
|
|
cris_scc_op},
|
|
|
|
{"setf", 0x05b0, 0x0A40, "f", 0, SIZE_NONE, 0,
|
|
cris_ax_ei_setf_op},
|
|
|
|
/* Need to have "swf" in front of "sext" so it is the one displayed in
|
|
disassembly. */
|
|
{"swf",
|
|
0x0530+CC_EXT*0x1000,
|
|
0x0AC0+(0xf-CC_EXT)*0x1000, "r", 0, SIZE_NONE,
|
|
cris_ver_v10p,
|
|
cris_scc_op},
|
|
|
|
{"sext",
|
|
0x0530+CC_EXT*0x1000,
|
|
0x0AC0+(0xf-CC_EXT)*0x1000, "r", 0, SIZE_NONE,
|
|
cris_ver_v0_3,
|
|
cris_scc_op},
|
|
|
|
{"sge",
|
|
0x0530+CC_GE*0x1000,
|
|
0x0AC0+(0xf-CC_GE)*0x1000, "r", 0, SIZE_NONE, 0,
|
|
cris_scc_op},
|
|
|
|
{"sgt",
|
|
0x0530+CC_GT*0x1000,
|
|
0x0AC0+(0xf-CC_GT)*0x1000, "r", 0, SIZE_NONE, 0,
|
|
cris_scc_op},
|
|
|
|
{"shi",
|
|
0x0530+CC_HI*0x1000,
|
|
0x0AC0+(0xf-CC_HI)*0x1000, "r", 0, SIZE_NONE, 0,
|
|
cris_scc_op},
|
|
|
|
{"shs",
|
|
0x0530+CC_HS*0x1000,
|
|
0x0AC0+(0xf-CC_HS)*0x1000, "r", 0, SIZE_NONE, 0,
|
|
cris_scc_op},
|
|
|
|
{"sle",
|
|
0x0530+CC_LE*0x1000,
|
|
0x0AC0+(0xf-CC_LE)*0x1000, "r", 0, SIZE_NONE, 0,
|
|
cris_scc_op},
|
|
|
|
{"slo",
|
|
0x0530+CC_LO*0x1000,
|
|
0x0AC0+(0xf-CC_LO)*0x1000, "r", 0, SIZE_NONE, 0,
|
|
cris_scc_op},
|
|
|
|
{"sls",
|
|
0x0530+CC_LS*0x1000,
|
|
0x0AC0+(0xf-CC_LS)*0x1000, "r", 0, SIZE_NONE, 0,
|
|
cris_scc_op},
|
|
|
|
{"slt",
|
|
0x0530+CC_LT*0x1000,
|
|
0x0AC0+(0xf-CC_LT)*0x1000, "r", 0, SIZE_NONE, 0,
|
|
cris_scc_op},
|
|
|
|
{"smi",
|
|
0x0530+CC_MI*0x1000,
|
|
0x0AC0+(0xf-CC_MI)*0x1000, "r", 0, SIZE_NONE, 0,
|
|
cris_scc_op},
|
|
|
|
{"sne",
|
|
0x0530+CC_NE*0x1000,
|
|
0x0AC0+(0xf-CC_NE)*0x1000, "r", 0, SIZE_NONE, 0,
|
|
cris_scc_op},
|
|
|
|
{"spl",
|
|
0x0530+CC_PL*0x1000,
|
|
0x0AC0+(0xf-CC_PL)*0x1000, "r", 0, SIZE_NONE, 0,
|
|
cris_scc_op},
|
|
|
|
{"sub", 0x0680, 0x0940, "m r,R", 0, SIZE_NONE, 0,
|
|
cris_reg_mode_add_sub_cmp_and_or_move_op},
|
|
|
|
{"sub", 0x0a80, 0x0140, "m s,R", 0, SIZE_FIELD, 0,
|
|
cris_none_reg_mode_add_sub_cmp_and_or_move_op},
|
|
|
|
{"sub", 0x0a80, 0x0140, "m S,D", 0, SIZE_NONE, 0,
|
|
cris_none_reg_mode_add_sub_cmp_and_or_move_op},
|
|
|
|
{"sub", 0x0a80, 0x0540, "m S,R,r", 0, SIZE_NONE, 0,
|
|
cris_three_operand_add_sub_cmp_and_or_op},
|
|
|
|
{"subq", 0x0280, 0x0d40, "I,R", 0, SIZE_NONE, 0,
|
|
cris_quick_mode_add_sub_op},
|
|
|
|
{"subs", 0x04a0, 0x0b40, "z r,R", 0, SIZE_NONE, 0,
|
|
cris_reg_mode_add_sub_cmp_and_or_move_op},
|
|
|
|
{"subs", 0x08a0, 0x0340, "z s,R", 0, SIZE_FIELD, 0,
|
|
cris_none_reg_mode_add_sub_cmp_and_or_move_op},
|
|
|
|
{"subs", 0x08a0, 0x0340, "z S,D", 0, SIZE_NONE, 0,
|
|
cris_none_reg_mode_add_sub_cmp_and_or_move_op},
|
|
|
|
{"subs", 0x08a0, 0x0740, "z S,R,r", 0, SIZE_NONE, 0,
|
|
cris_three_operand_add_sub_cmp_and_or_op},
|
|
|
|
{"subu", 0x0480, 0x0b60, "z r,R", 0, SIZE_NONE, 0,
|
|
cris_reg_mode_add_sub_cmp_and_or_move_op},
|
|
|
|
{"subu", 0x0880, 0x0360, "z s,R", 0, SIZE_FIELD, 0,
|
|
cris_none_reg_mode_add_sub_cmp_and_or_move_op},
|
|
|
|
{"subu", 0x0880, 0x0360, "z S,D", 0, SIZE_NONE, 0,
|
|
cris_none_reg_mode_add_sub_cmp_and_or_move_op},
|
|
|
|
{"subu", 0x0880, 0x0760, "z S,R,r", 0, SIZE_NONE, 0,
|
|
cris_three_operand_add_sub_cmp_and_or_op},
|
|
|
|
{"svc",
|
|
0x0530+CC_VC*0x1000,
|
|
0x0AC0+(0xf-CC_VC)*0x1000, "r", 0, SIZE_NONE, 0,
|
|
cris_scc_op},
|
|
|
|
{"svs",
|
|
0x0530+CC_VS*0x1000,
|
|
0x0AC0+(0xf-CC_VS)*0x1000, "r", 0, SIZE_NONE, 0,
|
|
cris_scc_op},
|
|
|
|
/* The insn "swapn" is the same as "not" and will be disassembled as
|
|
such, but the swap* family of mnmonics are generally v8-and-higher
|
|
only, so count it in. */
|
|
{"swapn", 0x8770, 0x7880, "r", 0, SIZE_NONE,
|
|
cris_ver_v8p,
|
|
cris_not_implemented_op},
|
|
|
|
{"swapw", 0x4770, 0xb880, "r", 0, SIZE_NONE,
|
|
cris_ver_v8p,
|
|
cris_not_implemented_op},
|
|
|
|
{"swapnw", 0xc770, 0x3880, "r", 0, SIZE_NONE,
|
|
cris_ver_v8p,
|
|
cris_not_implemented_op},
|
|
|
|
{"swapb", 0x2770, 0xd880, "r", 0, SIZE_NONE,
|
|
cris_ver_v8p,
|
|
cris_not_implemented_op},
|
|
|
|
{"swapnb", 0xA770, 0x5880, "r", 0, SIZE_NONE,
|
|
cris_ver_v8p,
|
|
cris_not_implemented_op},
|
|
|
|
{"swapwb", 0x6770, 0x9880, "r", 0, SIZE_NONE,
|
|
cris_ver_v8p,
|
|
cris_not_implemented_op},
|
|
|
|
{"swapnwb", 0xE770, 0x1880, "r", 0, SIZE_NONE,
|
|
cris_ver_v8p,
|
|
cris_not_implemented_op},
|
|
|
|
{"swapr", 0x1770, 0xe880, "r", 0, SIZE_NONE,
|
|
cris_ver_v8p,
|
|
cris_not_implemented_op},
|
|
|
|
{"swapnr", 0x9770, 0x6880, "r", 0, SIZE_NONE,
|
|
cris_ver_v8p,
|
|
cris_not_implemented_op},
|
|
|
|
{"swapwr", 0x5770, 0xa880, "r", 0, SIZE_NONE,
|
|
cris_ver_v8p,
|
|
cris_not_implemented_op},
|
|
|
|
{"swapnwr", 0xd770, 0x2880, "r", 0, SIZE_NONE,
|
|
cris_ver_v8p,
|
|
cris_not_implemented_op},
|
|
|
|
{"swapbr", 0x3770, 0xc880, "r", 0, SIZE_NONE,
|
|
cris_ver_v8p,
|
|
cris_not_implemented_op},
|
|
|
|
{"swapnbr", 0xb770, 0x4880, "r", 0, SIZE_NONE,
|
|
cris_ver_v8p,
|
|
cris_not_implemented_op},
|
|
|
|
{"swapwbr", 0x7770, 0x8880, "r", 0, SIZE_NONE,
|
|
cris_ver_v8p,
|
|
cris_not_implemented_op},
|
|
|
|
{"swapnwbr", 0xf770, 0x0880, "r", 0, SIZE_NONE,
|
|
cris_ver_v8p,
|
|
cris_not_implemented_op},
|
|
|
|
{"test", 0x0640, 0x0980, "m D", 0, SIZE_NONE, 0,
|
|
cris_reg_mode_test_op},
|
|
|
|
{"test", 0x0b80, 0xf040, "m s", 0, SIZE_FIELD, 0,
|
|
cris_none_reg_mode_clear_test_op},
|
|
|
|
{"test", 0x0b80, 0xf040, "m S", 0, SIZE_NONE, 0,
|
|
cris_none_reg_mode_clear_test_op},
|
|
|
|
{"xor", 0x07B0, 0x0840, "r,R", 0, SIZE_NONE, 0,
|
|
cris_xor_op},
|
|
|
|
{NULL, 0, 0, NULL, 0, 0, 0, cris_not_implemented_op}
|
|
};
|
|
|
|
/* Condition-names, indexed by the CC_* numbers as found in cris.h. */
|
|
const char * const
|
|
cris_cc_strings[] =
|
|
{
|
|
"hs",
|
|
"lo",
|
|
"ne",
|
|
"eq",
|
|
"vc",
|
|
"vs",
|
|
"pl",
|
|
"mi",
|
|
"ls",
|
|
"hi",
|
|
"ge",
|
|
"lt",
|
|
"gt",
|
|
"le",
|
|
"a",
|
|
/* In v0, this would be "ext". */
|
|
"wf",
|
|
};
|
|
|
|
|
|
/*
|
|
* Local variables:
|
|
* eval: (c-set-style "gnu")
|
|
* indent-tabs-mode: t
|
|
* End:
|
|
*/
|