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6d8809aa62
* config/tc-sparc.c (md_longopts): Add --no-undeclared-regs option.
(sparc_ip): Warn if %g2 or %g3 register is used and not covered
by .register pseudo-op if -64 and --no-undeclared-regs.
(s_register, sparc_adjust_symtab): New functions.
* config/tc-sparc.h (tc_adjust_symtab, sparc_adjust_symtab):
Declare sparc_adjust_symtab as tc_adjust_symtab.
* doc/c-sparc.texi: Add description of #ignore special literal
for .register pseudo-op.
195 lines
6.5 KiB
Plaintext
195 lines
6.5 KiB
Plaintext
@c Copyright (C) 1991, 1992, 1993, 1994, 1995 Free Software Foundation, Inc.
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@c This is part of the GAS manual.
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@c For copying conditions, see the file as.texinfo.
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@ifset GENERIC
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@page
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@node Sparc-Dependent
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@chapter SPARC Dependent Features
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@end ifset
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@ifclear GENERIC
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@node Machine Dependencies
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@chapter SPARC Dependent Features
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@end ifclear
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@cindex SPARC support
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@menu
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* Sparc-Opts:: Options
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* Sparc-Aligned-Data:: Option to enforce aligned data
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* Sparc-Float:: Floating Point
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* Sparc-Directives:: Sparc Machine Directives
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@end menu
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@node Sparc-Opts
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@section Options
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@cindex options for SPARC
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@cindex SPARC options
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@cindex architectures, SPARC
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@cindex SPARC architectures
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The SPARC chip family includes several successive levels, using the same
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core instruction set, but including a few additional instructions at
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each level. There are exceptions to this however. For details on what
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instructions each variant supports, please see the chip's architecture
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reference manual.
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By default, @code{@value{AS}} assumes the core instruction set (SPARC
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v6), but ``bumps'' the architecture level as needed: it switches to
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successively higher architectures as it encounters instructions that
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only exist in the higher levels.
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If not configured for SPARC v9 (@code{sparc64-*-*}) GAS will not bump
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passed sparclite by default, an option must be passed to enable the
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v9 instructions.
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GAS treats sparclite as being compatible with v8, unless an architecture
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is explicitly requested. SPARC v9 is always incompatible with sparclite.
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@c The order here is the same as the order of enum sparc_opcode_arch_val
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@c to give the user a sense of the order of the "bumping".
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@table @code
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@kindex -Av6
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@kindex Av7
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@kindex -Av8
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@kindex -Asparclet
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@kindex -Asparclite
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@kindex -Av9
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@kindex -Av9a
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@item -Av6 | -Av7 | -Av8 | -Asparclet | -Asparclite
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@itemx -Av8plus | -Av8plusa | -Av9 | -Av9a
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Use one of the @samp{-A} options to select one of the SPARC
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architectures explicitly. If you select an architecture explicitly,
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@code{@value{AS}} reports a fatal error if it encounters an instruction
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or feature requiring an incompatible or higher level.
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@samp{-Av8plus} and @samp{-Av8plusa} select a 32 bit environment.
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@samp{-Av9} and @samp{-Av9a} select a 64 bit environment and are not
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available unless GAS is explicitly configured with 64 bit environment
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support.
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@samp{-Av8plusa} and @samp{-Av9a} enable the SPARC V9 instruction set with
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UltraSPARC extensions.
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@item -xarch=v8plus | -xarch=v8plusa
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For compatibility with the Solaris v9 assembler. These options are
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equivalent to -Av8plus and -Av8plusa, respectively.
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@item -bump
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Warn whenever it is necessary to switch to another level.
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If an architecture level is explicitly requested, GAS will not issue
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warnings until that level is reached, and will then bump the level
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as required (except between incompatible levels).
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@item -32 | -64
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Select the word size, either 32 bits or 64 bits.
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These options are only available with the ELF object file format,
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and require that the necessary BFD support has been included.
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@end table
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@node Sparc-Aligned-Data
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@section Enforcing aligned data
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@cindex data alignment on SPARC
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@cindex SPARC data alignment
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SPARC GAS normally permits data to be misaligned. For example, it
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permits the @code{.long} pseudo-op to be used on a byte boundary.
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However, the native SunOS and Solaris assemblers issue an error when
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they see misaligned data.
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@kindex --enforce-aligned-data
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You can use the @code{--enforce-aligned-data} option to make SPARC GAS
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also issue an error about misaligned data, just as the SunOS and Solaris
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assemblers do.
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The @code{--enforce-aligned-data} option is not the default because gcc
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issues misaligned data pseudo-ops when it initializes certain packed
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data structures (structures defined using the @code{packed} attribute).
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You may have to assemble with GAS in order to initialize packed data
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structures in your own code.
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@ignore
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@c FIXME: (sparc) Fill in "syntax" section!
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@c subsection syntax
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I don't know anything about Sparc syntax. Someone who does
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will have to write this section.
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@end ignore
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@node Sparc-Float
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@section Floating Point
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@cindex floating point, SPARC (@sc{ieee})
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@cindex SPARC floating point (@sc{ieee})
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The Sparc uses @sc{ieee} floating-point numbers.
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@node Sparc-Directives
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@section Sparc Machine Directives
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@cindex SPARC machine directives
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@cindex machine directives, SPARC
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The Sparc version of @code{@value{AS}} supports the following additional
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machine directives:
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@table @code
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@cindex @code{align} directive, SPARC
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@item .align
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This must be followed by the desired alignment in bytes.
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@cindex @code{common} directive, SPARC
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@item .common
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This must be followed by a symbol name, a positive number, and
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@code{"bss"}. This behaves somewhat like @code{.comm}, but the
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syntax is different.
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@cindex @code{half} directive, SPARC
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@item .half
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This is functionally identical to @code{.short}.
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@cindex @code{nword} directive, SPARC
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@item .nword
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On the Sparc, the @code{.nword} directive produces native word sized value,
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ie. if assembling with -32 it is equivalent to @code{.word}, if assembling
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with -64 it is equivalent to @code{.xword}.
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@cindex @code{proc} directive, SPARC
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@item .proc
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This directive is ignored. Any text following it on the same
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line is also ignored.
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@cindex @code{register} directive, SPARC
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@item .register
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This directive declares use of a global application or system register.
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It must be followed by a register name %g2, %g3, %g6 or %g7, comma and
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the symbol name for that register. If symbol name is @code{#scratch},
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it is a scratch register, if it is @code{#ignore}, it just surpresses any
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errors about using undeclared global register, but does not emit any
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information about it into the object file. This can be useful e.g. if you
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save the register before use and restore it after.
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@cindex @code{reserve} directive, SPARC
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@item .reserve
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This must be followed by a symbol name, a positive number, and
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@code{"bss"}. This behaves somewhat like @code{.lcomm}, but the
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syntax is different.
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@cindex @code{seg} directive, SPARC
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@item .seg
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This must be followed by @code{"text"}, @code{"data"}, or
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@code{"data1"}. It behaves like @code{.text}, @code{.data}, or
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@code{.data 1}.
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@cindex @code{skip} directive, SPARC
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@item .skip
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This is functionally identical to the @code{.space} directive.
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@cindex @code{word} directive, SPARC
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@item .word
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On the Sparc, the @code{.word} directive produces 32 bit values,
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instead of the 16 bit values it produces on many other machines.
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@cindex @code{xword} directive, SPARC
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@item .xword
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On the Sparc V9 processor, the @code{.xword} directive produces
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64 bit values.
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@end table
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