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8217716: Remove dead code in PhaseChaitin

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Reviewed-by: thartmann
This commit is contained in:
Claes Redestad 2019-01-24 14:43:56 +01:00
parent a8ae1c1332
commit 689f7accd4
4 changed files with 13 additions and 106 deletions
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1
src/hotspot/share/libadt/vectset.hpp
View File

@ -110,7 +110,6 @@ public:
// Expose internals for speed-critical fast iterators
uint word_size() const { return size; }
uint32_t* EXPOSE() const { return data; }
// Fast inlined "test and set". Replaces the idiom:
// if( visited[idx] ) return;

83
src/hotspot/share/opto/chaitin.cpp
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@ -749,6 +749,17 @@ void PhaseChaitin::gather_lrg_masks( bool after_aggressive ) {
LRG& lrg = lrgs(vreg);
if (vreg) { // No vreg means un-allocable (e.g. memory)
// Check for float-vs-int live range (used in register-pressure
// calculations)
const Type *n_type = n->bottom_type();
if (n_type->is_floatingpoint()) {
lrg._is_float = 1;
}
#ifndef PRODUCT
// Collect bits not used by product code, but which may be useful for
// debugging.
// Collect has-copy bit
if (idx) {
lrg._has_copy = 1;
@ -757,13 +768,6 @@ void PhaseChaitin::gather_lrg_masks( bool after_aggressive ) {
copy_src._has_copy = 1;
}
// Check for float-vs-int live range (used in register-pressure
// calculations)
const Type *n_type = n->bottom_type();
if (n_type->is_floatingpoint()) {
lrg._is_float = 1;
}
// Check for twice prior spilling. Once prior spilling might have
// spilled 'soft', 2nd prior spill should have spilled 'hard' and
// further spilling is unlikely to make progress.
@ -774,7 +778,6 @@ void PhaseChaitin::gather_lrg_masks( bool after_aggressive ) {
}
}
#ifndef PRODUCT
if (trace_spilling() && lrg._def != NULL) {
// collect defs for MultiDef printing
if (lrg._defs == NULL) {
@ -1109,8 +1112,6 @@ void PhaseChaitin::set_was_low() {
#endif
}
#define REGISTER_CONSTRAINED 16
// Compute cost/area ratio, in case we spill. Build the lo-degree list.
void PhaseChaitin::cache_lrg_info( ) {
Compile::TracePhase tp("chaitinCacheLRG", &timers[_t_chaitinCacheLRG]);
@ -1145,56 +1146,6 @@ void PhaseChaitin::cache_lrg_info( ) {
}
}
// Simplify the IFG by removing LRGs of low degree that have NO copies
void PhaseChaitin::Pre_Simplify( ) {
// Warm up the lo-degree no-copy list
int lo_no_copy = 0;
for (uint i = 1; i < _lrg_map.max_lrg_id(); i++) {
if ((lrgs(i).lo_degree() && !lrgs(i)._has_copy) ||
!lrgs(i).alive() ||
lrgs(i)._must_spill) {
lrgs(i)._next = lo_no_copy;
lo_no_copy = i;
}
}
while( lo_no_copy ) {
uint lo = lo_no_copy;
lo_no_copy = lrgs(lo)._next;
int size = lrgs(lo).num_regs();
// Put the simplified guy on the simplified list.
lrgs(lo)._next = _simplified;
_simplified = lo;
// Yank this guy from the IFG.
IndexSet *adj = _ifg->remove_node( lo );
// If any neighbors' degrees fall below their number of
// allowed registers, then put that neighbor on the low degree
// list. Note that 'degree' can only fall and 'numregs' is
// unchanged by this action. Thus the two are equal at most once,
// so LRGs hit the lo-degree worklists at most once.
IndexSetIterator elements(adj);
uint neighbor;
while ((neighbor = elements.next()) != 0) {
LRG *n = &lrgs(neighbor);
assert( _ifg->effective_degree(neighbor) == n->degree(), "" );
// Check for just becoming of-low-degree
if( n->just_lo_degree() && !n->_has_copy ) {
assert(!(*_ifg->_yanked)[neighbor],"Cannot move to lo degree twice");
// Put on lo-degree list
n->_next = lo_no_copy;
lo_no_copy = neighbor;
}
}
} // End of while lo-degree no_copy worklist not empty
// No more lo-degree no-copy live ranges to simplify
}
// Simplify the IFG by removing LRGs of low degree.
void PhaseChaitin::Simplify( ) {
Compile::TracePhase tp("chaitinSimplify", &timers[_t_chaitinSimplify]);
@ -1616,18 +1567,6 @@ uint PhaseChaitin::Select( ) {
return spill_reg-LRG::SPILL_REG; // Return number of spills
}
// Copy 'was_spilled'-edness from the source Node to the dst Node.
void PhaseChaitin::copy_was_spilled( Node *src, Node *dst ) {
if( _spilled_once.test(src->_idx) ) {
_spilled_once.set(dst->_idx);
lrgs(_lrg_map.find(dst))._was_spilled1 = 1;
if( _spilled_twice.test(src->_idx) ) {
_spilled_twice.set(dst->_idx);
lrgs(_lrg_map.find(dst))._was_spilled2 = 1;
}
}
}
// Set the 'spilled_once' or 'spilled_twice' flag on a node.
void PhaseChaitin::set_was_spilled( Node *n ) {
if( _spilled_once.test_set(n->_idx) )

21
src/hotspot/share/opto/chaitin.hpp
View File

@ -35,12 +35,11 @@
#include "opto/regmask.hpp"
#include "opto/machnode.hpp"
class LoopTree;
class Matcher;
class PhaseCFG;
class PhaseLive;
class PhaseRegAlloc;
class PhaseChaitin;
class PhaseChaitin;
#define OPTO_DEBUG_SPLIT_FREQ BLOCK_FREQUENCY(0.001)
#define OPTO_LRG_HIGH_FREQ BLOCK_FREQUENCY(0.25)
@ -136,7 +135,6 @@ public:
void Insert( OptoReg::Name reg ) { _mask.Insert(reg); debug_only(_msize_valid=0;) }
void Remove( OptoReg::Name reg ) { _mask.Remove(reg); debug_only(_msize_valid=0;) }
void clear_to_pairs() { _mask.clear_to_pairs(); debug_only(_msize_valid=0;) }
void clear_to_sets() { _mask.clear_to_sets(_num_regs); debug_only(_msize_valid=0;) }
// Number of registers this live range uses when it colors
@ -237,9 +235,6 @@ public:
// Add edge between a and b. Returns true if actually addded.
int add_edge( uint a, uint b );
// Add edge between a and everything in the vector
void add_vector( uint a, IndexSet *vec );
// Test for edge existance
int test_edge( uint a, uint b ) const;
@ -401,7 +396,6 @@ class PhaseChaitin : public PhaseRegAlloc {
PhaseLive *_live; // Liveness, used in the interference graph
PhaseIFG *_ifg; // Interference graph (for original chunk)
Node_List **_lrg_nodes; // Array of node; lists for lrgs which spill
VectorSet _spilled_once; // Nodes that have been spilled
VectorSet _spilled_twice; // Nodes that have been spilled twice
@ -496,8 +490,7 @@ private:
void de_ssa();
// Add edge between reg and everything in the vector.
// Same as _ifg->add_vector(reg,live) EXCEPT use the RegMask
// information to trim the set of interferences. Return the
// Use the RegMask information to trim the set of interferences. Return the
// count of edges added.
void interfere_with_live(uint lid, IndexSet* liveout);
#ifdef ASSERT
@ -666,17 +659,9 @@ private:
// coalescing, it should Simplify. This call sets the was-lo-degree bit.
void set_was_low();
// Split live-ranges that must spill due to register conflicts (as opposed
// to capacity spills). Typically these are things def'd in a register
// and used on the stack or vice-versa.
void pre_spill();
// Init LRG caching of degree, numregs. Init lo_degree list.
void cache_lrg_info( );
// Simplify the IFG by removing LRGs of low degree with no copies
void Pre_Simplify();
// Simplify the IFG by removing LRGs of low degree
void Simplify();
@ -692,8 +677,6 @@ private:
// Return new number of live ranges
uint Split(uint maxlrg, ResourceArea* split_arena);
// Copy 'was_spilled'-edness from one Node to another.
void copy_was_spilled( Node *src, Node *dst );
// Set the 'spilled_once' or 'spilled_twice' flag on a node.
void set_was_spilled( Node *n );

14
src/hotspot/share/opto/ifg.cpp
View File

@ -67,20 +67,6 @@ int PhaseIFG::add_edge( uint a, uint b ) {
return _adjs[a].insert( b );
}
// Add an edge between 'a' and everything in the vector.
void PhaseIFG::add_vector( uint a, IndexSet *vec ) {
// IFG is triangular, so do the inserts where 'a' < 'b'.
assert( !_is_square, "only on triangular" );
IndexSet *adjs_a = &_adjs[a];
if( !vec->count() ) return;
IndexSetIterator elements(vec);
uint neighbor;
while ((neighbor = elements.next()) != 0) {
add_edge( a, neighbor );
}
}
// Is there an edge between a and b?
int PhaseIFG::test_edge( uint a, uint b ) const {
// Sort a and b, so that a is larger