dolphin-emu/archived-gcdsp-ida
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Pull in CMPAR disassembly fix from Dolphin.

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The two operand register selection bits were swapped for that instruction. For
example, "CMPAR AC1, AX0.H" would be disassembled as "CMPAR AC0, AX1.H",
leading to pain and confusion.
This commit is contained in:
Pierre Bourdon
2014-12-13 04:27:07 +01:00
parent 9e0a198138
commit 0b90941d4d
1 changed files with 1 additions and 1 deletions
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2
gcdsp_generated.py
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@@ -199,7 +199,7 @@ opcodes = [
["MULXMV",0xa600,0xe600,1,3,[[OpType.REGM18,1,0,11,0x1000],[OpType.REGM19,1,0,10,0x0800],[OpType.ACC,1,0,8,0x0100]],True,False],
["TST",0xb100,0xf700,1,1,[[OpType.ACC,1,0,11,0x0800]],True,False],
["MULC",0xc000,0xe700,1,2,[[OpType.ACCM,1,0,12,0x1000],[OpType.REG1A,1,0,11,0x0800]],True,False],
["CMPAR",0xc100,0xe700,1,2,[[OpType.ACC,1,0,12,0x1000],[OpType.REG1A,1,0,11,0x0800]],True,False],
["CMPAR",0xc100,0xe700,1,2,[[OpType.ACC,1,0,11,0x0800],[OpType.REG1A,1,0,12,0x1000]],True,False],
["MULCMVZ",0xc200,0xe600,1,3,[[OpType.ACCM,1,0,12,0x1000],[OpType.REG1A,1,0,11,0x0800],[OpType.ACC,1,0,8,0x0100]],True,False],
["MULCAC",0xc400,0xe600,1,3,[[OpType.ACCM,1,0,12,0x1000],[OpType.REG1A,1,0,11,0x0800],[OpType.ACC,1,0,8,0x0100]],True,False],
["MULCMV",0xc600,0xe600,1,3,[[OpType.ACCM,1,0,12,0x1000],[OpType.REG1A,1,0,11,0x0800],[OpType.ACC,1,0,8,0x0100]],True,False],