Replace all bitfields which were only declared with "(un)signed" with their actual types. Let me know if I missed any. It would also be a good idea to test this commit in both x64 and x86.

git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@6232 8ced0084-cf51-0410-be5f-012b33b47a6e

Source/Core/AudioCommon/Src/AudioCommon.h

@@ -36,21 +36,21 @@ union UDSPControl
 	u16 Hex;
 	struct
 	{
-		unsigned DSPReset       : 1; // Write 1 to reset and waits for 0
-		unsigned DSPAssertInt   : 1;
-		unsigned DSPHalt        : 1;
+		u16 DSPReset       : 1; // Write 1 to reset and waits for 0
+		u16 DSPAssertInt   : 1;
+		u16 DSPHalt        : 1;
 
-		unsigned AI             : 1;
-		unsigned AI_mask        : 1;
-		unsigned ARAM           : 1;
-		unsigned ARAM_mask      : 1;
-		unsigned DSP            : 1;
-		unsigned DSP_mask       : 1;
+		u16 AI             : 1;
+		u16 AI_mask        : 1;
+		u16 ARAM           : 1;
+		u16 ARAM_mask      : 1;
+		u16 DSP            : 1;
+		u16 DSP_mask       : 1;
 
-		unsigned ARAM_DMAState  : 1; // DSPGetDMAStatus() uses this flag
-		unsigned DSPInitCode    : 1;
-		unsigned DSPInit        : 1; // DSPInit() writes to this flag
-		unsigned pad            : 4;
+		u16 ARAM_DMAState  : 1; // DSPGetDMAStatus() uses this flag
+		u16 DSPInitCode    : 1;
+		u16 DSPInit        : 1; // DSPInit() writes to this flag
+		u16 pad            : 4;
 	};
 	UDSPControl(u16 _Hex = 0) : Hex(_Hex) {}
 };

Source/Core/Core/Src/HW/AudioInterface.cpp

@@ -53,15 +53,15 @@ union AICR
 	AICR(u32 _hex) { hex = _hex;}
 	struct 
 	{
-		unsigned PSTAT		: 1;  // sample counter/playback enable
-		unsigned AIFR		: 1;  // AI Frequency (0=32khz 1=48khz)
-		unsigned AIINTMSK	: 1;  // 0=interrupt masked 1=interrupt enabled
-		unsigned AIINT		: 1;  // audio interrupt status
-		unsigned AIINTVLD	: 1;  // This bit controls whether AIINT is affected by the AIIT register 
+		u32 PSTAT		: 1;  // sample counter/playback enable
+		u32 AIFR		: 1;  // AI Frequency (0=32khz 1=48khz)
+		u32 AIINTMSK	: 1;  // 0=interrupt masked 1=interrupt enabled
+		u32 AIINT		: 1;  // audio interrupt status
+		u32 AIINTVLD	: 1;  // This bit controls whether AIINT is affected by the AIIT register 
                                   // matching AISLRCNT. Once set, AIINT will hold
-		unsigned SCRESET	: 1;  // write to reset counter
-        unsigned DACFR  	: 1;  // DAC Frequency (0=48khz 1=32khz)
-		unsigned			:25;
+		u32 SCRESET		: 1;  // write to reset counter
+        u32 DACFR		: 1;  // DAC Frequency (0=48khz 1=32khz)
+		u32				:25;
 	};
 	u32 hex;
 };
@@ -71,9 +71,9 @@ union AIVR
 {
 	struct
 	{
-		unsigned leftVolume		:  8;
-		unsigned rightVolume	:  8;
-		unsigned				: 16;
+		u32 leftVolume		:  8;
+		u32 rightVolume		:  8;
+		u32					: 16;
 	};
 	u32 hex;
 };

Source/Core/Core/Src/HW/EXI_Channel.h

@@ -62,17 +62,17 @@ private:
 		//	Channels 0, 1, 2
 		//		Channels 0, 1 only
 		//			Channel 0 only
-			unsigned EXIINTMASK		: 1;
-			unsigned EXIINT			: 1;
-			unsigned TCINTMASK		: 1;
-			unsigned TCINT			: 1;
-			unsigned CLK			: 3;
-			unsigned CHIP_SELECT	: 3; // CS1 and CS2 are Channel 0 only
-				unsigned EXTINTMASK	: 1;
-				unsigned EXTINT		: 1;
-				unsigned EXT		: 1; // External Insertion Status (1: External EXI device present)
-					unsigned ROMDIS	: 1; // ROM Disable
-			unsigned				:18;
+			u32 EXIINTMASK		: 1;
+			u32 EXIINT			: 1;
+			u32 TCINTMASK		: 1;
+			u32 TCINT			: 1;
+			u32 CLK				: 3;
+			u32 CHIP_SELECT		: 3; // CS1 and CS2 are Channel 0 only
+				u32 EXTINTMASK	: 1;
+				u32 EXTINT		: 1;
+				u32 EXT			: 1; // External Insertion Status (1: External EXI device present)
+					u32 ROMDIS	: 1; // ROM Disable
+			u32					:18;
 		};
 		UEXI_STATUS() {Hex = 0;}
 		UEXI_STATUS(u32 _hex) {Hex = _hex;}
@@ -84,11 +84,11 @@ private:
 		u32 Hex;
 		struct
 		{
-			unsigned TSTART			: 1;
-			unsigned DMA			: 1;
-			unsigned RW				: 2;
-			unsigned TLEN			: 2;
-			unsigned				:26;
+			u32 TSTART		: 1;
+			u32 DMA			: 1;
+			u32 RW			: 2;
+			u32 TLEN		: 2;
+			u32				:26;
 		};
 	};
 

Source/Core/Core/Src/HW/EXI_DeviceMic.h

@@ -53,13 +53,13 @@ private:
 		u8 U8[2];
 		struct
 		{
-			unsigned			:8; // Unknown
-			unsigned button		:1; // 1: Button Pressed
-			unsigned unk1		:1; // 1 ? Overflow?
-			unsigned unk2		:1; // Unknown related to 0 and 15 values It seems
-			unsigned sRate		:2; // Sample Rate, 00-11025, 01-22050, 10-44100, 11-??
-			unsigned pLength	:2; // Period Length, 00-32, 01-64, 10-128, 11-???
-			unsigned sampling	:1; // If We Are Sampling or Not
+			u16				:8; // Unknown
+			u16 button		:1; // 1: Button Pressed
+			u16 unk1		:1; // 1 ? Overflow?
+			u16 unk2		:1; // Unknown related to 0 and 15 values It seems
+			u16 sRate		:2; // Sample Rate, 00-11025, 01-22050, 10-44100, 11-??
+			u16 pLength		:2; // Period Length, 00-32, 01-64, 10-128, 11-???
+			u16 sampling	:1; // If We Are Sampling or Not
 		};
 	};
 	int Index;

Source/Core/Core/Src/HW/MemmapFunctions.cpp

@@ -562,14 +562,15 @@ void WriteUnchecked_U32(const u32 _iValue, const u32 _Address)
 #define PTE2_WIMG(v) (((v)>>3)&0xf)
 #define PTE2_PP(v)   ((v)&3)
 
+// Hey! these duplicate a structure in Gekko.h
 union UPTE1
 {
 	struct 
 	{
-		unsigned API    : 6;
-		unsigned H      : 1;
-		unsigned VSID   : 24;
-		unsigned V      : 1;        
+		u32 API    : 6;
+		u32 H      : 1;
+		u32 VSID   : 24;
+		u32 V      : 1;        
 	};
 	u32 Hex;
 };
@@ -578,13 +579,13 @@ union UPTE2
 {
 	struct 
 	{
-		unsigned PP     : 2;
-		unsigned        : 1;
-		unsigned WIMG   : 4;
-		unsigned C      : 1;
-		unsigned R      : 1;
-		unsigned        : 3;
-		unsigned RPN    : 20;
+		u32 PP     : 2;
+		u32        : 1;
+		u32 WIMG   : 4;
+		u32 C      : 1;
+		u32 R      : 1;
+		u32        : 3;
+		u32 RPN    : 20;
 	};
 	u32 Hex;
 };

Source/Core/Core/Src/HW/SI_DeviceGCController.h

@@ -63,10 +63,10 @@ private:
 		u32 Hex;
 		struct  
 		{
-			unsigned Parameter1	:	8;
-			unsigned Parameter2	:	8;
-			unsigned Command	:	8;
-			unsigned			:	8;
+			u32 Parameter1	:	8;
+			u32 Parameter2	:	8;
+			u32 Command		:	8;
+			u32				:	8;
 		};
 		UCommand()				{Hex = 0;}
 		UCommand(u32 _iValue)	{Hex = _iValue;}		

Source/Core/Core/Src/HW/VideoInterface.h

@@ -114,9 +114,9 @@ union UVIVerticalTimingRegister
 	u16 Hex;
 	struct
 	{
-		unsigned EQU	:	 4; // Equalization pulse in half lines
-		unsigned ACV	:	10; // Active video in lines per field (seems always zero)
-		unsigned		:	 2;
+		u16 EQU	:	 4; // Equalization pulse in half lines
+		u16 ACV	:	10; // Active video in lines per field (seems always zero)
+		u16		:	 2;
 	};
 	UVIVerticalTimingRegister(u16 _hex) { Hex = _hex;}
 	UVIVerticalTimingRegister() { Hex = 0;}
@@ -127,14 +127,14 @@ union UVIDisplayControlRegister
 	u16 Hex;
 	struct
 	{
-		unsigned ENB	:	1; // Enables video timing generation and data request
-		unsigned RST	:	1; // Clears all data requests and puts VI into its idle state
-		unsigned NIN	:	1; // 0: Interlaced, 1: Non-Interlaced: top field drawn at field rate and bottom field is not displayed
-		unsigned DLR	:	1; // Selects 3D Display Mode
-		unsigned LE0	:	2; // Display Latch; 0: Off, 1: On for 1 field, 2: On for 2 fields, 3: Always on
-		unsigned LE1	:	2;
-		unsigned FMT	:	2; // 0: NTSC, 1: PAL, 2: MPAL, 3: Debug
-		unsigned		:	6;
+		u16 ENB	:	1; // Enables video timing generation and data request
+		u16 RST	:	1; // Clears all data requests and puts VI into its idle state
+		u16 NIN	:	1; // 0: Interlaced, 1: Non-Interlaced: top field drawn at field rate and bottom field is not displayed
+		u16 DLR	:	1; // Selects 3D Display Mode
+		u16 LE0	:	2; // Display Latch; 0: Off, 1: On for 1 field, 2: On for 2 fields, 3: Always on
+		u16 LE1	:	2;
+		u16 FMT	:	2; // 0: NTSC, 1: PAL, 2: MPAL, 3: Debug
+		u16		:	6;
 	};
 	UVIDisplayControlRegister(u16 _hex) { Hex = _hex;}
 	UVIDisplayControlRegister() { Hex = 0;}
@@ -146,12 +146,12 @@ union UVIHorizontalTiming0
 	struct { u16 Lo, Hi; };
 	struct  
 	{		
-		unsigned HLW		:	9; // Halfline Width (W*16 = Width (720))
-		unsigned			:	7;
-		unsigned HCE		:	7; // Horizontal Sync Start to Color Burst End
-		unsigned			:	1;
-		unsigned HCS		:	7; // Horizontal Sync Start to Color Burst Start
-		unsigned			:	1;
+		u32 HLW		:	9; // Halfline Width (W*16 = Width (720))
+		u32			:	7;
+		u32 HCE		:	7; // Horizontal Sync Start to Color Burst End
+		u32			:	1;
+		u32 HCS		:	7; // Horizontal Sync Start to Color Burst Start
+		u32			:	1;
 	};
 };
 
@@ -161,11 +161,11 @@ union UVIHorizontalTiming1
 	struct { u16 Lo, Hi; };
 	struct  
 	{		
-		unsigned HSY		:	 7; // Horizontal Sync Width
-		unsigned HBE640		:	 9; // Horizontal Sync Start to horizontal blank end
-		unsigned			:	 1;
-		unsigned HBS640		:	 9; // Half line to horizontal blanking start
-		unsigned			:	 6;
+		u32 HSY		:	 7; // Horizontal Sync Width
+		u32 HBE640	:	 9; // Horizontal Sync Start to horizontal blank end
+		u32			:	 1;
+		u32 HBS640	:	 9; // Half line to horizontal blanking start
+		u32			:	 6;
 	};
 };
 
@@ -176,10 +176,10 @@ union UVIVBlankTimingRegister
 	struct { u16 Lo, Hi; };
 	struct  
 	{		
-		unsigned PRB		:	10; // Pre-blanking in half lines
-		unsigned			:	 6;
-		unsigned PSB		:	10; // Post blanking in half lines
-		unsigned			:	 6;
+		u32 PRB		:	10; // Pre-blanking in half lines
+		u32			:	 6;
+		u32 PSB		:	10; // Post blanking in half lines
+		u32			:	 6;
 	};
 };
 
@@ -190,10 +190,10 @@ union UVIBurstBlankingRegister
 	struct { u16 Lo, Hi; };
 	struct  
 	{		
-		unsigned BS0		:	 5; // Field x start to burst blanking start in halflines
-		unsigned BE0		:	11; // Field x start to burst blanking end in halflines
-		unsigned BS2		:	 5; // Field x+2 start to burst blanking start in halflines
-		unsigned BE2		:	11; // Field x+2 start to burst blanking end in halflines
+		u32 BS0		:	 5; // Field x start to burst blanking start in halflines
+		u32 BE0		:	11; // Field x start to burst blanking end in halflines
+		u32 BS2		:	 5; // Field x+2 start to burst blanking start in halflines
+		u32 BE2		:	11; // Field x+2 start to burst blanking end in halflines
 	};
 };
 
@@ -204,11 +204,11 @@ union UVIFBInfoRegister
 	struct  
 	{
 		// TODO: mask out lower 9bits/align to 9bits???
-		unsigned FBB		:	24; // Base address of the framebuffer in external mem
+		u32 FBB		:	24; // Base address of the framebuffer in external mem
 		// POFF only seems to exist in the top reg. XOFF, unknown.
-		unsigned XOFF		:	 4; // Horizontal Offset of the left-most pixel within the first word of the fetched picture
-		unsigned POFF		:	 1; // Page offest: 1: fb address is (address>>5)
-		unsigned CLRPOFF	:	 3; // ? setting bit 31 clears POFF
+		u32 XOFF	:	 4; // Horizontal Offset of the left-most pixel within the first word of the fetched picture
+		u32 POFF	:	 1; // Page offest: 1: fb address is (address>>5)
+		u32 CLRPOFF	:	 3; // ? setting bit 31 clears POFF
 	};
 };
 
@@ -219,13 +219,13 @@ union UVIInterruptRegister
 	struct { u16 Lo, Hi; };
 	struct  
 	{		
-		unsigned HCT		:	11; // Horizontal Position
-		unsigned			:	 5;
-		unsigned VCT		:	11; // Vertical Position
-		unsigned			:	 1;
-		unsigned IR_MASK	:	 1; // Interrupt Mask Bit
-		unsigned			:	 2;
-		unsigned IR_INT		:	 1; // Interrupt Status (1=Active, 0=Clear)
+		u32 HCT		:	11; // Horizontal Position
+		u32			:	 5;
+		u32 VCT		:	11; // Vertical Position
+		u32			:	 1;
+		u32 IR_MASK	:	 1; // Interrupt Mask Bit
+		u32			:	 2;
+		u32 IR_INT	:	 1; // Interrupt Status (1=Active, 0=Clear)
 	};
 };
 
@@ -235,11 +235,11 @@ union UVILatchRegister
 	struct { u16 Lo, Hi; };
 	struct  
 	{		
-		unsigned HCT		:	11; // Horizontal Count
-		unsigned			:	 5;
-		unsigned VCT		:	11; // Vertical Count
-		unsigned			:	 4;
-		unsigned TRG		:	 1; // Trigger Flag
+		u32 HCT		:	11; // Horizontal Count
+		u32			:	 5;
+		u32 VCT		:	11; // Vertical Count
+		u32			:	 4;
+		u32 TRG		:	 1; // Trigger Flag
 	};
 };
 
@@ -248,8 +248,8 @@ union UVIHorizontalStepping
 	u16 Hex;
 	struct
 	{
-		unsigned FbSteps	:	 8;
-		unsigned FieldSteps	:	 8;
+		u16 FbSteps		:	 8;
+		u16 FieldSteps	:	 8;
 	};
 };
 
@@ -258,10 +258,10 @@ union UVIHorizontalScaling
 	u16 Hex;
 	struct
 	{
-		unsigned STP		:	9; // Horizontal stepping size (U1.8 Scaler Value) (0x160 Works for 320)
-		unsigned			:	3;
-		unsigned HS_EN		:	1; // Enable Horizontal Scaling
-		unsigned			:	3;
+		u16 STP		:	9; // Horizontal stepping size (U1.8 Scaler Value) (0x160 Works for 320)
+		u16			:	3;
+		u16 HS_EN	:	1; // Enable Horizontal Scaling
+		u16			:	3;
 	};
 	UVIHorizontalScaling(u16 _hex) { Hex = _hex;}
 	UVIHorizontalScaling() { Hex = 0;}
@@ -274,10 +274,10 @@ union UVIFilterCoefTable3
 	struct { u16 Lo, Hi; };
 	struct
 	{
-		unsigned Tap0		:	10;
-		unsigned Tap1		:	10;
-		unsigned Tap2		:	10;
-		unsigned			:	 2;
+		u32 Tap0	:	10;
+		u32 Tap1	:	10;
+		u32 Tap2	:	10;
+		u32			:	 2;
 	};
 };
 
@@ -288,10 +288,10 @@ union UVIFilterCoefTable4
 	struct { u16 Lo, Hi; };
 	struct
 	{
-		unsigned Tap0		:	 8;
-		unsigned Tap1		:	 8;
-		unsigned Tap2		:	 8;
-		unsigned Tap3		:	 8;
+		u32 Tap0	:	 8;
+		u32 Tap1	:	 8;
+		u32 Tap2	:	 8;
+		u32 Tap3	:	 8;
 	};
 };
 
@@ -308,10 +308,10 @@ union UVIBorderBlankRegister
 	struct { u16 Lo, Hi; };
 	struct
 	{
-		unsigned HBE656		:	10; // Border Horizontal Blank End
-		unsigned			:	11;
-		unsigned HBS656		:	10; // Border Horizontal Blank start
-		unsigned BRDR_EN	:	 1; // Border Enable
+		u32 HBE656	:	10; // Border Horizontal Blank End
+		u32			:	11;
+		u32 HBS656	:	10; // Border Horizontal Blank start
+		u32 BRDR_EN	:	 1; // Border Enable
 	};
 };
 

Source/Core/Core/Src/PowerPC/Gekko.h

@@ -35,233 +35,233 @@ union UGeckoInstruction
 
 	struct
 	{
-		unsigned Rc		:	1;
-		unsigned SUBOP10:	10;
-		unsigned RB		:	5;
-		unsigned RA		:	5;
-		unsigned RD		:	5;
-		unsigned OPCD	:	6;
+		u32 Rc		:	1;
+		u32 SUBOP10	:	10;
+		u32 RB		:	5;
+		u32 RA		:	5;
+		u32 RD		:	5;
+		u32 OPCD	:	6;
 	}; // changed
 	struct
 	{
 		signed SIMM_16	:	16;
-		unsigned 		:	5;
-		unsigned TO		:	5;
-		unsigned OPCD_2	:	6;
+		u32 			:	5;
+		u32 TO			:	5;
+		u32 OPCD_2		:	6;
 	};
 	struct
 	{
-		unsigned Rc_2	:	1;
-		unsigned		:	10;
-		unsigned 		:	5;
-		unsigned 		:	5;
-		unsigned RS		:	5;
-		unsigned OPCD_3	:	6;
+		u32 Rc_2	:	1;
+		u32			:	10;
+		u32 		:	5;
+		u32 		:	5;
+		u32 RS		:	5;
+		u32 OPCD_3	:	6;
 	};
 	struct
 	{
-		unsigned UIMM	:	16;
-		unsigned 		:	5;
-		unsigned 		:	5;
-		unsigned OPCD_4	:	6;
+		u32 UIMM	:	16;
+		u32 		:	5;
+		u32 		:	5;
+		u32 OPCD_4	:	6;
 	};
 	struct
 	{
-		unsigned LK		:	1;
-		unsigned AA		:	1;
-		unsigned LI		:	24;
-		unsigned OPCD_5	:	6;
+		u32 LK		:	1;
+		u32 AA		:	1;
+		u32 LI		:	24;
+		u32 OPCD_5	:	6;
 	};
 	struct
 	{     
-		unsigned LK_2	:	1;
-		unsigned AA_2	:	1;
-		unsigned BD		:	14;
-		unsigned BI		:	5;
-		unsigned BO		:	5;
-		unsigned OPCD_6	:	6;
+		u32 LK_2	:	1;
+		u32 AA_2	:	1;
+		u32 BD		:	14;
+		u32 BI		:	5;
+		u32 BO		:	5;
+		u32 OPCD_6	:	6;
 	};
 	struct
 	{
-		unsigned LK_3	:	1;
-		unsigned		:	10;
-		unsigned		:	5;
-		unsigned BI_2	:	5;
-		unsigned BO_2	:	5;
-		unsigned OPCD_7	:	6;
+		u32 LK_3	:	1;
+		u32			:	10;
+		u32			:	5;
+		u32 BI_2	:	5;
+		u32 BO_2	:	5;
+		u32 OPCD_7	:	6;
 	};
 	struct
 	{
-		unsigned		:	11;
-		unsigned RB_2	:	5;
-		unsigned RA_2	:	5;
-		unsigned L		:	1;
-		unsigned 		:	1;
-		unsigned CRFD	:	3;
-		unsigned OPCD_8	:	6;
+		u32			:	11;
+		u32 RB_2	:	5;
+		u32 RA_2	:	5;
+		u32 L		:	1;
+		u32 		:	1;
+		u32 CRFD	:	3;
+		u32 OPCD_8	:	6;
 	};
 	struct
 	{
 		signed  SIMM_16_2	:	16;
-		unsigned RA_3	:	5;
-		unsigned L_2	:	1;
-		unsigned		:	1;
-		unsigned CRFD_2	:	3;
-		unsigned OPCD_9	:	6;
+		u32 RA_3	:	5;
+		u32 L_2		:	1;
+		u32			:	1;
+		u32 CRFD_2	:	3;
+		u32 OPCD_9	:	6;
 	};
 	struct
 	{     
-		unsigned UIMM_2	:	16;
-		unsigned RA_4	:	5;
-		unsigned L_3	:	1;
-		unsigned dummy2	:	1;
-		unsigned CRFD_3	:	3;
-		unsigned OPCD_A	:	6;
+		u32 UIMM_2	:	16;
+		u32 RA_4	:	5;
+		u32 L_3		:	1;
+		u32 dummy2	:	1;
+		u32 CRFD_3	:	3;
+		u32 OPCD_A	:	6;
 	};
 	struct
 	{
-		unsigned		:	1;
-		unsigned SUBOP10_2:	10;
-		unsigned RB_5	:	5;
-		unsigned RA_5	:	5;
-		unsigned L_4	:	1;
-		unsigned dummy3	:	1;
-		unsigned CRFD_4	:	3;
-		unsigned OPCD_B	:	6;
+		u32			:	1;
+		u32 SUBOP10_2:	10;
+		u32 RB_5	:	5;
+		u32 RA_5	:	5;
+		u32 L_4		:	1;
+		u32 dummy3	:	1;
+		u32 CRFD_4	:	3;
+		u32 OPCD_B	:	6;
 	};
 	struct
 	{
-		unsigned		:	16;
-		unsigned SR		:	4;
-		unsigned 		:	1;
-		unsigned RS_2	:	5;
-		unsigned OPCD_C	:	6;
+		u32			:	16;
+		u32 SR		:	4;
+		u32 		:	1;
+		u32 RS_2	:	5;
+		u32 OPCD_C	:	6;
 	};
 
 	// Table 59
 	struct
 	{
-		unsigned Rc_4	:	1;
-		unsigned SUBOP5	:	5;
-		unsigned RC		:	5;
-		unsigned		:	5;
-		unsigned RA_6	:	5;
-		unsigned RD_2	:	5;
-		unsigned OPCD_D	:	6;
+		u32 Rc_4	:	1;
+		u32 SUBOP5	:	5;
+		u32 RC		:	5;
+		u32			:	5;
+		u32 RA_6	:	5;
+		u32 RD_2	:	5;
+		u32 OPCD_D	:	6;
 	};
 
 	struct
-	{	unsigned		:	10;
-		unsigned OE		:	1;
-		unsigned SPR	:	10;
-		unsigned		:	11;
+	{	u32			:	10;
+		u32 OE		:	1;
+		u32 SPR		:	10;
+		u32			:	11;
 	};
 	struct
 	{
-		unsigned		:	10;
-		unsigned OE_3	:	1;
-		unsigned SPRU	:	5;
-		unsigned SPRL	:	5;
-		unsigned		:	11;
+		u32			:	10;
+		u32 OE_3	:	1;
+		u32 SPRU	:	5;
+		u32 SPRL	:	5;
+		u32			:	11;
 	};
 
 	// rlwinmx
 	struct
 	{
-		unsigned Rc_3	:	1;
-		unsigned ME		:	5;
-		unsigned MB		:	5;
-		unsigned SH		:	5;
-		unsigned		:	16;
+		u32 Rc_3	:	1;
+		u32 ME		:	5;
+		u32 MB		:	5;
+		u32 SH		:	5;
+		u32			:	16;
 	};
 
 	// crxor
 	struct 
 	{
-		unsigned		:	11;
-		unsigned CRBB	:	5;
-		unsigned CRBA	:	5;
-		unsigned CRBD	:	5;		
-		unsigned		:	6;
+		u32			:	11;
+		u32 CRBB	:	5;
+		u32 CRBA	:	5;
+		u32 CRBD	:	5;		
+		u32			:	6;
 	};
 
 	// mftb
 	struct 
 	{
-		unsigned		:	11;
-		unsigned TBR	:	10;
-		unsigned		:	11;
+		u32			:	11;
+		u32 TBR		:	10;
+		u32			:	11;
 	};
 
 	struct 
 	{
-		unsigned		:	11;
-		unsigned TBRU	:	5;
-		unsigned TBRL	:	5;
-		unsigned		:	11;
+		u32			:	11;
+		u32 TBRU	:	5;
+		u32 TBRL	:	5;
+		u32			:	11;
 	};
 
 	struct 
 	{
-		unsigned		:	18;
-		unsigned CRFS	:	3;
-		unsigned 		:	2;
-		unsigned CRFD_5	:	3;
-		unsigned		:	6;
+		u32			:	18;
+		u32 CRFS	:	3;
+		u32 		:	2;
+		u32 CRFD_5	:	3;
+		u32			:	6;
 	};
 
 	// float
 	struct 
 	{
-		unsigned		:	12;
-		unsigned CRM	:	8;
-		unsigned		:	1;
-		unsigned FD		:	5;
-		unsigned		:	6;
+		u32			:	12;
+		u32 CRM		:	8;
+		u32			:	1;
+		u32 FD		:	5;
+		u32			:	6;
 	};
 	struct 
 	{
-		unsigned		:	6;
-		unsigned FC		:	5;
-		unsigned FB		:	5;
-		unsigned FA		:	5;
-		unsigned FS		:	5;
-		unsigned		:	6;
+		u32			:	6;
+		u32 FC		:	5;
+		u32 FB		:	5;
+		u32 FA		:	5;
+		u32 FS		:	5;
+		u32			:	6;
 	};
 	struct 
 	{
-		unsigned OFS    :	16;
-		unsigned        :	16;
+		u32 OFS		:	16;
+		u32			:	16;
 	};
 	struct
 	{
-		unsigned        :   17;
-		unsigned FM     :   8;
-		unsigned        :   7;
+		u32			:   17;
+		u32 FM		:   8;
+		u32			:   7;
 	};
 
 	// paired
 	struct 
 	{
-		unsigned	    :	7;
-		unsigned Ix     :	3;
-		unsigned Wx     :	1;
-		unsigned	     :	1;
-		unsigned I		:   3;
-		unsigned W		:   1;
-		unsigned	    :	16;
+		u32			:	7;
+		u32 Ix		:	3;
+		u32 Wx		:	1;
+		u32			:	1;
+		u32 I		:   3;
+		u32 W		:   1;
+		u32			:	16;
 	};
 
 	struct 
 	{
 		signed	SIMM_12	:	12;
-		unsigned		:	20;
+		u32				:	20;
 	};
 
 	struct 
 	{
-		unsigned dummyX :   11;
-		unsigned NB : 5;
+		u32 dummyX	:   11;
+		u32 NB		: 5;
 	};
 };
 
@@ -277,14 +277,14 @@ union UGQR
 	u32 Hex;
 	struct 
 	{
-		unsigned	ST_TYPE		: 3;
-		unsigned				: 5;
-		unsigned	ST_SCALE	: 6;
-		unsigned				: 2;
-		unsigned	LD_TYPE		: 3;
-		unsigned				: 5;
-		unsigned	LD_SCALE	: 6;
-		unsigned				: 2;
+		u32	ST_TYPE		: 3;
+		u32				: 5;
+		u32	ST_SCALE	: 6;
+		u32				: 2;
+		u32	LD_TYPE		: 3;
+		u32				: 5;
+		u32	LD_SCALE	: 6;
+		u32				: 2;
 	};
 
 	UGQR(u32 _hex) { Hex = _hex; }
@@ -308,11 +308,11 @@ union UReg_XER
 {
 	struct 
 	{
-		unsigned BYTE_COUNT	: 7;
-		unsigned			: 22;
-		unsigned CA			: 1;
-		unsigned OV			: 1;
-		unsigned SO			: 1;
+		u32 BYTE_COUNT	: 7;
+		u32				: 22;
+		u32 CA			: 1;
+		u32 OV			: 1;
+		u32 SO			: 1;
 	};
 	u32 Hex;
 
@@ -325,26 +325,26 @@ union UReg_MSR
 {
 	struct
 	{
-		unsigned LE		:	1;
-		unsigned RI		:	1;
-		unsigned PM		:	1;
-		unsigned 		:	1; // res28
-		unsigned DR		:	1;
-		unsigned IR		:	1;
-		unsigned IP		:	1;
-		unsigned 		:	1; // res24
-		unsigned FE1	:	1;
-		unsigned BE 	:	1;
-		unsigned SE  	:	1;
-		unsigned FE0	:	1;
-		unsigned MCHECK	:	1;
-		unsigned FP		:	1;
-		unsigned PR		:	1;
-		unsigned EE		:	1;
-		unsigned ILE	:	1;
-		unsigned		:	1; // res14
-		unsigned POW	:	1;
-		unsigned res	:	13;
+		u32 LE		:	1;
+		u32 RI		:	1;
+		u32 PM		:	1;
+		u32 		:	1; // res28
+		u32 DR		:	1;
+		u32 IR		:	1;
+		u32 IP		:	1;
+		u32 		:	1; // res24
+		u32 FE1		:	1;
+		u32 BE	 	:	1;
+		u32 SE  	:	1;
+		u32 FE0		:	1;
+		u32 MCHECK	:	1;
+		u32 FP		:	1;
+		u32 PR		:	1;
+		u32 EE		:	1;
+		u32 ILE		:	1;
+		u32			:	1; // res14
+		u32 POW		:	1;
+		u32 res		:	13;
 	};
 	u32 Hex;
 
@@ -357,33 +357,33 @@ union UReg_FPSCR
 {
 	struct
 	{
-		unsigned RN		:	2;
-		unsigned NI		:	1;
-		unsigned XE		:	1;
-		unsigned ZE		:	1;
-		unsigned UE		:	1;
-		unsigned OE		:	1;
-		unsigned VE		:	1;
-		unsigned VXCVI	:	1;
-		unsigned VXSQRT	:	1;
-		unsigned VXSOFT	:	1;
-		unsigned		:	1;
-		unsigned FPRF	:	5;
-		unsigned FI		:	1;
-		unsigned FR		:	1;
-		unsigned VXVC	:	1;
-		unsigned VXIMZ	:	1;
-		unsigned VXZDZ	:	1;
-		unsigned VXIDI	:	1;
-		unsigned VXISI	:	1;
-		unsigned VXSNAN	:	1;
-		unsigned XX		:	1;
-		unsigned ZX		:	1;
-		unsigned UX		:	1;
-		unsigned OX		:	1;
-		unsigned VX		:	1;
-		unsigned FEX	:	1;
-		unsigned FX		:	1;
+		u32 RN		:	2;
+		u32 NI		:	1;
+		u32 XE		:	1;
+		u32 ZE		:	1;
+		u32 UE		:	1;
+		u32 OE		:	1;
+		u32 VE		:	1;
+		u32 VXCVI	:	1;
+		u32 VXSQRT	:	1;
+		u32 VXSOFT	:	1;
+		u32			:	1;
+		u32 FPRF	:	5;
+		u32 FI		:	1;
+		u32 FR		:	1;
+		u32 VXVC	:	1;
+		u32 VXIMZ	:	1;
+		u32 VXZDZ	:	1;
+		u32 VXIDI	:	1;
+		u32 VXISI	:	1;
+		u32 VXSNAN	:	1;
+		u32 XX		:	1;
+		u32 ZX		:	1;
+		u32 UX		:	1;
+		u32 OX		:	1;
+		u32 VX		:	1;
+		u32 FEX		:	1;
+		u32 FX		:	1;
 	};
 	u32 Hex;
 
@@ -396,36 +396,36 @@ union UReg_HID0
 {
 	struct
 	{
-		unsigned NOOPTI		:	1;
-		unsigned			:	1;
-		unsigned BHT		:	1;
-		unsigned ABE		:	1;
-		unsigned			:	1;
-		unsigned BTIC		:	1;
-		unsigned DCFA		:	1;
-		unsigned SGE		:	1;
-		unsigned IFEM		:	1;
-		unsigned SPD		:	1;
-		unsigned DCFI		:	1;
-		unsigned ICFI		:	1;
-		unsigned DLOCK		:	1;
-		unsigned ILOCK		:	1;
-		unsigned DCE		:	1;
-		unsigned ICE		:	1;
-		unsigned NHR		:	1;
-		unsigned			:	3;
-		unsigned DPM		:	1;
-		unsigned SLEEP		:	1;
-		unsigned NAP		:	1;
-		unsigned DOZE		:	1;
-		unsigned PAR		:	1;
-		unsigned ECLK		:	1;
-		unsigned			:	1;
-		unsigned BCLK		:	1;
-		unsigned EBD		:	1;
-		unsigned EBA		:	1;
-		unsigned DBP		:	1;
-		unsigned EMCP		:	1;
+		u32 NOOPTI	:	1;
+		u32			:	1;
+		u32 BHT		:	1;
+		u32 ABE		:	1;
+		u32			:	1;
+		u32 BTIC	:	1;
+		u32 DCFA	:	1;
+		u32 SGE		:	1;
+		u32 IFEM	:	1;
+		u32 SPD		:	1;
+		u32 DCFI	:	1;
+		u32 ICFI	:	1;
+		u32 DLOCK	:	1;
+		u32 ILOCK	:	1;
+		u32 DCE		:	1;
+		u32 ICE		:	1;
+		u32 NHR		:	1;
+		u32			:	3;
+		u32 DPM		:	1;
+		u32 SLEEP	:	1;
+		u32 NAP		:	1;
+		u32 DOZE	:	1;
+		u32 PAR		:	1;
+		u32 ECLK	:	1;
+		u32			:	1;
+		u32 BCLK	:	1;
+		u32 EBD		:	1;
+		u32 EBA		:	1;
+		u32 DBP		:	1;
+		u32 EMCP	:	1;
 	};
 	u32 Hex;
 };
@@ -435,20 +435,20 @@ union UReg_HID2
 {
 	struct
 	{
-		unsigned			:	16;
-		unsigned DQOMEE		:	1;
-		unsigned DCMEE		:	1;
-		unsigned DNCEE		:	1;
-		unsigned DCHEE		:	1;
-		unsigned DQOERR		:	1;
-		unsigned DCEMERR	:	1;
-		unsigned DNCERR		:	1;
-		unsigned DCHERR		:	1;
-		unsigned DMAQL		:	4;
-		unsigned LCE		:	1;
-		unsigned PSE		:	1;
-		unsigned WPE		:	1;
-		unsigned LSQE		:	1;
+		u32			:	16;
+		u32 DQOMEE	:	1;
+		u32 DCMEE	:	1;
+		u32 DNCEE	:	1;
+		u32 DCHEE	:	1;
+		u32 DQOERR	:	1;
+		u32 DCEMERR	:	1;
+		u32 DNCERR	:	1;
+		u32 DCHERR	:	1;
+		u32 DMAQL	:	4;
+		u32 LCE		:	1;
+		u32 PSE		:	1;
+		u32 WPE		:	1;
+		u32 LSQE	:	1;
 	};
 	u32 Hex;
 
@@ -461,17 +461,17 @@ union UReg_HID4
 {
 	struct
 	{
-		unsigned			:	20;
-		unsigned L2CFI		:	1;
-		unsigned L2MUM		:	1;
-		unsigned DBP		:	1;
-		unsigned LPE		:	1;
-		unsigned ST0		:	1;
-		unsigned SBE		:	1;
-		unsigned			:	1;
-		unsigned BPD		:	2;
-		unsigned L2FM		:	2;
-		unsigned			:	1;
+		u32			:	20;
+		u32 L2CFI	:	1;
+		u32 L2MUM	:	1;
+		u32 DBP		:	1;
+		u32 LPE		:	1;
+		u32 ST0		:	1;
+		u32 SBE		:	1;
+		u32			:	1;
+		u32 BPD		:	2;
+		u32 L2FM	:	2;
+		u32			:	1;
 	};
 	u32 Hex;
 
@@ -485,9 +485,9 @@ union UReg_SPR1
 	u32 Hex;
 	struct 
 	{
-		unsigned htaborg  : 16;
-		unsigned          : 7;
-		unsigned htabmask : 9;
+		u32 htaborg  : 16;
+		u32          : 7;
+		u32 htabmask : 9;
 	};
 };
 
@@ -498,9 +498,9 @@ union UReg_WPAR
 {
 	struct
 	{
-		unsigned BNE		: 1;
-		unsigned			: 4;
-		unsigned GB_ADDR	: 27;
+		u32 BNE		: 1;
+		u32			: 4;
+		u32 GB_ADDR	: 27;
 	};
 	u32 Hex;
 
@@ -513,8 +513,8 @@ union UReg_DMAU
 {
 	struct
 	{
-		unsigned DMA_LEN_U	:	5;
-		unsigned MEM_ADDR	:	27;		
+		u32 DMA_LEN_U	:	5;
+		u32 MEM_ADDR	:	27;		
 	};
 	u32 Hex;
 
@@ -527,11 +527,11 @@ union UReg_DMAL
 {
 	struct
 	{
-		unsigned DMA_F		:	1;
-		unsigned DMA_T		:	1;
-		unsigned DMA_LEN_L	:	2;
-		unsigned DMA_LD		:	1;
-		unsigned LC_ADDR	:	27;		
+		u32 DMA_F		:	1;
+		u32 DMA_T		:	1;
+		u32 DMA_LEN_L	:	2;
+		u32 DMA_LD		:	1;
+		u32 LC_ADDR		:	27;		
 	};
 	u32 Hex;
 
@@ -543,11 +543,11 @@ union UReg_BAT_Up
 {
 	struct 
 	{
-		unsigned VP         :   1;
-		unsigned VS         :   1;
-		unsigned BL			:	11; // Block length (aka block size mask)
-		unsigned			:	4;
-		unsigned BEPI		:	15;		
+		u32 VP			:   1;
+		u32 VS			:   1;
+		u32 BL			:	11; // Block length (aka block size mask)
+		u32				:	4;
+		u32 BEPI		:	15;		
 	};
 	u32 Hex;
 
@@ -559,11 +559,11 @@ union UReg_BAT_Lo
 {
 	struct 
 	{
-		unsigned PP         :   2;
-		unsigned            :   1;
-		unsigned WIMG		:	4;
-		unsigned			:	10;
-		unsigned BRPN		:	15; // Physical Block Number
+		u32 PP			:   2;
+		u32				:   1;
+		u32 WIMG		:	4;
+		u32				:	10;
+		u32 BRPN		:	15; // Physical Block Number
 	};
 	u32 Hex;
 
@@ -575,17 +575,17 @@ union UReg_PTE
 {
 	struct 
 	{
-		unsigned API		:	6;
-		unsigned H			:	1;
-		unsigned VSID		:	24;
-		unsigned V			:	1;
-		unsigned PP			:	2;
-		unsigned			:	1;
-		unsigned WIMG		:	4;
-		unsigned C			:	1;
-		unsigned R			:	1;
-		unsigned			:   3;
-		unsigned RPN		:	20;
+		u64 API			:	6;
+		u64 H			:	1;
+		u64 VSID		:	24;
+		u64 V			:	1;
+		u64 PP			:	2;
+		u64				:	1;
+		u64 WIMG		:	4;
+		u64 C			:	1;
+		u64 R			:	1;
+		u64				:   3;
+		u64 RPN			:	20;
 
 	};
 

Source/Core/VideoCommon/Src/BPMemory.h

@@ -199,10 +199,10 @@ union IND_MTXA
 {
     struct
     {
-        signed ma : 11;
-        signed mb : 11;
-        unsigned s0 : 2; // bits 0-1 of scale factor
-        unsigned rid : 8;
+        s32 ma : 11;
+        s32 mb : 11;
+        u32 s0 : 2; // bits 0-1 of scale factor
+        u32 rid : 8;
     };
     u32 hex;
 };
@@ -211,10 +211,10 @@ union IND_MTXB
 {
     struct
     {
-        signed mc : 11;
-        signed md : 11;
-        unsigned s1 : 2; // bits 2-3 of scale factor
-        unsigned rid : 8;
+        s32 mc : 11;
+        s32 md : 11;
+        u32 s1 : 2; // bits 2-3 of scale factor
+        u32 rid : 8;
     };
     u32 hex;
 };
@@ -223,10 +223,10 @@ union IND_MTXC
 {
     struct
     {
-        signed me : 11;
-        signed mf : 11;
-        unsigned s2 : 2; // bits 4-5 of scale factor
-        unsigned rid : 8;
+        s32 me : 11;
+        s32 mf : 11;
+        u32 s2 : 2; // bits 4-5 of scale factor
+        u32 rid : 8;
     };
     u32 hex;
 };
@@ -242,8 +242,8 @@ union IND_IMASK
 {
     struct
     {
-        unsigned mask : 24;
-        unsigned rid : 8;
+        u32 mask : 24;
+        u32 rid : 8;
     };
     u32 hex;
 };
@@ -361,17 +361,17 @@ union TevStageIndirect
     // if mid, sw, tw, and addprev are 0, then no indirect stage is used, mask = 0x17fe00
     struct
     {
-        unsigned bt        : 2; // indirect tex stage ID
-        unsigned fmt       : 2; // format: ITF_X
-        unsigned bias      : 3; // ITB_X
-        unsigned bs        : 2; // ITBA_X, indicates which coordinate will become the 'bump alpha'
-        unsigned mid       : 4; // matrix id to multiply offsets with
-        unsigned sw        : 3; // ITW_X, wrapping factor for S of regular coord
-        unsigned tw        : 3; // ITW_X, wrapping factor for T of regular coord
-        unsigned lb_utclod : 1; // use modified or unmodified texture coordinates for LOD computation
-        unsigned fb_addprev : 1; // 1 if the texture coordinate results from the previous TEV stage should be added
-        unsigned pad0 : 3;
-        unsigned rid : 8;
+        u32 bt			: 2; // indirect tex stage ID
+        u32 fmt			: 2; // format: ITF_X
+        u32 bias		: 3; // ITB_X
+        u32 bs			: 2; // ITBA_X, indicates which coordinate will become the 'bump alpha'
+        u32 mid			: 4; // matrix id to multiply offsets with
+        u32 sw			: 3; // ITW_X, wrapping factor for S of regular coord
+        u32 tw			: 3; // ITW_X, wrapping factor for T of regular coord
+        u32 lb_utclod	: 1; // use modified or unmodified texture coordinates for LOD computation
+        u32 fb_addprev	: 1; // 1 if the texture coordinate results from the previous TEV stage should be added
+        u32 pad0		: 3;
+        u32 rid			: 8;
     };
     struct
     {
@@ -386,20 +386,20 @@ union TwoTevStageOrders
 {
     struct 
     {
-        unsigned texmap0    : 3; // indirect tex stage texmap
-        unsigned texcoord0  : 3;
-        unsigned enable0    : 1; // 1 if should read from texture
-        unsigned colorchan0 : 3; // RAS1_CC_X
+        u32 texmap0    : 3; // indirect tex stage texmap
+        u32 texcoord0  : 3;
+        u32 enable0    : 1; // 1 if should read from texture
+        u32 colorchan0 : 3; // RAS1_CC_X
 
-        unsigned pad0       : 2;
+        u32 pad0       : 2;
 
-        unsigned texmap1    : 3;
-        unsigned texcoord1  : 3;
-        unsigned enable1    : 1; // 1 if should read from texture
-        unsigned colorchan1 : 3; // RAS1_CC_X
+        u32 texmap1    : 3;
+        u32 texcoord1  : 3;
+        u32 enable1    : 1; // 1 if should read from texture
+        u32 colorchan1 : 3; // RAS1_CC_X
 
-        unsigned pad1       : 2;
-        unsigned rid        : 8;
+        u32 pad1       : 2;
+        u32 rid        : 8;
     };
     u32 hex;
     int getTexMap(int i){return i?texmap1:texmap0;}
@@ -412,12 +412,12 @@ union TEXSCALE
 {
     struct
     {
-        unsigned ss0 : 4; // indirect tex stage 0, 2^(-ss0)
-        unsigned ts0 : 4; // indirect tex stage 0
-        unsigned ss1 : 4; // indirect tex stage 1
-        unsigned ts1 : 4; // indirect tex stage 1
-        unsigned pad : 8;
-        unsigned rid : 8;
+        u32 ss0 : 4; // indirect tex stage 0, 2^(-ss0)
+        u32 ts0 : 4; // indirect tex stage 0
+        u32 ss1 : 4; // indirect tex stage 1
+        u32 ts1 : 4; // indirect tex stage 1
+        u32 pad : 8;
+        u32 rid : 8;
     };
     u32 hex;
 
@@ -429,15 +429,15 @@ union RAS1_IREF
 {
     struct
     {
-        unsigned bi0 : 3; // indirect tex stage 0 ntexmap
-        unsigned bc0 : 3; // indirect tex stage 0 ntexcoord
-        unsigned bi1 : 3;
-        unsigned bc1 : 3;
-        unsigned bi2 : 3;
-        unsigned bc3 : 3;
-        unsigned bi4 : 3;
-        unsigned bc4 : 3;
-        unsigned rid : 8;
+        u32 bi0 : 3; // indirect tex stage 0 ntexmap
+        u32 bc0 : 3; // indirect tex stage 0 ntexcoord
+        u32 bi1 : 3;
+        u32 bc1 : 3;
+        u32 bi2 : 3;
+        u32 bc3 : 3;
+        u32 bi4 : 3;
+        u32 bc4 : 3;
+        u32 rid : 8;
     };
     u32 hex;
 
@@ -452,15 +452,15 @@ union TexMode0
 {
     struct 
     {
-        unsigned wrap_s : 2;
-        unsigned wrap_t : 2;
-        unsigned mag_filter : 1;
-        unsigned min_filter : 3;
-        unsigned diag_lod : 1;
-        signed lod_bias : 8;
-		unsigned pad0 : 2;
-        unsigned max_aniso : 2;
-        unsigned lod_clamp : 1;
+        u32 wrap_s : 2;
+        u32 wrap_t : 2;
+        u32 mag_filter : 1;
+        u32 min_filter : 3;
+        u32 diag_lod : 1;
+        s32 lod_bias : 8;
+		u32 pad0 : 2;
+        u32 max_aniso : 2;
+        u32 lod_clamp : 1;
     };
     u32 hex;
 };
@@ -468,8 +468,8 @@ union TexMode1
 {
     struct 
     {
-        unsigned min_lod : 8;
-        unsigned max_lod : 8;
+        u32 min_lod : 8;
+        u32 max_lod : 8;
     };
     u32 hex;
 };
@@ -477,9 +477,9 @@ union TexImage0
 {
     struct 
     {
-        unsigned width : 10; //actually w-1
-        unsigned height : 10; //actually h-1
-        unsigned format : 4;
+        u32 width : 10; //actually w-1
+        u32 height : 10; //actually h-1
+        u32 format : 4;
     };
     u32 hex;
 };
@@ -487,10 +487,10 @@ union TexImage1
 {
     struct 
     {
-        unsigned tmem_offset : 15; // we ignore texture caching for now, we do it ourselves
-        unsigned cache_width : 3; 
-        unsigned cache_height : 3;
-        unsigned image_type : 1;
+        u32 tmem_offset : 15; // we ignore texture caching for now, we do it ourselves
+        u32 cache_width : 3; 
+        u32 cache_height : 3;
+        u32 image_type : 1;
     };
     u32 hex;
 };
@@ -499,9 +499,9 @@ union TexImage2
 {
     struct 
     {
-        unsigned tmem_offset : 15; // we ignore texture caching for now, we do it ourselves
-        unsigned cache_width : 3; 
-        unsigned cache_height : 3;
+        u32 tmem_offset : 15; // we ignore texture caching for now, we do it ourselves
+        u32 cache_width : 3; 
+        u32 cache_height : 3;
     };
     u32 hex;
 };
@@ -510,7 +510,7 @@ union TexImage3
 {
     struct 
     {
-        unsigned image_base: 24;  //address in memory >> 5 (was 20 for GC)
+        u32 image_base: 24;  //address in memory >> 5 (was 20 for GC)
     };
     u32 hex;
 };
@@ -518,8 +518,8 @@ union TexTLUT
 {
     struct 
     {	
-        unsigned tmem_offset : 10;
-        unsigned tlut_format : 2;
+        u32 tmem_offset : 10;
+        u32 tlut_format : 2;
     };
     u32 hex;
 };
@@ -528,7 +528,7 @@ union ZTex1
 {
     struct 
     {
-        unsigned bias : 24;
+        u32 bias : 24;
     };
     u32 hex;
 };
@@ -537,8 +537,8 @@ union ZTex2
 {
     struct 
     {
-        unsigned type : 2; // TEV_Z_TYPE_X
-        unsigned op : 2; // GXZTexOp
+        u32 type : 2; // TEV_Z_TYPE_X
+        u32 op : 2; // GXZTexOp
     };
     u32 hex;
 };
@@ -573,13 +573,13 @@ union GenMode
 {
     struct 
     {
-        unsigned numtexgens : 4;    //     0xF
-        unsigned numcolchans : 5;   //   0x1E0
-        unsigned ms_en : 1;         //   0x200
-        unsigned numtevstages : 4;  //  0x3C00
-        unsigned cullmode : 2;      //  0xC000
-        unsigned numindstages : 3;  // 0x30000
-        unsigned zfreeze : 5;       //0x3C0000
+        u32 numtexgens : 4;    //     0xF
+        u32 numcolchans : 5;   //   0x1E0
+        u32 ms_en : 1;         //   0x200
+        u32 numtevstages : 4;  //  0x3C00
+        u32 cullmode : 2;      //  0xC000
+        u32 numindstages : 3;  // 0x30000
+        u32 zfreeze : 5;       //0x3C0000
     };
     u32 hex;
 };
@@ -588,12 +588,12 @@ union LPSize
 {
     struct 
     {
-        unsigned linesize : 8; // in 1/6th pixels
-        unsigned pointsize : 8; // in 1/6th pixels
-        unsigned lineoff : 3;
-        unsigned pointoff : 3;
-        unsigned lineaspect : 1;
-        unsigned padding : 1;
+        u32 linesize : 8; // in 1/6th pixels
+        u32 pointsize : 8; // in 1/6th pixels
+        u32 lineoff : 3;
+        u32 pointoff : 3;
+        u32 lineaspect : 1;
+        u32 padding : 1;
     };
     u32 hex;
 };
@@ -603,8 +603,8 @@ union X12Y12
 {
     struct 
     {
-        unsigned y : 12;
-        unsigned x : 12;
+        u32 y : 12;
+        u32 x : 12;
     };
     u32 hex;
 };
@@ -612,8 +612,8 @@ union X10Y10
 {
     struct 
     {
-        unsigned x : 10;
-        unsigned y : 10;
+        u32 x : 10;
+        u32 y : 10;
     };
     u32 hex;
 };
@@ -625,15 +625,15 @@ union BlendMode
 {
     struct 
     {
-        unsigned blendenable   : 1;
-        unsigned logicopenable : 1;
-        unsigned dither : 1;
-        unsigned colorupdate : 1;
-        unsigned alphaupdate : 1;
-        unsigned dstfactor : 3; //BLEND_ONE, BLEND_INV_SRc etc
-        unsigned srcfactor : 3;
-        unsigned subtract : 1;
-        unsigned logicmode : 4;
+        u32 blendenable   : 1;
+        u32 logicopenable : 1;
+        u32 dither : 1;
+        u32 colorupdate : 1;
+        u32 alphaupdate : 1;
+        u32 dstfactor : 3; //BLEND_ONE, BLEND_INV_SRc etc
+        u32 srcfactor : 3;
+        u32 subtract : 1;
+        u32 logicmode : 4;
     };
     u32 hex;
 };
@@ -643,9 +643,9 @@ union FogParam0
 {
     struct 
     {
-        unsigned mantissa : 11;
-        unsigned exponent : 8;
-        unsigned sign : 1;
+        u32 mantissa : 11;
+        u32 exponent : 8;
+        u32 sign : 1;
     };
 
     float GetA() {
@@ -661,11 +661,11 @@ union FogParam3
 {
     struct
     {
-        unsigned c_mant : 11;
-        unsigned c_exp : 8;
-        unsigned c_sign : 1;
-        unsigned proj : 1; // 0 - perspective, 1 - orthographic
-        unsigned fsel : 3; // 0 - off, 2 - linear, 4 - exp, 5 - exp2, 6 - backward exp, 7 - backward exp2
+        u32 c_mant : 11;
+        u32 c_exp : 8;
+        u32 c_sign : 1;
+        u32 proj : 1; // 0 - perspective, 1 - orthographic
+        u32 fsel : 3; // 0 - off, 2 - linear, 4 - exp, 5 - exp2, 6 - backward exp, 7 - backward exp2
     };
 
     // amount to subtract from eyespacez after range adjustment
@@ -690,9 +690,9 @@ struct FogParams
     {
         struct
         {
-            unsigned b  : 8;
-            unsigned g  : 8;
-            unsigned r  : 8;
+            u32 b  : 8;
+            u32 g  : 8;
+            u32 r  : 8;
         };
         u32 hex;
     };
@@ -704,9 +704,9 @@ union ZMode
 {
     struct 
     {
-        unsigned testenable		: 1;
-        unsigned func			: 3;
-        unsigned updateenable	: 1;  //size?
+        u32 testenable		: 1;
+        u32 func			: 3;
+        u32 updateenable	: 1;  //size?
     };
     u32 hex;
 };
@@ -715,8 +715,8 @@ union ConstantAlpha
 {
     struct 
     {
-        unsigned alpha : 8;
-        unsigned enable : 1;
+        u32 alpha : 8;
+        u32 enable : 1;
     };
     u32 hex;
 };
@@ -734,11 +734,11 @@ union PE_CONTROL
 {
     struct
     {
-        unsigned pixel_format : 3; // PIXELFMT_X
-        unsigned zformat : 3; // 0 - linear, 1 - near, 2 - mid, 3 - far
-        unsigned zcomploc : 1; // 1: before tex stage
-        unsigned unused : 17;
-        unsigned rid : 8;
+        u32 pixel_format : 3; // PIXELFMT_X
+        u32 zformat : 3; // 0 - linear, 1 - near, 2 - mid, 3 - far
+        u32 zcomploc : 1; // 1: before tex stage
+        u32 unused : 17;
+        u32 rid : 8;
     };
     u32 hex;
 };
@@ -750,9 +750,9 @@ union TCInfo
 {
     struct 
     {
-        unsigned scale_minus_1 : 16;
-        unsigned range_bias : 1;
-        unsigned cylindric_wrap : 1;
+        u32 scale_minus_1 : 16;
+        u32 range_bias : 1;
+        u32 cylindric_wrap : 1;
     };
     u32 hex;
 };
@@ -768,10 +768,10 @@ union ColReg
     u32 hex;
     struct
     {
-        signed a : 11;
-        unsigned : 1;
-        signed b : 11;
-        unsigned type : 1;
+        s32 a : 11;
+        u32 : 1;
+        s32 b : 11;
+        u32 type : 1;
     };
 };
 
@@ -784,12 +784,12 @@ struct TevReg
 union TevKSel
 {
     struct {
-        unsigned swap1 : 2;
-        unsigned swap2 : 2;
-        unsigned kcsel0 : 5;
-        unsigned kasel0 : 5;
-        unsigned kcsel1 : 5;
-        unsigned kasel1 : 5;
+        u32 swap1 : 2;
+        u32 swap2 : 2;
+        u32 kcsel0 : 5;
+        u32 kasel0 : 5;
+        u32 kcsel1 : 5;
+        u32 kasel1 : 5;
     };
     u32 hex;
 
@@ -801,11 +801,11 @@ union AlphaFunc
 {
     struct
     {
-        unsigned ref0 : 8;
-        unsigned ref1 : 8;
-        unsigned comp0 : 3;
-        unsigned comp1 : 3;
-        unsigned logic : 2;
+        u32 ref0 : 8;
+        u32 ref1 : 8;
+        u32 comp0 : 3;
+        u32 comp1 : 3;
+        u32 logic : 2;
     };
     u32 hex;
 };
@@ -815,18 +815,18 @@ union UPE_Copy
     u32 Hex;
     struct 
     {
-        unsigned clamp0					: 1;
-        unsigned clamp1					: 1;
-        unsigned                        : 1;
-        unsigned target_pixel_format	: 4; // realformat is (fmt/2)+((fmt&1)*8).... for some reason the msb is the lsb
-        unsigned gamma					: 2;
-        unsigned half_scale             : 1; // real size should be 2x smaller (run a gauss filter?) "mipmap"
-        unsigned scale_invert			: 1;
-        unsigned clear					: 1;
-        unsigned frame_to_field			: 2;
-        unsigned copy_to_xfb			: 1;
-        unsigned intensity_fmt          : 1; // if set, is an intensity format (I4,I8,IA4,IA8)
-        unsigned						: 16; // seems to set everything to 1s when target pixel format is invalid
+        u32 clamp0				: 1;
+		u32 clamp1				: 1;
+        u32                     : 1;
+        u32 target_pixel_format	: 4; // realformat is (fmt/2)+((fmt&1)*8).... for some reason the msb is the lsb
+        u32 gamma				: 2;
+        u32 half_scale          : 1; // real size should be 2x smaller (run a gauss filter?) "mipmap"
+        u32 scale_invert		: 1;
+        u32 clear				: 1;
+		u32 frame_to_field		: 2;
+        u32 copy_to_xfb			: 1;
+        u32 intensity_fmt       : 1; // if set, is an intensity format (I4,I8,IA4,IA8)
+        u32						: 16; // seems to set everything to 1s when target pixel format is invalid
     };
 };
 

Source/Core/VideoCommon/Src/CPMemory.h

@@ -212,11 +212,11 @@ union TMatrixIndexA
 {
     struct
     {
-        unsigned PosNormalMtxIdx : 6;
-        unsigned Tex0MtxIdx : 6;
-        unsigned Tex1MtxIdx : 6;
-        unsigned Tex2MtxIdx : 6;
-        unsigned Tex3MtxIdx : 6;
+        u32 PosNormalMtxIdx : 6;
+        u32 Tex0MtxIdx : 6;
+        u32 Tex1MtxIdx : 6;
+        u32 Tex2MtxIdx : 6;
+        u32 Tex3MtxIdx : 6;
     };
     struct
     {
@@ -229,10 +229,10 @@ union TMatrixIndexB
 {
     struct
     {
-        unsigned Tex4MtxIdx : 6;
-        unsigned Tex5MtxIdx : 6;
-        unsigned Tex6MtxIdx : 6;
-        unsigned Tex7MtxIdx : 6;
+        u32 Tex4MtxIdx : 6;
+        u32 Tex5MtxIdx : 6;
+        u32 Tex6MtxIdx : 6;
+        u32 Tex7MtxIdx : 6;
     };
     struct
     {

Source/Core/VideoCommon/Src/CommandProcessor.h

@@ -89,12 +89,12 @@ union UCPStatusReg
 {
 	struct
 	{
-		unsigned OverflowHiWatermark	:	1;
-		unsigned UnderflowLoWatermark	:	1;
-		unsigned ReadIdle				:	1;
-		unsigned CommandIdle			:	1;
-		unsigned Breakpoint				:	1;
-		unsigned						:	11;
+		u16 OverflowHiWatermark	:	1;
+		u16 UnderflowLoWatermark:	1;
+		u16 ReadIdle			:	1;
+		u16 CommandIdle			:	1;
+		u16 Breakpoint			:	1;
+		u16						:	11;
 	};
 	u16 Hex;
 	UCPStatusReg() {Hex = 0; }
@@ -106,13 +106,13 @@ union UCPCtrlReg
 {
 	struct
 	{
-		unsigned GPReadEnable			:	1;
-		unsigned BPEnable				:	1;
-		unsigned FifoOverflowIntEnable	:	1;
-		unsigned FifoUnderflowIntEnable	:	1;
-		unsigned GPLinkEnable			:	1;
-		unsigned BPInt					:	1;
-		unsigned						:	10;
+		u16 GPReadEnable			:	1;
+		u16 BPEnable				:	1;
+		u16 FifoOverflowIntEnable	:	1;
+		u16 FifoUnderflowIntEnable	:	1;
+		u16 GPLinkEnable			:	1;
+		u16 BPInt					:	1;
+		u16							:	10;
 	};
 	u16 Hex;
 	UCPCtrlReg() {Hex = 0; }
@@ -124,10 +124,10 @@ union UCPClearReg
 {
 	struct
 	{
-		unsigned ClearFifoOverflow		:	1;
-		unsigned ClearFifoUnderflow		:	1;
-		unsigned ClearMetrices			:	1;
-		unsigned						:	13;
+		u16 ClearFifoOverflow		:	1;
+		u16 ClearFifoUnderflow		:	1;
+		u16 ClearMetrices			:	1;
+		u16							:	13;
 	};
 	u16 Hex;
 	UCPClearReg() {Hex = 0; }

Source/Core/VideoCommon/Src/XFMemory.h

@@ -109,13 +109,13 @@ union LitChannel
 {
     struct
     {
-        unsigned matsource      : 1;
-        unsigned enablelighting : 1;
-        unsigned lightMask0_3   : 4;
-        unsigned ambsource      : 1;
-        unsigned diffusefunc    : 2; // LIGHTDIF_X
-        unsigned attnfunc       : 2; // LIGHTATTN_X
-        unsigned lightMask4_7   : 4;
+        u32 matsource      : 1;
+        u32 enablelighting : 1;
+        u32 lightMask0_3   : 4;
+        u32 ambsource      : 1;
+        u32 diffusefunc    : 2; // LIGHTDIF_X
+        u32 attnfunc       : 2; // LIGHTATTN_X
+        u32 lightMask4_7   : 4;
     };
     struct
     {
@@ -139,10 +139,10 @@ union INVTXSPEC
 {
     struct
     {
-        unsigned numcolors : 2;
-        unsigned numnormals : 2; // 0 - nothing, 1 - just normal, 2 - normals and binormals
-        unsigned numtextures : 4;
-        unsigned unused : 24;
+        u32 numcolors : 2;
+        u32 numnormals : 2; // 0 - nothing, 1 - just normal, 2 - normals and binormals
+        u32 numtextures : 4;
+        u32 unused : 24;
     };
     u32 hex;
 };
@@ -151,13 +151,13 @@ union TexMtxInfo
 {
     struct 
     {
-        unsigned unknown : 1;
-        unsigned projection : 1; // XF_TEXPROJ_X
-        unsigned inputform : 2; // XF_TEXINPUT_X
-        unsigned texgentype : 3; // XF_TEXGEN_X
-        unsigned sourcerow : 5; // XF_SRCGEOM_X
-        unsigned embosssourceshift : 3; // what generated texcoord to use
-        unsigned embosslightshift : 3; // light index that is used
+        u32 unknown : 1;
+        u32 projection : 1; // XF_TEXPROJ_X
+        u32 inputform : 2; // XF_TEXINPUT_X
+        u32 texgentype : 3; // XF_TEXGEN_X
+        u32 sourcerow : 5; // XF_SRCGEOM_X
+        u32 embosssourceshift : 3; // what generated texcoord to use
+        u32 embosslightshift : 3; // light index that is used
     };
     u32 hex;
 };
@@ -166,9 +166,9 @@ union PostMtxInfo
 {
     struct 
     {
-        unsigned index : 6; // base row of dual transform matrix
-        unsigned unused : 2;
-        unsigned normalize : 1; // normalize before send operation
+        u32 index : 6; // base row of dual transform matrix
+        u32 unused : 2;
+        u32 normalize : 1; // normalize before send operation
     };
     u32 hex;
 };

Source/Plugins/Plugin_VideoSoftware/Src/CommandProcessor.h

@@ -74,12 +74,12 @@ namespace CommandProcessor
     {
 	    struct
 	    {
-		    unsigned OverflowHiWatermark	:	1;
-		    unsigned UnderflowLoWatermark	:	1;
-		    unsigned ReadIdle				:	1; // done reading
-		    unsigned CommandIdle			:	1; // done processing commands
-		    unsigned Breakpoint				:	1;
-		    unsigned						:	11;
+		    u16 OverflowHiWatermark	:	1;
+		    u16 UnderflowLoWatermark:	1;
+		    u16 ReadIdle			:	1; // done reading
+		    u16 CommandIdle			:	1; // done processing commands
+		    u16 Breakpoint			:	1;
+		    u16						:	11;
 	    };
 	    u16 Hex;
 	    UCPStatusReg() {Hex = 0; }
@@ -91,13 +91,13 @@ namespace CommandProcessor
     {
 	    struct
 	    {
-		    unsigned GPReadEnable			:	1;
-		    unsigned BPEnable           	:	1;
-		    unsigned FifoOverflowIntEnable	:	1;
-		    unsigned FifoUnderflowIntEnable	:	1;
-		    unsigned GPLinkEnable			:	1;
-		    unsigned BreakPointIntEnable	:	1;
-		    unsigned						:	10;
+		    u16 GPReadEnable			:	1;
+		    u16 BPEnable           		:	1;
+		    u16 FifoOverflowIntEnable	:	1;
+		    u16 FifoUnderflowIntEnable	:	1;
+		    u16 GPLinkEnable			:	1;
+		    u16 BreakPointIntEnable		:	1;
+		    u16							:	10;
 	    };
 	    u16 Hex;
 	    UCPCtrlReg() {Hex = 0; }
@@ -109,10 +109,10 @@ namespace CommandProcessor
     {
 	    struct
 	    {
-		    unsigned ClearFifoOverflow		:	1;
-		    unsigned ClearFifoUnderflow		:	1;
-		    unsigned ClearMetrices			:	1;
-		    unsigned						:	13;
+		    u16 ClearFifoOverflow		:	1;
+		    u16 ClearFifoUnderflow		:	1;
+		    u16 ClearMetrices			:	1;
+		    u16							:	13;
 	    };
 	    u16 Hex;
 	    UCPClearReg() {Hex = 0; }

Source/Plugins/Plugin_VideoSoftware/Src/XFMemLoader.h

@@ -89,14 +89,14 @@ union LitChannel
 {
     struct
     {
-        unsigned matsource      : 1;
-        unsigned enablelighting : 1;
-        unsigned lightMask0_3   : 4;
-        unsigned ambsource      : 1;
-        unsigned diffusefunc    : 2; // LIGHTDIF_X
-        unsigned attnfunc       : 2; // LIGHTATTN_X
-        unsigned lightMask4_7   : 4;
-        unsigned unused         : 17;
+        u32 matsource      : 1;
+        u32 enablelighting : 1;
+        u32 lightMask0_3   : 4;
+        u32 ambsource      : 1;
+        u32 diffusefunc    : 2; // LIGHTDIF_X
+        u32 attnfunc       : 2; // LIGHTATTN_X
+        u32 lightMask4_7   : 4;
+        u32 unused         : 17;
     };
     u32 hex;
     unsigned int GetFullLightMask() const
@@ -109,10 +109,10 @@ union INVTXSPEC
 {
     struct
     {
-        unsigned numcolors : 2;
-        unsigned numnormals : 2; // 0 - nothing, 1 - just normal, 2 - normals and binormals
-        unsigned numtextures : 4;
-        unsigned unused : 24;
+        u32 numcolors : 2;
+        u32 numnormals : 2; // 0 - nothing, 1 - just normal, 2 - normals and binormals
+        u32 numtextures : 4;
+        u32 unused : 24;
     };
     u32 hex;
 };
@@ -121,11 +121,11 @@ union TXFMatrixIndexA
 {
     struct
     {
-        unsigned PosNormalMtxIdx : 6;
-        unsigned Tex0MtxIdx : 6;
-        unsigned Tex1MtxIdx : 6;
-        unsigned Tex2MtxIdx : 6;
-        unsigned Tex3MtxIdx : 6;
+        u32 PosNormalMtxIdx : 6;
+        u32 Tex0MtxIdx : 6;
+        u32 Tex1MtxIdx : 6;
+        u32 Tex2MtxIdx : 6;
+        u32 Tex3MtxIdx : 6;
     };
     struct
     {
@@ -138,10 +138,10 @@ union TXFMatrixIndexB
 {
     struct
     {
-        unsigned Tex4MtxIdx : 6;
-        unsigned Tex5MtxIdx : 6;
-        unsigned Tex6MtxIdx : 6;
-        unsigned Tex7MtxIdx : 6;
+        u32 Tex4MtxIdx : 6;
+        u32 Tex5MtxIdx : 6;
+        u32 Tex6MtxIdx : 6;
+        u32 Tex7MtxIdx : 6;
     };
     struct
     {
@@ -164,13 +164,13 @@ union TexMtxInfo
 {
     struct 
     {
-        unsigned unknown : 1;
-        unsigned projection : 1; // XF_TEXPROJ_X
-        unsigned inputform : 2; // XF_TEXINPUT_X
-        unsigned texgentype : 3; // XF_TEXGEN_X
-        unsigned sourcerow : 5; // XF_SRCGEOM_X
-        unsigned embosssourceshift : 3; // what generated texcoord to use
-        unsigned embosslightshift : 3; // light index that is used
+        u32 unknown : 1;
+        u32 projection : 1; // XF_TEXPROJ_X
+        u32 inputform : 2; // XF_TEXINPUT_X
+        u32 texgentype : 3; // XF_TEXGEN_X
+        u32 sourcerow : 5; // XF_SRCGEOM_X
+        u32 embosssourceshift : 3; // what generated texcoord to use
+        u32 embosslightshift : 3; // light index that is used
     };
     u32 hex;
 };
@@ -179,9 +179,9 @@ union PostMtxInfo
 {
     struct 
     {
-        unsigned index : 6; // base row of dual transform matrix
-        unsigned unused : 2;
-        unsigned normalize : 1; // normalize before send operation
+        u32 index : 6; // base row of dual transform matrix
+        u32 unused : 2;
+        u32 normalize : 1; // normalize before send operation
     };
     u32 hex;
 };