diff --git a/Source/Core/Core/PowerPC/JitArm64/Jit.h b/Source/Core/Core/PowerPC/JitArm64/Jit.h
index 7bd62b0aab..6c776e2230 100644
--- a/Source/Core/Core/PowerPC/JitArm64/Jit.h
+++ b/Source/Core/Core/PowerPC/JitArm64/Jit.h
@@ -145,17 +145,13 @@ public:
 	void fctiwzx(UGeckoInstruction inst);
 
 	// Paired
-	void ps_abs(UGeckoInstruction inst);
 	void ps_madd(UGeckoInstruction inst);
 	void ps_maddsX(UGeckoInstruction inst);
 	void ps_mergeXX(UGeckoInstruction inst);
-	void ps_mr(UGeckoInstruction inst);
 	void ps_msub(UGeckoInstruction inst);
 	void ps_mulsX(UGeckoInstruction inst);
-	void ps_nabs(UGeckoInstruction inst);
 	void ps_nmadd(UGeckoInstruction inst);
 	void ps_nmsub(UGeckoInstruction inst);
-	void ps_neg(UGeckoInstruction inst);
 	void ps_res(UGeckoInstruction inst);
 	void ps_sel(UGeckoInstruction inst);
 	void ps_sum0(UGeckoInstruction inst);
diff --git a/Source/Core/Core/PowerPC/JitArm64/JitArm64_FloatingPoint.cpp b/Source/Core/Core/PowerPC/JitArm64/JitArm64_FloatingPoint.cpp
index 9d96ed70c9..f1f956db69 100644
--- a/Source/Core/Core/PowerPC/JitArm64/JitArm64_FloatingPoint.cpp
+++ b/Source/Core/Core/PowerPC/JitArm64/JitArm64_FloatingPoint.cpp
@@ -87,20 +87,43 @@ void JitArm64::fp_logic(UGeckoInstruction inst)
 	FALLBACK_IF(inst.Rc);
 
 	u32 b = inst.FB, d = inst.FD;
-
 	u32 op10 = inst.SUBOP10;
 
-	ARM64Reg VB = fpr.R(b, REG_IS_LOADED);
-	ARM64Reg VD = fpr.RW(d);
+	bool packed = inst.OPCD == 4;
 
-	switch (op10)
+	// MR with source === dest => no-op
+	if (op10 == 72 && b == d)
+		return;
+
+	if (packed)
 	{
-	case  40: m_float_emit.FNEG(EncodeRegToDouble(VD), EncodeRegToDouble(VB)); break;
-	case  72: m_float_emit.INS(64, VD, 0, VB, 0); break;
-	case 136: m_float_emit.FABS(EncodeRegToDouble(VD), EncodeRegToDouble(VB));
-	          m_float_emit.FNEG(EncodeRegToDouble(VD), EncodeRegToDouble(VD)); break;
-	case 264: m_float_emit.FABS(EncodeRegToDouble(VD), EncodeRegToDouble(VB)); break;
-	default: _assert_msg_(DYNA_REC, 0, "fp_logic WTF!!!");
+		ARM64Reg VB = fpr.R(b, REG_REG);
+		ARM64Reg VD = fpr.RW(d, REG_REG);
+
+		switch (op10)
+		{
+		case  40: m_float_emit.FNEG(64, VD, VB); break;
+		case  72: m_float_emit.ORR(VD, VB, VB); break;
+		case 136: m_float_emit.FABS(64, VD, VB);
+		          m_float_emit.FNEG(64, VD, VD); break;
+		case 264: m_float_emit.FABS(64, VD, VB); break;
+		default: _assert_msg_(DYNA_REC, 0, "fp_logic"); break;
+		}
+	}
+	else
+	{
+		ARM64Reg VB = fpr.R(b, REG_IS_LOADED);
+		ARM64Reg VD = fpr.RW(d);
+
+		switch (op10)
+		{
+		case  40: m_float_emit.FNEG(EncodeRegToDouble(VD), EncodeRegToDouble(VB)); break;
+		case  72: m_float_emit.INS(64, VD, 0, VB, 0); break;
+		case 136: m_float_emit.FABS(EncodeRegToDouble(VD), EncodeRegToDouble(VB));
+		          m_float_emit.FNEG(EncodeRegToDouble(VD), EncodeRegToDouble(VD)); break;
+		case 264: m_float_emit.FABS(EncodeRegToDouble(VD), EncodeRegToDouble(VB)); break;
+		default: _assert_msg_(DYNA_REC, 0, "fp_logic"); break;
+		}
 	}
 }
 
diff --git a/Source/Core/Core/PowerPC/JitArm64/JitArm64_Paired.cpp b/Source/Core/Core/PowerPC/JitArm64/JitArm64_Paired.cpp
index b815f3e593..8665adb912 100644
--- a/Source/Core/Core/PowerPC/JitArm64/JitArm64_Paired.cpp
+++ b/Source/Core/Core/PowerPC/JitArm64/JitArm64_Paired.cpp
@@ -17,20 +17,6 @@
 
 using namespace Arm64Gen;
 
-void JitArm64::ps_abs(UGeckoInstruction inst)
-{
-	INSTRUCTION_START
-	JITDISABLE(bJITPairedOff);
-	FALLBACK_IF(inst.Rc);
-
-	u32 b = inst.FB, d = inst.FD;
-
-	ARM64Reg VB = fpr.R(b, REG_REG);
-	ARM64Reg VD = fpr.RW(d, REG_REG);
-
-	m_float_emit.FABS(64, VD, VB);
-}
-
 void JitArm64::ps_madd(UGeckoInstruction inst)
 {
 	INSTRUCTION_START
@@ -123,23 +109,6 @@ void JitArm64::ps_mergeXX(UGeckoInstruction inst)
 	}
 }
 
-void JitArm64::ps_mr(UGeckoInstruction inst)
-{
-	INSTRUCTION_START
-	JITDISABLE(bJITPairedOff);
-	FALLBACK_IF(inst.Rc);
-
-	u32 b = inst.FB, d = inst.FD;
-
-	if (d == b)
-		return;
-
-	ARM64Reg VB = fpr.R(b, REG_REG);
-	ARM64Reg VD = fpr.RW(d, REG_REG);
-
-	m_float_emit.ORR(VD, VB, VB);
-}
-
 void JitArm64::ps_mulsX(UGeckoInstruction inst)
 {
 	INSTRUCTION_START
@@ -184,35 +153,6 @@ void JitArm64::ps_msub(UGeckoInstruction inst)
 	fpr.Unlock(V0);
 }
 
-void JitArm64::ps_nabs(UGeckoInstruction inst)
-{
-	INSTRUCTION_START
-	JITDISABLE(bJITPairedOff);
-	FALLBACK_IF(inst.Rc);
-
-	u32 b = inst.FB, d = inst.FD;
-
-	ARM64Reg VB = fpr.R(b, REG_REG);
-	ARM64Reg VD = fpr.RW(d, REG_REG);
-
-	m_float_emit.FABS(64, VD, VB);
-	m_float_emit.FNEG(64, VD, VD);
-}
-
-void JitArm64::ps_neg(UGeckoInstruction inst)
-{
-	INSTRUCTION_START
-	JITDISABLE(bJITPairedOff);
-	FALLBACK_IF(inst.Rc);
-
-	u32 b = inst.FB, d = inst.FD;
-
-	ARM64Reg VB = fpr.R(b, REG_REG);
-	ARM64Reg VD = fpr.RW(d, REG_REG);
-
-	m_float_emit.FNEG(64, VD, VB);
-}
-
 void JitArm64::ps_nmadd(UGeckoInstruction inst)
 {
 	INSTRUCTION_START
diff --git a/Source/Core/Core/PowerPC/JitArm64/JitArm64_Tables.cpp b/Source/Core/Core/PowerPC/JitArm64/JitArm64_Tables.cpp
index 7a109ff14a..7b7c38a481 100644
--- a/Source/Core/Core/PowerPC/JitArm64/JitArm64_Tables.cpp
+++ b/Source/Core/Core/PowerPC/JitArm64/JitArm64_Tables.cpp
@@ -104,11 +104,11 @@ static GekkoOPTemplate table4[] =
 {    //SUBOP10
 	{0,    &JitArm64::FallBackToInterpreter},   // ps_cmpu0
 	{32,   &JitArm64::FallBackToInterpreter},   // ps_cmpo0
-	{40,   &JitArm64::ps_neg},                  // ps_neg
-	{136,  &JitArm64::ps_nabs},                 // ps_nabs
-	{264,  &JitArm64::ps_abs},                  // ps_abs
+	{40,   &JitArm64::fp_logic},                // ps_neg
+	{136,  &JitArm64::fp_logic},                // ps_nabs
+	{264,  &JitArm64::fp_logic},                // ps_abs
 	{64,   &JitArm64::FallBackToInterpreter},   // ps_cmpu1
-	{72,   &JitArm64::ps_mr},                   // ps_mr
+	{72,   &JitArm64::fp_logic},                // ps_mr
 	{96,   &JitArm64::FallBackToInterpreter},   // ps_cmpo1
 	{528,  &JitArm64::ps_mergeXX},              // ps_merge00
 	{560,  &JitArm64::ps_mergeXX},              // ps_merge01