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JIT: some paired singles optimizations
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Fiora
parent
68b2d86daf
commit
34287b8042
@ -3,19 +3,13 @@
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// Refer to the license.txt file included.
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#include "Common/CommonTypes.h"
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#include "Common/CPUDetect.h"
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#include "Core/PowerPC/Jit64/Jit.h"
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#include "Core/PowerPC/Jit64/JitRegCache.h"
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using namespace Gen;
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// TODO
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// ps_madds0
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// ps_muls0
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// ps_madds1
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// cmppd, andpd, andnpd, or
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// lfsx, ps_merge01 etc
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static const u64 GC_ALIGNED16(psSignBits[2]) = {0x8000000000000000ULL, 0x8000000000000000ULL};
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static const u64 GC_ALIGNED16(psAbsMask[2]) = {0x7FFFFFFFFFFFFFFFULL, 0x7FFFFFFFFFFFFFFFULL};
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@ -36,9 +30,6 @@ void Jit64::ps_mr(UGeckoInstruction inst)
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void Jit64::ps_sel(UGeckoInstruction inst)
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{
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// we can't use (V)BLENDVPD here because it just looks at the sign bit
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// but we need -0 = +0
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INSTRUCTION_START
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JITDISABLE(bJITPairedOff);
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FALLBACK_IF(inst.Rc);
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@ -49,16 +40,26 @@ void Jit64::ps_sel(UGeckoInstruction inst)
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int c = inst.FC;
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fpr.Lock(a, b, c, d);
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MOVAPD(XMM0, fpr.R(a));
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PXOR(XMM1, R(XMM1));
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// XMM0 = XMM0 < 0 ? all 1s : all 0s
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CMPPD(XMM0, R(XMM1), LT);
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MOVAPD(XMM1, R(XMM0));
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PAND(XMM0, fpr.R(b));
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PANDN(XMM1, fpr.R(c));
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POR(XMM0, R(XMM1));
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if (cpu_info.bSSE4_1)
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{
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PXOR(XMM0, R(XMM0));
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CMPPD(XMM0, fpr.R(a), LT); // XMM0 = XMM0 >= 0 ? all 1s : all 0s
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MOVAPD(XMM1, fpr.R(b));
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BLENDVPD(XMM1, fpr.R(c));
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}
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else
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{
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MOVAPD(XMM1, fpr.R(a));
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PXOR(XMM0, R(XMM0));
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CMPPD(XMM1, R(XMM0), LT); // XMM0 = XMM0 < 0 ? all 1s : all 0s
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MOVAPD(XMM0, R(XMM1));
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PAND(XMM1, fpr.R(b));
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PANDN(XMM0, fpr.R(c));
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POR(XMM1, R(XMM0));
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}
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fpr.BindToRegister(d, false);
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MOVAPD(fpr.RX(d), R(XMM0));
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MOVAPD(fpr.RX(d), R(XMM1));
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fpr.UnlockAll();
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}
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@ -98,20 +99,6 @@ void Jit64::ps_sign(UGeckoInstruction inst)
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fpr.UnlockAll();
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}
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//add a, b, c
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//mov a, b
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//add a, c
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//we need:
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/*
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psq_l
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psq_stu
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*/
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/*
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add a,b,a
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*/
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//There's still a little bit more optimization that can be squeezed out of this
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void Jit64::tri_op(int d, int a, int b, bool reversible, void (XEmitter::*op)(X64Reg, OpArg), UGeckoInstruction inst, bool roundRHS)
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{
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@ -152,7 +139,7 @@ void Jit64::tri_op(int d, int a, int b, bool reversible, void (XEmitter::*op)(X6
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MOVAPD(XMM0, fpr.R(b));
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fpr.BindToRegister(d, false);
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MOVAPD(fpr.RX(d), fpr.R(a));
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(this->*op)(fpr.RX(d), Gen::R(XMM0));
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(this->*op)(fpr.RX(d), R(XMM0));
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}
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}
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else
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@ -204,32 +191,26 @@ void Jit64::ps_sum(UGeckoInstruction inst)
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int b = inst.FB;
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int c = inst.FC;
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fpr.Lock(a,b,c,d);
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fpr.BindToRegister(d, d == a || d == b || d == c, true);
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switch (inst.SUBOP5)
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{
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case 10:
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// ps_sum0, do the sum in upper subregisters, merge uppers
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MOVDDUP(XMM0, fpr.R(a));
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MOVAPD(XMM1, fpr.R(b));
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ADDPD(XMM0, R(XMM1));
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UNPCKHPD(XMM0, fpr.R(c)); //merge
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MOVAPD(fpr.R(d), XMM0);
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MOVDDUP(XMM0, fpr.R(a)); // {a.ps0, a.ps0}
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ADDPD(XMM0, fpr.R(b)); // {a.ps0 + b.ps0, a.ps0 + b.ps1}
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UNPCKHPD(XMM0, fpr.R(c)); // {a.ps0 + b.ps1, c.ps1}
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break;
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case 11:
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// ps_sum1, do the sum in lower subregisters, merge lowers
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MOVAPD(XMM0, fpr.R(a));
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MOVAPD(XMM1, fpr.R(b));
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SHUFPD(XMM1, R(XMM1), 5); // copy higher to lower
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ADDPD(XMM0, R(XMM1)); // sum lowers
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MOVAPD(XMM1, fpr.R(c));
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UNPCKLPD(XMM1, R(XMM0)); // merge
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MOVAPD(fpr.R(d), XMM1);
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MOVDDUP(XMM1, fpr.R(a)); // {a.ps0, a.ps0}
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ADDPD(XMM1, fpr.R(b)); // {a.ps0 + b.ps0, a.ps0 + b.ps1}
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MOVAPD(XMM0, fpr.R(c));
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SHUFPD(XMM0, R(XMM1), 2); // {c.ps0, a.ps0 + b.ps1}
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break;
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default:
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PanicAlert("ps_sum WTF!!!");
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}
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ForceSinglePrecisionP(fpr.RX(d));
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SetFPRFIfNeeded(inst, fpr.RX(d));
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ForceSinglePrecisionP(XMM0);
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SetFPRFIfNeeded(inst, XMM0);
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fpr.BindToRegister(d, false);
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MOVAPD(fpr.RX(d), R(XMM0));
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fpr.UnlockAll();
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}
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@ -244,37 +225,28 @@ void Jit64::ps_muls(UGeckoInstruction inst)
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int a = inst.FA;
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int c = inst.FC;
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fpr.Lock(a, c, d);
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fpr.BindToRegister(d, d == a || d == c, true);
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switch (inst.SUBOP5)
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{
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case 12:
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// Single multiply scalar high
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// TODO - faster version for when regs are different
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MOVDDUP(XMM1, fpr.R(c));
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Force25BitPrecision(XMM1, XMM0);
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MOVAPD(XMM0, fpr.R(a));
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MULPD(XMM0, R(XMM1));
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MOVAPD(fpr.R(d), XMM0);
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MOVDDUP(XMM0, fpr.R(c));
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break;
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case 13:
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// TODO - faster version for when regs are different
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MOVAPD(XMM1, fpr.R(c));
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Force25BitPrecision(XMM1, XMM0);
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MOVAPD(XMM0, fpr.R(a));
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SHUFPD(XMM1, R(XMM1), 3); // copy higher to lower
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MULPD(XMM0, R(XMM1));
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MOVAPD(fpr.R(d), XMM0);
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MOVAPD(XMM0, fpr.R(c));
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SHUFPD(XMM0, R(XMM0), 3);
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break;
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default:
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PanicAlert("ps_muls WTF!!!");
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}
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ForceSinglePrecisionP(fpr.RX(d));
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SetFPRFIfNeeded(inst, fpr.RX(d));
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Force25BitPrecision(XMM0, XMM1);
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MULPD(XMM0, fpr.R(a));
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ForceSinglePrecisionP(XMM0);
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SetFPRFIfNeeded(inst, XMM0);
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fpr.BindToRegister(d, false);
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MOVAPD(fpr.RX(d), R(XMM0));
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fpr.UnlockAll();
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}
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//TODO: find easy cases and optimize them, do a breakout like ps_arith
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void Jit64::ps_mergeXX(UGeckoInstruction inst)
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{
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INSTRUCTION_START
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@ -305,7 +277,7 @@ void Jit64::ps_mergeXX(UGeckoInstruction inst)
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_assert_msg_(DYNA_REC, 0, "ps_merge - invalid op");
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}
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fpr.BindToRegister(d, false);
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MOVAPD(fpr.RX(d), Gen::R(XMM0));
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MOVAPD(fpr.RX(d), R(XMM0));
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fpr.UnlockAll();
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}
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@ -373,8 +345,8 @@ void Jit64::ps_maddXX(UGeckoInstruction inst)
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return;
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}
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fpr.BindToRegister(d, false);
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MOVAPD(fpr.RX(d), Gen::R(XMM0));
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ForceSinglePrecisionP(fpr.RX(d));
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SetFPRFIfNeeded(inst, fpr.RX(d));
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ForceSinglePrecisionP(XMM0);
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SetFPRFIfNeeded(inst, XMM0);
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MOVAPD(fpr.RX(d), R(XMM0));
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fpr.UnlockAll();
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}
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