From 4fa61a1e7ff247678da8500e81b4208128bc591a Mon Sep 17 00:00:00 2001 From: skidau Date: Mon, 25 Mar 2013 00:57:53 +1100 Subject: [PATCH] Removed the tracking of the FIFO Writes as it was made obsolete by r1d550f4496e4. --- Source/Core/Core/Src/HW/GPFifo.cpp | 14 ----------- Source/Core/Core/Src/PowerPC/Jit64/Jit.cpp | 24 ------------------- Source/Core/Core/Src/PowerPC/Jit64IL/IR.cpp | 2 +- Source/Core/Core/Src/PowerPC/Jit64IL/IR.h | 5 +--- .../Core/Core/Src/PowerPC/Jit64IL/IR_X86.cpp | 22 ----------------- .../Core/Core/Src/PowerPC/Jit64IL/JitIL.cpp | 5 ---- .../Core/Core/Src/PowerPC/JitCommon/JitBase.h | 2 -- 7 files changed, 2 insertions(+), 72 deletions(-) diff --git a/Source/Core/Core/Src/HW/GPFifo.cpp b/Source/Core/Core/Src/HW/GPFifo.cpp index a7f7bd967b..ab3058bd8d 100644 --- a/Source/Core/Core/Src/HW/GPFifo.cpp +++ b/Source/Core/Core/Src/HW/GPFifo.cpp @@ -96,20 +96,6 @@ void STACKALIGN CheckGatherPipe() // move back the spill bytes memmove(m_gatherPipe, m_gatherPipe + cnt, m_gatherPipeCount); - - // Profile where the FIFO writes are occurring. - if (jit && PC != 0 && (jit->js.fifoWriteAddresses.find(PC)) == (jit->js.fifoWriteAddresses.end())) - { - // Log only stores, fp stores and ps stores, filtering out other instructions arrived via optimizeGatherPipe - int type = GetOpInfo(Memory::ReadUnchecked_U32(PC))->type; - if (type == OPTYPE_STORE || type == OPTYPE_STOREFP || (type == OPTYPE_PS && !strcmp(GetOpInfo(Memory::ReadUnchecked_U32(PC))->opname, "psq_st"))) - { - jit->js.fifoWriteAddresses.insert(PC); - - // Invalidate the JIT block so that it gets recompiled with the external exception check included. - jit->GetBlockCache()->InvalidateICache(PC, 4); - } - } } } diff --git a/Source/Core/Core/Src/PowerPC/Jit64/Jit.cpp b/Source/Core/Core/Src/PowerPC/Jit64/Jit.cpp index be4789e233..fd24b36406 100644 --- a/Source/Core/Core/Src/PowerPC/Jit64/Jit.cpp +++ b/Source/Core/Core/Src/PowerPC/Jit64/Jit.cpp @@ -611,30 +611,6 @@ const u8* Jit64::DoJit(u32 em_address, PPCAnalyst::CodeBuffer *code_buf, JitBloc js.firstFPInstructionFound = true; } - // Add an external exception check if the instruction writes to the FIFO. - if (jit->js.fifoWriteAddresses.find(ops[i].address) != jit->js.fifoWriteAddresses.end()) - { - gpr.Flush(FLUSH_ALL); - fpr.Flush(FLUSH_ALL); - - TEST(32, M((void *)&PowerPC::ppcState.Exceptions), Imm32(EXCEPTION_ISI | EXCEPTION_PROGRAM | EXCEPTION_SYSCALL | EXCEPTION_FPU_UNAVAILABLE | EXCEPTION_DSI | EXCEPTION_ALIGNMENT)); - FixupBranch clearInt = J_CC(CC_NZ, true); - TEST(32, M((void *)&PowerPC::ppcState.Exceptions), Imm32(EXCEPTION_EXTERNAL_INT)); - FixupBranch noExtException = J_CC(CC_Z, true); - TEST(32, M((void *)&PowerPC::ppcState.msr), Imm32(0x0008000)); - FixupBranch noExtIntEnable = J_CC(CC_Z, true); - TEST(32, M((void *)&ProcessorInterface::m_InterruptCause), Imm32(ProcessorInterface::INT_CAUSE_CP | ProcessorInterface::INT_CAUSE_PE_TOKEN | ProcessorInterface::INT_CAUSE_PE_FINISH)); - FixupBranch noCPInt = J_CC(CC_Z, true); - - MOV(32, M(&PC), Imm32(ops[i].address)); - WriteExternalExceptionExit(); - - SetJumpTarget(noCPInt); - SetJumpTarget(noExtIntEnable); - SetJumpTarget(noExtException); - SetJumpTarget(clearInt); - } - if (Core::g_CoreStartupParameter.bEnableDebugging && breakpoints.IsAddressBreakPoint(ops[i].address) && GetState() != CPU_STEPPING) { gpr.Flush(FLUSH_ALL); diff --git a/Source/Core/Core/Src/PowerPC/Jit64IL/IR.cpp b/Source/Core/Core/Src/PowerPC/Jit64IL/IR.cpp index 2a830a03cf..fdec5b747d 100644 --- a/Source/Core/Core/Src/PowerPC/Jit64IL/IR.cpp +++ b/Source/Core/Core/Src/PowerPC/Jit64IL/IR.cpp @@ -1269,7 +1269,7 @@ static const unsigned alwaysUsedList[] = { Store16, Store32, StoreSingle, StoreDouble, StorePaired, StoreFReg, FDCmpCR, BlockStart, BlockEnd, IdleBranch, BranchCond, BranchUncond, ShortIdleLoop, SystemCall, InterpreterBranch, RFIExit, FPExceptionCheck, - DSIExceptionCheck, ISIException, ExtExceptionCheck, BreakPointCheck, + DSIExceptionCheck, ISIException, BreakPointCheck, Int3, Tramp, Nop }; static const unsigned extra8RegList[] = { diff --git a/Source/Core/Core/Src/PowerPC/Jit64IL/IR.h b/Source/Core/Core/Src/PowerPC/Jit64IL/IR.h index 7fabd946f9..5bc7da9d8d 100644 --- a/Source/Core/Core/Src/PowerPC/Jit64IL/IR.h +++ b/Source/Core/Core/Src/PowerPC/Jit64IL/IR.h @@ -168,7 +168,7 @@ enum Opcode { // used for exception checking, at least until someone // has a better idea of integrating it FPExceptionCheck, DSIExceptionCheck, - ISIException, ExtExceptionCheck, BreakPointCheck, + ISIException, BreakPointCheck, // "Opcode" representing a register too far away to // reference directly; this is a size optimization Tramp, @@ -411,9 +411,6 @@ public: InstLoc EmitISIException(InstLoc dest) { return EmitUOp(ISIException, dest); } - InstLoc EmitExtExceptionCheck(InstLoc pc) { - return EmitUOp(ExtExceptionCheck, pc); - } InstLoc EmitBreakPointCheck(InstLoc pc) { return EmitUOp(BreakPointCheck, pc); } diff --git a/Source/Core/Core/Src/PowerPC/Jit64IL/IR_X86.cpp b/Source/Core/Core/Src/PowerPC/Jit64IL/IR_X86.cpp index 7c12d613a3..88d815e33d 100644 --- a/Source/Core/Core/Src/PowerPC/Jit64IL/IR_X86.cpp +++ b/Source/Core/Core/Src/PowerPC/Jit64IL/IR_X86.cpp @@ -762,7 +762,6 @@ static void DoWriteCode(IRBuilder* ibuild, JitIL* Jit, bool UseProfile, bool Mak case FPExceptionCheck: case DSIExceptionCheck: case ISIException: - case ExtExceptionCheck: case BreakPointCheck: case Int3: case Tramp: @@ -1941,27 +1940,6 @@ static void DoWriteCode(IRBuilder* ibuild, JitIL* Jit, bool UseProfile, bool Mak Jit->WriteExceptionExit(); break; } - case ExtExceptionCheck: { - unsigned InstLoc = ibuild->GetImmValue(getOp1(I)); - - Jit->TEST(32, M((void *)&PowerPC::ppcState.Exceptions), Imm32(EXCEPTION_ISI | EXCEPTION_PROGRAM | EXCEPTION_SYSCALL | EXCEPTION_FPU_UNAVAILABLE | EXCEPTION_DSI | EXCEPTION_ALIGNMENT)); - FixupBranch clearInt = Jit->J_CC(CC_NZ); - Jit->TEST(32, M((void *)&PowerPC::ppcState.Exceptions), Imm32(EXCEPTION_EXTERNAL_INT)); - FixupBranch noExtException = Jit->J_CC(CC_Z); - Jit->TEST(32, M((void *)&PowerPC::ppcState.msr), Imm32(0x0008000)); - FixupBranch noExtIntEnable = Jit->J_CC(CC_Z); - Jit->TEST(32, M((void *)&ProcessorInterface::m_InterruptCause), Imm32(ProcessorInterface::INT_CAUSE_CP | ProcessorInterface::INT_CAUSE_PE_TOKEN | ProcessorInterface::INT_CAUSE_PE_FINISH)); - FixupBranch noCPInt = Jit->J_CC(CC_Z); - - Jit->MOV(32, M(&PC), Imm32(InstLoc)); - Jit->WriteExceptionExit(); - - Jit->SetJumpTarget(noCPInt); - Jit->SetJumpTarget(noExtIntEnable); - Jit->SetJumpTarget(noExtException); - Jit->SetJumpTarget(clearInt); - break; - } case BreakPointCheck: { unsigned InstLoc = ibuild->GetImmValue(getOp1(I)); diff --git a/Source/Core/Core/Src/PowerPC/Jit64IL/JitIL.cpp b/Source/Core/Core/Src/PowerPC/Jit64IL/JitIL.cpp index a60becfad9..f10df33d99 100644 --- a/Source/Core/Core/Src/PowerPC/Jit64IL/JitIL.cpp +++ b/Source/Core/Core/Src/PowerPC/Jit64IL/JitIL.cpp @@ -679,11 +679,6 @@ const u8* JitIL::DoJit(u32 em_address, PPCAnalyst::CodeBuffer *code_buf, JitBloc ibuild.EmitFPExceptionCheck(ibuild.EmitIntConst(ops[i].address)); } - if (jit->js.fifoWriteAddresses.find(js.compilerPC) != jit->js.fifoWriteAddresses.end()) - { - ibuild.EmitExtExceptionCheck(ibuild.EmitIntConst(ops[i].address)); - } - if (Core::g_CoreStartupParameter.bEnableDebugging && breakpoints.IsAddressBreakPoint(ops[i].address) && GetState() != CPU_STEPPING) { ibuild.EmitBreakPointCheck(ibuild.EmitIntConst(ops[i].address)); diff --git a/Source/Core/Core/Src/PowerPC/JitCommon/JitBase.h b/Source/Core/Core/Src/PowerPC/JitCommon/JitBase.h index 158171be0f..9b8c67474c 100644 --- a/Source/Core/Core/Src/PowerPC/JitCommon/JitBase.h +++ b/Source/Core/Core/Src/PowerPC/JitCommon/JitBase.h @@ -74,8 +74,6 @@ protected: u8* rewriteStart; JitBlock *curBlock; - - std::set fifoWriteAddresses; }; public: