From a68c1bf648a5ecfb7c3d1f99fdb048c9fef6ff90 Mon Sep 17 00:00:00 2001 From: Tillmann Karras Date: Mon, 28 Jun 2021 03:20:22 +0100 Subject: [PATCH] PowerPC: add enum values for emulator SO and LT shifts --- Source/Core/Core/PowerPC/ConditionRegister.h | 10 ++++--- .../Interpreter/Interpreter_Integer.cpp | 3 ++- .../PowerPC/Jit64/Jit_SystemRegisters.cpp | 24 ++++++++--------- .../PowerPC/Jit64Common/Jit64AsmCommon.cpp | 2 +- .../JitArm64/JitArm64_SystemRegisters.cpp | 26 +++++++++---------- 5 files changed, 35 insertions(+), 30 deletions(-) diff --git a/Source/Core/Core/PowerPC/ConditionRegister.h b/Source/Core/Core/PowerPC/ConditionRegister.h index 3a9c7cc4ad..0891e99159 100644 --- a/Source/Core/Core/PowerPC/ConditionRegister.h +++ b/Source/Core/Core/PowerPC/ConditionRegister.h @@ -20,6 +20,9 @@ enum CRBits CR_EQ_BIT = 1, CR_GT_BIT = 2, CR_LT_BIT = 3, + + CR_EMU_SO_BIT = 59, + CR_EMU_LT_BIT = 62, }; // Optimized CR implementation. Instead of storing CR in its PowerPC format @@ -46,10 +49,10 @@ struct ConditionRegister static u64 PPCToInternal(u8 value) { u64 cr_val = 0x100000000; - cr_val |= (u64) !!(value & CR_SO) << 59; + cr_val |= (u64) !!(value & CR_SO) << CR_EMU_SO_BIT; cr_val |= (u64) !(value & CR_EQ); cr_val |= (u64) !(value & CR_GT) << 63; - cr_val |= (u64) !!(value & CR_LT) << 62; + cr_val |= (u64) !!(value & CR_LT) << CR_EMU_LT_BIT; return cr_val; } @@ -64,7 +67,8 @@ struct ConditionRegister u32 ppc_cr = 0; // LT/SO - ppc_cr |= (cr_val >> 59) & (PowerPC::CR_LT | PowerPC::CR_SO); + static_assert(CR_EMU_LT_BIT - CR_EMU_SO_BIT == CR_LT_BIT - CR_SO_BIT); + ppc_cr |= (cr_val >> CR_EMU_SO_BIT) & (PowerPC::CR_LT | PowerPC::CR_SO); // EQ ppc_cr |= ((cr_val & 0xFFFFFFFF) == 0) << PowerPC::CR_EQ_BIT; // GT diff --git a/Source/Core/Core/PowerPC/Interpreter/Interpreter_Integer.cpp b/Source/Core/Core/PowerPC/Interpreter/Interpreter_Integer.cpp index 3b9570efc1..37a79a4fb7 100644 --- a/Source/Core/Core/PowerPC/Interpreter/Interpreter_Integer.cpp +++ b/Source/Core/Core/PowerPC/Interpreter/Interpreter_Integer.cpp @@ -13,7 +13,8 @@ void Interpreter::Helper_UpdateCR0(u32 value) { s64 sign_extended = (s64)(s32)value; u64 cr_val = (u64)sign_extended; - cr_val = (cr_val & ~(1ull << 59)) | ((u64)PowerPC::GetXER_SO() << 59); + cr_val = (cr_val & ~(1ull << PowerPC::CR_EMU_SO_BIT)) | + ((u64)PowerPC::GetXER_SO() << PowerPC::CR_EMU_SO_BIT); PowerPC::ppcState.cr.fields[0] = cr_val; } diff --git a/Source/Core/Core/PowerPC/Jit64/Jit_SystemRegisters.cpp b/Source/Core/Core/PowerPC/Jit64/Jit_SystemRegisters.cpp index 6e40d753ba..91799e9c06 100644 --- a/Source/Core/Core/PowerPC/Jit64/Jit_SystemRegisters.cpp +++ b/Source/Core/Core/PowerPC/Jit64/Jit_SystemRegisters.cpp @@ -25,7 +25,7 @@ void Jit64::GetCRFieldBit(int field, int bit, X64Reg out, bool negate) switch (bit) { case PowerPC::CR_SO_BIT: // check bit 59 set - BT(64, CROffset(field), Imm8(59)); + BT(64, CROffset(field), Imm8(PowerPC::CR_EMU_SO_BIT)); SETcc(negate ? CC_NC : CC_C, R(out)); break; @@ -40,7 +40,7 @@ void Jit64::GetCRFieldBit(int field, int bit, X64Reg out, bool negate) break; case PowerPC::CR_LT_BIT: // check bit 62 set - BT(64, CROffset(field), Imm8(62)); + BT(64, CROffset(field), Imm8(PowerPC::CR_EMU_LT_BIT)); SETcc(negate ? CC_NC : CC_C, R(out)); break; @@ -60,8 +60,8 @@ void Jit64::SetCRFieldBit(int field, int bit, X64Reg in) switch (bit) { case PowerPC::CR_SO_BIT: // set bit 59 to input - BTR(64, R(RSCRATCH2), Imm8(59)); - SHL(64, R(in), Imm8(59)); + BTR(64, R(RSCRATCH2), Imm8(PowerPC::CR_EMU_SO_BIT)); + SHL(64, R(in), Imm8(PowerPC::CR_EMU_SO_BIT)); OR(64, R(RSCRATCH2), R(in)); break; @@ -80,8 +80,8 @@ void Jit64::SetCRFieldBit(int field, int bit, X64Reg in) break; case PowerPC::CR_LT_BIT: // set bit 62 to input - BTR(64, R(RSCRATCH2), Imm8(62)); - SHL(64, R(in), Imm8(62)); + BTR(64, R(RSCRATCH2), Imm8(PowerPC::CR_EMU_LT_BIT)); + SHL(64, R(in), Imm8(PowerPC::CR_EMU_LT_BIT)); OR(64, R(RSCRATCH2), R(in)); break; } @@ -95,7 +95,7 @@ void Jit64::ClearCRFieldBit(int field, int bit) switch (bit) { case PowerPC::CR_SO_BIT: - BTR(64, CROffset(field), Imm8(59)); + BTR(64, CROffset(field), Imm8(PowerPC::CR_EMU_SO_BIT)); break; case PowerPC::CR_EQ_BIT: @@ -110,7 +110,7 @@ void Jit64::ClearCRFieldBit(int field, int bit) break; case PowerPC::CR_LT_BIT: - BTR(64, CROffset(field), Imm8(62)); + BTR(64, CROffset(field), Imm8(PowerPC::CR_EMU_LT_BIT)); break; } // We don't need to set bit 32; the cases where that's needed only come up when setting bits, not @@ -126,7 +126,7 @@ void Jit64::SetCRFieldBit(int field, int bit) switch (bit) { case PowerPC::CR_SO_BIT: - BTS(64, R(RSCRATCH), Imm8(59)); + BTS(64, R(RSCRATCH), Imm8(PowerPC::CR_EMU_SO_BIT)); break; case PowerPC::CR_EQ_BIT: @@ -139,7 +139,7 @@ void Jit64::SetCRFieldBit(int field, int bit) break; case PowerPC::CR_LT_BIT: - BTS(64, R(RSCRATCH), Imm8(62)); + BTS(64, R(RSCRATCH), Imm8(PowerPC::CR_EMU_LT_BIT)); break; } @@ -163,7 +163,7 @@ FixupBranch Jit64::JumpIfCRFieldBit(int field, int bit, bool jump_if_set) switch (bit) { case PowerPC::CR_SO_BIT: // check bit 59 set - BT(64, CROffset(field), Imm8(59)); + BT(64, CROffset(field), Imm8(PowerPC::CR_EMU_SO_BIT)); return J_CC(jump_if_set ? CC_C : CC_NC, true); case PowerPC::CR_EQ_BIT: // check bits 31-0 == 0 @@ -175,7 +175,7 @@ FixupBranch Jit64::JumpIfCRFieldBit(int field, int bit, bool jump_if_set) return J_CC(jump_if_set ? CC_G : CC_LE, true); case PowerPC::CR_LT_BIT: // check bit 62 set - BT(64, CROffset(field), Imm8(62)); + BT(64, CROffset(field), Imm8(PowerPC::CR_EMU_LT_BIT)); return J_CC(jump_if_set ? CC_C : CC_NC, true); default: diff --git a/Source/Core/Core/PowerPC/Jit64Common/Jit64AsmCommon.cpp b/Source/Core/Core/PowerPC/Jit64Common/Jit64AsmCommon.cpp index 71cf960cb3..f86d928d90 100644 --- a/Source/Core/Core/PowerPC/Jit64Common/Jit64AsmCommon.cpp +++ b/Source/Core/Core/PowerPC/Jit64Common/Jit64AsmCommon.cpp @@ -322,7 +322,7 @@ void CommonAsmRoutines::GenMfcr() // SO: Bit 59 set; set flag bit 0 // LT: Bit 62 set; set flag bit 3 - SHR(64, R(cr_val), Imm8(59)); + SHR(64, R(cr_val), Imm8(PowerPC::CR_EMU_SO_BIT)); AND(32, R(cr_val), Imm8(PowerPC::CR_LT | PowerPC::CR_SO)); OR(32, R(dst), R(cr_val)); } diff --git a/Source/Core/Core/PowerPC/JitArm64/JitArm64_SystemRegisters.cpp b/Source/Core/Core/PowerPC/JitArm64/JitArm64_SystemRegisters.cpp index ddb8cb337d..e81004abe7 100644 --- a/Source/Core/Core/PowerPC/JitArm64/JitArm64_SystemRegisters.cpp +++ b/Source/Core/Core/PowerPC/JitArm64/JitArm64_SystemRegisters.cpp @@ -22,14 +22,14 @@ FixupBranch JitArm64::JumpIfCRFieldBit(int field, int bit, bool jump_if_set) switch (bit) { case PowerPC::CR_SO_BIT: // check bit 59 set - return jump_if_set ? TBNZ(XA, 59) : TBZ(XA, 59); + return jump_if_set ? TBNZ(XA, PowerPC::CR_EMU_SO_BIT) : TBZ(XA, PowerPC::CR_EMU_SO_BIT); case PowerPC::CR_EQ_BIT: // check bits 31-0 == 0 return jump_if_set ? CBZ(WA) : CBNZ(WA); case PowerPC::CR_GT_BIT: // check val > 0 CMP(XA, ARM64Reg::SP); return B(jump_if_set ? CC_GT : CC_LE); case PowerPC::CR_LT_BIT: // check bit 62 set - return jump_if_set ? TBNZ(XA, 62) : TBZ(XA, 62); + return jump_if_set ? TBNZ(XA, PowerPC::CR_EMU_LT_BIT) : TBZ(XA, PowerPC::CR_EMU_LT_BIT); default: ASSERT_MSG(DYNA_REC, false, "Invalid CR bit"); return {}; @@ -441,7 +441,7 @@ void JitArm64::crXXX(UGeckoInstruction inst) switch (bit) { case PowerPC::CR_SO_BIT: - ANDI2R(XA, XA, ~(u64(1) << 59)); + ANDI2R(XA, XA, ~(u64(1) << PowerPC::CR_EMU_SO_BIT)); break; case PowerPC::CR_EQ_BIT: @@ -454,7 +454,7 @@ void JitArm64::crXXX(UGeckoInstruction inst) break; case PowerPC::CR_LT_BIT: - ANDI2R(XA, XA, ~(u64(1) << 62)); + ANDI2R(XA, XA, ~(u64(1) << PowerPC::CR_EMU_LT_BIT)); break; } return; @@ -476,7 +476,7 @@ void JitArm64::crXXX(UGeckoInstruction inst) switch (bit) { case PowerPC::CR_SO_BIT: - ORRI2R(XA, XA, u64(1) << 59); + ORRI2R(XA, XA, u64(1) << PowerPC::CR_EMU_SO_BIT); break; case PowerPC::CR_EQ_BIT: @@ -488,7 +488,7 @@ void JitArm64::crXXX(UGeckoInstruction inst) break; case PowerPC::CR_LT_BIT: - ORRI2R(XA, XA, u64(1) << 62); + ORRI2R(XA, XA, u64(1) << PowerPC::CR_EMU_LT_BIT); break; } @@ -520,7 +520,7 @@ void JitArm64::crXXX(UGeckoInstruction inst) switch (bit) { case PowerPC::CR_SO_BIT: // check bit 59 set - UBFX(out, XC, 59, 1); + UBFX(out, XC, PowerPC::CR_EMU_SO_BIT, 1); if (negate) EOR(out, out, 0, 0, true); // XC ^ 1 break; @@ -536,7 +536,7 @@ void JitArm64::crXXX(UGeckoInstruction inst) break; case PowerPC::CR_LT_BIT: // check bit 62 set - UBFX(out, XC, 62, 1); + UBFX(out, XC, PowerPC::CR_EMU_LT_BIT, 1); if (negate) EOR(out, out, 0, 0, true); // XC ^ 1 break; @@ -582,7 +582,7 @@ void JitArm64::crXXX(UGeckoInstruction inst) switch (bit) { case PowerPC::CR_SO_BIT: // set bit 59 to input - BFI(XB, XA, 59, 1); + BFI(XB, XA, PowerPC::CR_EMU_SO_BIT, 1); break; case PowerPC::CR_EQ_BIT: // clear low 32 bits, set bit 0 to !input @@ -597,7 +597,7 @@ void JitArm64::crXXX(UGeckoInstruction inst) break; case PowerPC::CR_LT_BIT: // set bit 62 to input - BFI(XB, XA, 62, 1); + BFI(XB, XA, PowerPC::CR_EMU_LT_BIT, 1); break; } @@ -625,11 +625,11 @@ void JitArm64::mfcr(UGeckoInstruction inst) // SO if (i == 0) { - UBFX(XA, CR, 59, 1); + UBFX(XA, CR, PowerPC::CR_EMU_SO_BIT, 1); } else { - UBFX(XC, CR, 59, 1); + UBFX(XC, CR, PowerPC::CR_EMU_SO_BIT, 1); ORR(XA, XC, XA, ArithOption(XA, ShiftType::LSL, 4)); } @@ -644,7 +644,7 @@ void JitArm64::mfcr(UGeckoInstruction inst) CSEL(WA, WC, WA, CC_GT); // LT - UBFX(XC, CR, 62, 1); + UBFX(XC, CR, PowerPC::CR_EMU_LT_BIT, 1); ORR(WA, WA, WC, ArithOption(WC, ShiftType::LSL, 3)); }