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Merge pull request #9817 from Sintendo/jit64subfic

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Jit64: subfic - Optimize constants for d != a
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Markus Wick 2021-06-17 09:12:50 +02:00 committed by GitHub
commit b530d9b8c2
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1 changed files with 24 additions and 21 deletions
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45
Source/Core/Core/PowerPC/Jit64/Jit_Integer.cpp
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@ -898,28 +898,31 @@ void Jit64::subfic(UGeckoInstruction inst)
RCX64Reg Rd = gpr.Bind(d, RCMode::Write); RCX64Reg Rd = gpr.Bind(d, RCMode::Write);
RegCache::Realize(Ra, Rd); RegCache::Realize(Ra, Rd);
if (d == a) if (imm == 0)
{ {
if (imm == 0) if (d != a)
{ MOV(32, Rd, Ra);
// Flags act exactly like subtracting from 0
NEG(32, Rd); // Flags act exactly like subtracting from 0
// Output carry is inverted NEG(32, Rd);
FinalizeCarry(CC_NC); // Output carry is inverted
} FinalizeCarry(CC_NC);
else if (imm == -1) }
{ else if (imm == -1)
NOT(32, Rd); {
// CA is always set in this case if (d != a)
FinalizeCarry(true); MOV(32, Rd, Ra);
}
else NOT(32, Rd);
{ // CA is always set in this case
NOT(32, Rd); FinalizeCarry(true);
ADD(32, Rd, Imm32(imm + 1)); }
// Output carry is normal else if (d == a)
FinalizeCarry(CC_C); {
} NOT(32, Rd);
ADD(32, Rd, Imm32(imm + 1));
// Output carry is normal
FinalizeCarry(CC_C);
} }
else else
{ {