diff --git a/Source/UnitTests/Common/x64EmitterTest.cpp b/Source/UnitTests/Common/x64EmitterTest.cpp
index ff0c64b876..020e53afa2 100644
--- a/Source/UnitTests/Common/x64EmitterTest.cpp
+++ b/Source/UnitTests/Common/x64EmitterTest.cpp
@@ -882,9 +882,27 @@ TWO_OP_SSE_TEST(PMOVZXWD, "qword")
 TWO_OP_SSE_TEST(PMOVZXWQ, "dword")
 TWO_OP_SSE_TEST(PMOVZXDQ, "qword")
 
-// TODO: BLEND
+TWO_OP_SSE_TEST(PBLENDVB, "dqword")
+TWO_OP_SSE_TEST(BLENDVPS, "dqword")
+TWO_OP_SSE_TEST(BLENDVPD, "dqword")
 
-// TODO: AVX
+#define TWO_OP_PLUS_IMM_SSE_TEST(Name, MemBits)                                                    \
+  TEST_F(x64EmitterTest, Name)                                                                     \
+  {                                                                                                \
+    for (const auto& r1 : xmmnames)                                                                \
+    {                                                                                              \
+      for (const auto& r2 : xmmnames)                                                              \
+      {                                                                                            \
+        emitter->Name(r1.reg, R(r2.reg), 0x0b);                                                    \
+        ExpectDisassembly(#Name " " + r1.name + ", " + r2.name + ", 0x0b");                        \
+      }                                                                                            \
+      emitter->Name(r1.reg, MatR(R12), 0x0b);                                                      \
+      ExpectDisassembly(#Name " " + r1.name + ", " MemBits " ptr ds:[r12], 0x0b");                 \
+    }                                                                                              \
+  }
+
+TWO_OP_PLUS_IMM_SSE_TEST(BLENDPS, "dqword")
+TWO_OP_PLUS_IMM_SSE_TEST(BLENDPD, "dqword")
 
 // for VEX GPR instructions that take the form op reg, r/m, reg
 #define VEX_RMR_TEST(Name)                                                                         \
@@ -1035,6 +1053,26 @@ VEX_RMI_TEST(RORX)
       }                                                                                            \
   }
 
+AVX_RRM_TEST(VADDSS, "dword")
+AVX_RRM_TEST(VSUBSS, "dword")
+AVX_RRM_TEST(VMULSS, "dword")
+AVX_RRM_TEST(VDIVSS, "dword")
+AVX_RRM_TEST(VADDPS, "dqword")
+AVX_RRM_TEST(VSUBPS, "dqword")
+AVX_RRM_TEST(VMULPS, "dqword")
+AVX_RRM_TEST(VDIVPS, "dqword")
+AVX_RRM_TEST(VADDSD, "qword")
+AVX_RRM_TEST(VSUBSD, "qword")
+AVX_RRM_TEST(VMULSD, "qword")
+AVX_RRM_TEST(VDIVSD, "qword")
+AVX_RRM_TEST(VADDPD, "dqword")
+AVX_RRM_TEST(VSUBPD, "dqword")
+AVX_RRM_TEST(VMULPD, "dqword")
+AVX_RRM_TEST(VDIVPD, "dqword")
+AVX_RRM_TEST(VSQRTSD, "qword")
+AVX_RRM_TEST(VUNPCKLPS, "dqword")
+AVX_RRM_TEST(VUNPCKLPD, "dqword")
+AVX_RRM_TEST(VUNPCKHPD, "dqword")
 AVX_RRM_TEST(VANDPS, "dqword")
 AVX_RRM_TEST(VANDPD, "dqword")
 AVX_RRM_TEST(VANDNPS, "dqword")
@@ -1067,6 +1105,31 @@ FMA3_TEST(VFNMSUB, S, false)
 FMA3_TEST(VFMADDSUB, P, true)
 FMA3_TEST(VFMSUBADD, P, true)
 
+#define AVX_RRMI_TEST(Name, MemBits)                                                               \
+  TEST_F(x64EmitterTest, Name)                                                                     \
+  {                                                                                                \
+    for (const auto& r1 : xmmnames)                                                                \
+    {                                                                                              \
+      for (const auto& r2 : xmmnames)                                                              \
+      {                                                                                            \
+        for (const auto& r3 : xmmnames)                                                            \
+        {                                                                                          \
+          emitter->Name(r1.reg, r2.reg, R(r3.reg), 0x0b);                                          \
+          ExpectDisassembly(#Name " " + r1.name + ", " + r2.name + ", " + r3.name + ", 0x0b");     \
+        }                                                                                          \
+        emitter->Name(r1.reg, r2.reg, MatR(R12), 0x0b);                                            \
+        ExpectDisassembly(#Name " " + r1.name + ", " + r2.name +                                   \
+                          ", " MemBits " ptr ds:[r12], 0x0b");                                     \
+      }                                                                                            \
+    }                                                                                              \
+  }
+
+AVX_RRMI_TEST(VCMPPD, "dqword")
+AVX_RRMI_TEST(VSHUFPS, "dqword")
+AVX_RRMI_TEST(VSHUFPD, "dqword")
+AVX_RRMI_TEST(VBLENDPS, "dqword")
+AVX_RRMI_TEST(VBLENDPD, "dqword")
+
 // for VEX instructions that take the form op reg, reg, r/m, reg OR reg, reg, reg, r/m
 #define VEX_RRMR_RRRM_TEST(Name, sizename)                                                         \
   TEST_F(x64EmitterTest, Name)                                                                     \