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9db0ebd4b6
Not doing this can cause desyncs when TASing. (I don't know how common such desyncs would be, though. For games that don't change rounding modes, they shouldn't be a problem.)
96 lines
2.5 KiB
C++
96 lines
2.5 KiB
C++
// Copyright 2021 Dolphin Emulator Project
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// Licensed under GPLv2+
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// Refer to the license.txt file included.
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#include "Common/CPUDetect.h"
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#include "Common/CommonTypes.h"
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#include "Common/FPURoundMode.h"
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#include "Common/Logging/Log.h"
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#ifdef _MSC_VER
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#include <intrin.h>
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#endif
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static u64 GetFPCR()
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{
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#ifdef _MSC_VER
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return _ReadStatusReg(ARM64_FPCR);
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#else
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u64 fpcr;
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__asm__ __volatile__("mrs %0, fpcr" : "=r"(fpcr));
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return fpcr;
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#endif
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}
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static void SetFPCR(u64 fpcr)
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{
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#ifdef _MSC_VER
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_WriteStatusReg(ARM64_FPCR, fpcr);
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#else
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__asm__ __volatile__("msr fpcr, %0" : : "ri"(fpcr));
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#endif
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}
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namespace FPURoundMode
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{
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static const u64 default_fpcr = GetFPCR();
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static u64 saved_fpcr = default_fpcr;
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void SetRoundMode(int mode)
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{
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// We don't need to do anything here since SetSIMDMode is always called after calling this
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}
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void SetSIMDMode(int rounding_mode, bool non_ieee_mode)
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{
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// When AH is disabled, FZ controls flush-to-zero for both inputs and outputs. When AH is enabled,
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// FZ controls flush-to-zero for outputs, and FIZ controls flush-to-zero for inputs.
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constexpr u32 FZ = 1 << 24;
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constexpr u32 AH = 1 << 1;
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constexpr u32 FIZ = 1 << 0;
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constexpr u32 flush_to_zero_mask = FZ | AH | FIZ;
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// On CPUs with FEAT_AFP support, setting AH = 1, FZ = 1, FIZ = 0 emulates the GC/Wii CPU's
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// "non-IEEE mode". Unfortunately, FEAT_AFP didn't exist until 2020, so we can't count on setting
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// AH actually doing anything. But flushing both inputs and outputs seems to cause less problems
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// than flushing nothing, so let's just set FZ and AH and roll with whatever behavior we get.
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const u32 flush_to_zero_bits = (non_ieee_mode ? FZ | AH : 0);
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static bool afp_warning_shown = false;
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if (!afp_warning_shown && !cpu_info.bAFP && non_ieee_mode)
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{
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afp_warning_shown = true;
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WARN_LOG_FMT(POWERPC,
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"Non-IEEE mode was requested, but host CPU is not known to support FEAT_AFP");
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}
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// lookup table for FPSCR.RN-to-FPCR.RMode translation
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constexpr u32 rounding_mode_table[] = {
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(0 << 22), // nearest
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(3 << 22), // zero
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(1 << 22), // +inf
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(2 << 22), // -inf
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};
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constexpr u32 rounding_mode_mask = 3 << 22;
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const u32 rounding_mode_bits = rounding_mode_table[rounding_mode];
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const u64 base = default_fpcr & ~(flush_to_zero_mask | rounding_mode_mask);
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SetFPCR(base | rounding_mode_bits | flush_to_zero_bits);
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}
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void SaveSIMDState()
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{
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saved_fpcr = GetFPCR();
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}
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void LoadSIMDState()
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{
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SetFPCR(saved_fpcr);
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}
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void LoadDefaultSIMDState()
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{
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SetFPCR(default_fpcr);
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}
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} // namespace FPURoundMode
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