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https://github.com/dolphin-emu/dolphin.git
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775dc8a9c0
git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@4 8ced0084-cf51-0410-be5f-012b33b47a6e
509 lines
15 KiB
C++
509 lines
15 KiB
C++
#ifndef _BX_DISASM_H_
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#define _BX_DISASM_H_
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#include "config.h"
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#define BX_DECODE_MODRM(modrm_byte, mod, opcode, rm) { \
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mod = (modrm_byte >> 6) & 0x03; \
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opcode = (modrm_byte >> 3) & 0x07; \
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rm = modrm_byte & 0x07; \
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}
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#define BX_DECODE_SIB(sib_byte, scale, index, base) { \
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scale = sib_byte >> 6; \
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index = (sib_byte >> 3) & 0x07; \
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base = sib_byte & 0x07; \
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}
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// will be used in future
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#define IA_286 0x00000001 /* 286+ instruction */
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#define IA_386 0x00000002 /* 386+ instruction */
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#define IA_486 0x00000004 /* 486+ instruction */
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#define IA_PENTIUM 0x00000008 /* Pentium+ instruction */
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#define IA_P6 0x00000010 /* P6 new instruction */
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#define IA_SYSTEM 0x00000020 /* system instruction (require CPL=0) */
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#define IA_LEGACY 0x00000040 /* legacy instruction */
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#define IA_X87 0x00000080 /* FPU (X87) instruction */
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#define IA_MMX 0x00000100 /* MMX instruction */
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#define IA_3DNOW 0x00000200 /* 3DNow! instruction */
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#define IA_PREFETCH 0x00000400 /* Prefetch instruction */
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#define IA_SSE 0x00000800 /* SSE instruction */
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#define IA_SSE2 0x00001000 /* SSE2 instruction */
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#define IA_SSE3 0x00002000 /* SSE3 instruction */
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#define IA_SSE4 0x00004000 /* SSE4 instruction */
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#define IA_X86_64 0x00008000 /* x86-64 instruction */
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/* general purpose bit register */
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enum {
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rAX_REG,
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rCX_REG,
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rDX_REG,
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rBX_REG,
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rSP_REG,
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rBP_REG,
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rSI_REG,
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rDI_REG
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};
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/* segment register */
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enum {
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ES_REG,
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CS_REG,
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SS_REG,
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DS_REG,
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FS_REG,
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GS_REG,
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INVALID_SEG1,
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INVALID_SEG2
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};
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class disassembler;
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struct x86_insn;
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typedef void (disassembler::*BxDisasmPtr_t)(const x86_insn *insn);
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typedef void (disassembler::*BxDisasmResolveModrmPtr_t)(const x86_insn *insn, unsigned attr);
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struct BxDisasmOpcodeInfo_t
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{
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const char *IntelOpcode;
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const char *AttOpcode;
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BxDisasmPtr_t Operand1;
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BxDisasmPtr_t Operand2;
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BxDisasmPtr_t Operand3;
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};
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struct BxDisasmOpcodeTable_t
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{
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Bit32u Attr;
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const void *OpcodeInfo;
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};
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// segment override not used
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#define NO_SEG_OVERRIDE 0xFF
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// datasize attributes
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#define X_SIZE 0x0000
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#define B_SIZE 0x0100
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#define W_SIZE 0x0200
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#define D_SIZE 0x0300
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#define Q_SIZE 0x0400
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#define Z_SIZE 0x0500
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#define V_SIZE 0x0600
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#define O_SIZE 0x0700
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#define T_SIZE 0x0800
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#define P_SIZE 0x0900
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// branch hint attribute
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#define BRANCH_HINT 0x1000
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struct x86_insn
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{
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public:
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x86_insn(bx_bool is32, bx_bool is64);
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bx_bool is_seg_override() const {
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return (seg_override != NO_SEG_OVERRIDE);
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}
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public:
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bx_bool is_32, is_64;
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bx_bool as_32, as_64;
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bx_bool os_32, os_64;
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Bit8u extend8b;
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Bit8u rex_r, rex_x, rex_b;
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Bit8u seg_override;
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unsigned b1, prefixes;
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unsigned ilen;
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Bit8u modrm, mod, nnn, rm;
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Bit8u sib, scale, index, base;
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union {
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Bit16u displ16;
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Bit32u displ32;
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} displacement;
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};
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BX_CPP_INLINE x86_insn::x86_insn(bx_bool is32, bx_bool is64)
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{
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is_32 = is32;
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is_64 = is64;
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if (is_64) {
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os_64 = 0;
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as_64 = 1;
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os_32 = 1;
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as_32 = 1;
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}
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else {
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os_64 = 0;
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as_64 = 0;
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os_32 = is_32;
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as_32 = is_32;
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}
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extend8b = 0;
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rex_r = rex_b = rex_x = 0;
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seg_override = NO_SEG_OVERRIDE;
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prefixes = 0;
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ilen = 0;
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b1 = 0;
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modrm = mod = nnn = rm = 0;
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sib = scale = index = base = 0;
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displacement.displ32 = 0;
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}
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class disassembler {
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public:
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disassembler() { set_syntax_intel(); }
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unsigned disasm(bx_bool is_32, bx_bool is_64, bx_address base, bx_address ip, const Bit8u *instr, char *disbuf);
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unsigned disasm16(bx_address base, bx_address ip, const Bit8u *instr, char *disbuf)
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{ return disasm(0, 0, base, ip, instr, disbuf); }
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unsigned disasm32(bx_address base, bx_address ip, const Bit8u *instr, char *disbuf)
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{ return disasm(1, 0, base, ip, instr, disbuf); }
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unsigned disasm64(bx_address base, bx_address ip, const Bit8u *instr, char *disbuf)
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{ return disasm(1, 1, base, ip, instr, disbuf); }
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x86_insn decode(bx_bool is_32, bx_bool is_64, bx_address base, bx_address ip, const Bit8u *instr, char *disbuf);
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x86_insn decode16(bx_address base, bx_address ip, const Bit8u *instr, char *disbuf)
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{ return decode(0, 0, base, ip, instr, disbuf); }
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x86_insn decode32(bx_address base, bx_address ip, const Bit8u *instr, char *disbuf)
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{ return decode(1, 0, base, ip, instr, disbuf); }
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x86_insn decode64(bx_address base, bx_address ip, const Bit8u *instr, char *disbuf)
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{ return decode(1, 1, base, ip, instr, disbuf); }
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void set_syntax_intel();
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void set_syntax_att ();
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void toggle_syntax_mode();
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private:
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bx_bool intel_mode;
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const char **general_16bit_regname;
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const char **general_8bit_regname;
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const char **general_32bit_regname;
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const char **general_8bit_regname_rex;
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const char **general_64bit_regname;
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const char **segment_name;
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const char **index16;
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const char *sreg_mod01or10_rm32[8];
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const char *sreg_mod00_base32[8];
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const char *sreg_mod01or10_base32[8];
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const char *sreg_mod00_rm16[8];
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const char *sreg_mod01or10_rm16[8];
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private:
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bx_address db_eip, db_base;
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const Bit8u *instruction; // for fetching of next byte of instruction
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char *disbufptr;
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BxDisasmResolveModrmPtr_t resolve_modrm;
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BX_CPP_INLINE Bit8u fetch_byte() {
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db_eip++;
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return(*instruction++);
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};
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BX_CPP_INLINE Bit8u peek_byte() {
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return(*instruction);
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};
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BX_CPP_INLINE Bit16u fetch_word() {
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Bit8u b0 = * (Bit8u *) instruction++;
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Bit8u b1 = * (Bit8u *) instruction++;
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Bit16u ret16 = (b1<<8) | b0;
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db_eip += 2;
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return(ret16);
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};
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BX_CPP_INLINE Bit32u fetch_dword() {
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Bit8u b0 = * (Bit8u *) instruction++;
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Bit8u b1 = * (Bit8u *) instruction++;
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Bit8u b2 = * (Bit8u *) instruction++;
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Bit8u b3 = * (Bit8u *) instruction++;
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Bit32u ret32 = (b3<<24) | (b2<<16) | (b1<<8) | b0;
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db_eip += 4;
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return(ret32);
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};
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BX_CPP_INLINE Bit64u fetch_qword() {
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Bit64u d0 = fetch_dword();
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Bit64u d1 = fetch_dword();
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Bit64u ret64 = (d1<<32) | d0;
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return(ret64);
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};
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void dis_putc(char symbol);
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void dis_sprintf(const char *fmt, ...);
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void decode_modrm(x86_insn *insn);
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void resolve16_mod0 (const x86_insn *insn, unsigned mode);
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void resolve16_mod1or2(const x86_insn *insn, unsigned mode);
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void resolve32_mod0 (const x86_insn *insn, unsigned mode);
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void resolve32_mod1or2(const x86_insn *insn, unsigned mode);
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void resolve32_mod0_rm4 (const x86_insn *insn, unsigned mode);
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void resolve32_mod1or2_rm4(const x86_insn *insn, unsigned mode);
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void resolve64_mod0 (const x86_insn *insn, unsigned mode);
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void resolve64_mod1or2(const x86_insn *insn, unsigned mode);
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void resolve64_mod0_rm4 (const x86_insn *insn, unsigned mode);
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void resolve64_mod1or2_rm4(const x86_insn *insn, unsigned mode);
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void initialize_modrm_segregs();
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void print_datasize (unsigned mode);
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void print_memory_access16(int datasize,
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const char *seg, const char *index, Bit16u disp);
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void print_memory_access (int datasize,
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const char *seg, const char *base, const char *index, int scale, Bit32u disp);
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void print_disassembly_intel(const x86_insn *insn, const BxDisasmOpcodeInfo_t *entry);
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void print_disassembly_att (const x86_insn *insn, const BxDisasmOpcodeInfo_t *entry);
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public:
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/*
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* Codes for Addressing Method:
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* ---------------------------
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* A - Direct address. The instruction has no ModR/M byte; the address
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* of the operand is encoded in the instruction; and no base register,
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* index register, or scaling factor can be applied.
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* C - The reg field of the ModR/M byte selects a control register.
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* D - The reg field of the ModR/M byte selects a debug register.
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* E - A ModR/M byte follows the opcode and specifies the operand. The
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* operand is either a general-purpose register or a memory address.
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* If it is a memory address, the address is computed from a segment
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* register and any of the following values: a base register, an
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* index register, a scaling factor, a displacement.
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* F - Flags Register.
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* G - The reg field of the ModR/M byte selects a general register.
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* I - Immediate data. The operand value is encoded in subsequent bytes of
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* the instruction.
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* J - The instruction contains a relative offset to be added to the
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* instruction pointer register.
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* M - The ModR/M byte may refer only to memory.
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* N - The R/M field of the ModR/M byte selects a packed-quadword MMX
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technology register.
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* O - The instruction has no ModR/M byte; the offset of the operand is
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* coded as a word or double word (depending on address size attribute)
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* in the instruction. No base register, index register, or scaling
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* factor can be applied.
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* P - The reg field of the ModR/M byte selects a packed quadword MMX
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* technology register.
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* Q - A ModR/M byte follows the opcode and specifies the operand. The
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* operand is either an MMX technology register or a memory address.
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* If it is a memory address, the address is computed from a segment
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* register and any of the following values: a base register, an
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* index register, a scaling factor, and a displacement.
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* R - The mod field of the ModR/M byte may refer only to a general register.
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* S - The reg field of the ModR/M byte selects a segment register.
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* U - The R/M field of the ModR/M byte selects a 128-bit XMM register.
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* T - The reg field of the ModR/M byte selects a test register.
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* V - The reg field of the ModR/M byte selects a 128-bit XMM register.
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* W - A ModR/M byte follows the opcode and specifies the operand. The
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* operand is either a 128-bit XMM register or a memory address. If
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* it is a memory address, the address is computed from a segment
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* register and any of the following values: a base register, an
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* index register, a scaling factor, and a displacement.
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* X - Memory addressed by the DS:rSI register pair.
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* Y - Memory addressed by the ES:rDI register pair.
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*/
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/*
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* Codes for Operand Type:
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* ----------------------
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* a - Two one-word operands in memory or two double-word operands in
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* memory, depending on operand-size attribute (used only by the BOUND
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* instruction).
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* b - Byte, regardless of operand-size attribute.
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* d - Doubleword, regardless of operand-size attribute.
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* dq - Double-quadword, regardless of operand-size attribute.
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* p - 32-bit or 48-bit pointer, depending on operand-size attribute.
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* pd - 128-bit packed double-precision floating-point data.
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* pi - Quadword MMX technology register (packed integer)
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* ps - 128-bit packed single-precision floating-point data.
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* q - Quadword, regardless of operand-size attribute.
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* s - 6-byte or 10-byte pseudo-descriptor.
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* si - Doubleword integer register (scalar integer)
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* ss - Scalar element of a 128-bit packed single-precision floating data.
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* sd - Scalar element of a 128-bit packed double-precision floating data.
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* v - Word, doubleword or quadword, depending on operand-size attribute.
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* w - Word, regardless of operand-size attr.
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*/
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// far call/jmp
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void Apw(const x86_insn *insn);
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void Apd(const x86_insn *insn);
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// 8-bit general purpose registers
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void AL(const x86_insn *insn);
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void CL(const x86_insn *insn);
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// 16-bit general purpose registers
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void AX(const x86_insn *insn);
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void DX(const x86_insn *insn);
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// 32-bit general purpose registers
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void EAX(const x86_insn *insn);
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// 64-bit general purpose registers
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void RAX(const x86_insn *insn);
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// segment registers
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void CS(const x86_insn *insn);
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void DS(const x86_insn *insn);
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void ES(const x86_insn *insn);
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void SS(const x86_insn *insn);
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void FS(const x86_insn *insn);
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void GS(const x86_insn *insn);
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// segment registers
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void Sw(const x86_insn *insn);
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// test registers
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void Td(const x86_insn *insn);
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// control register
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void Cd(const x86_insn *insn);
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void Cq(const x86_insn *insn);
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// debug register
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void Dd(const x86_insn *insn);
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void Dq(const x86_insn *insn);
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// 8-bit general purpose register
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void R8(const x86_insn *insn);
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// 16-bit general purpose register
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void RX(const x86_insn *insn);
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// 32-bit general purpose register
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void ERX(const x86_insn *insn);
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// 64-bit general purpose register
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void RRX(const x86_insn *insn);
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// general purpose register or memory operand
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void Eb(const x86_insn *insn);
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void Ew(const x86_insn *insn);
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void Ed(const x86_insn *insn);
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void Eq(const x86_insn *insn);
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// general purpose register
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void Gb(const x86_insn *insn);
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void Gw(const x86_insn *insn);
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void Gd(const x86_insn *insn);
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void Gq(const x86_insn *insn);
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// immediate
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void I1(const x86_insn *insn);
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void Ib(const x86_insn *insn);
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void Iw(const x86_insn *insn);
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void Id(const x86_insn *insn);
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void Iq(const x86_insn *insn);
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// two immediates Iw/Ib
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void IwIb(const x86_insn *insn);
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// sign extended immediate
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void sIbw(const x86_insn *insn);
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void sIbd(const x86_insn *insn);
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void sIbq(const x86_insn *insn);
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void sIdq(const x86_insn *insn);
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// floating point
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void ST0(const x86_insn *insn);
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void STi(const x86_insn *insn);
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// general purpose register
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void Rw(const x86_insn *insn);
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void Rd(const x86_insn *insn);
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void Rq(const x86_insn *insn);
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// mmx register
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void Pq(const x86_insn *insn);
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// mmx register or memory operand
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void Qd(const x86_insn *insn);
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void Qq(const x86_insn *insn);
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void Vq(const x86_insn *insn);
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void Nq(const x86_insn *insn);
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// xmm register
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void Udq(const x86_insn *insn);
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void Vdq(const x86_insn *insn);
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void Vss(const x86_insn *insn);
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void Vsd(const x86_insn *insn);
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void Vps(const x86_insn *insn);
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void Vpd(const x86_insn *insn);
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// xmm register or memory operand
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void Wq(const x86_insn *insn);
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void Wdq(const x86_insn *insn);
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void Wss(const x86_insn *insn);
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void Wsd(const x86_insn *insn);
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void Wps(const x86_insn *insn);
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void Wpd(const x86_insn *insn);
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// direct memory access
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void OP_O(const x86_insn *insn, unsigned size);
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void Ob(const x86_insn *insn);
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void Ow(const x86_insn *insn);
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void Od(const x86_insn *insn);
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void Oq(const x86_insn *insn);
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// memory operand
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void OP_M(const x86_insn *insn, unsigned size);
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void Ma(const x86_insn *insn);
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void Mp(const x86_insn *insn);
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void Ms(const x86_insn *insn);
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void Mx(const x86_insn *insn);
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void Mb(const x86_insn *insn);
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void Mw(const x86_insn *insn);
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void Md(const x86_insn *insn);
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void Mq(const x86_insn *insn);
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void Mt(const x86_insn *insn);
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void Mdq(const x86_insn *insn);
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void Mps(const x86_insn *insn);
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void Mpd(const x86_insn *insn);
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// string instructions
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void OP_X(const x86_insn *insn, unsigned size);
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void Xb(const x86_insn *insn);
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void Xw(const x86_insn *insn);
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void Xd(const x86_insn *insn);
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void Xq(const x86_insn *insn);
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// string instructions
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void OP_Y(const x86_insn *insn, unsigned size);
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void Yb(const x86_insn *insn);
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void Yw(const x86_insn *insn);
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void Yd(const x86_insn *insn);
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void Yq(const x86_insn *insn);
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// jump offset
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void Jb(const x86_insn *insn);
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void Jw(const x86_insn *insn);
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void Jd(const x86_insn *insn);
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};
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#endif
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