From 0b90941d4d4ede13e5d0c016e12e92014b8a9185 Mon Sep 17 00:00:00 2001 From: Pierre Bourdon Date: Sat, 13 Dec 2014 04:27:07 +0100 Subject: [PATCH] Pull in CMPAR disassembly fix from Dolphin. The two operand register selection bits were swapped for that instruction. For example, "CMPAR AC1, AX0.H" would be disassembled as "CMPAR AC0, AX1.H", leading to pain and confusion. --- gcdsp_generated.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcdsp_generated.py b/gcdsp_generated.py index 835ba91..155a341 100644 --- a/gcdsp_generated.py +++ b/gcdsp_generated.py @@ -199,7 +199,7 @@ opcodes = [ ["MULXMV",0xa600,0xe600,1,3,[[OpType.REGM18,1,0,11,0x1000],[OpType.REGM19,1,0,10,0x0800],[OpType.ACC,1,0,8,0x0100]],True,False], ["TST",0xb100,0xf700,1,1,[[OpType.ACC,1,0,11,0x0800]],True,False], ["MULC",0xc000,0xe700,1,2,[[OpType.ACCM,1,0,12,0x1000],[OpType.REG1A,1,0,11,0x0800]],True,False], - ["CMPAR",0xc100,0xe700,1,2,[[OpType.ACC,1,0,12,0x1000],[OpType.REG1A,1,0,11,0x0800]],True,False], + ["CMPAR",0xc100,0xe700,1,2,[[OpType.ACC,1,0,11,0x0800],[OpType.REG1A,1,0,12,0x1000]],True,False], ["MULCMVZ",0xc200,0xe600,1,3,[[OpType.ACCM,1,0,12,0x1000],[OpType.REG1A,1,0,11,0x0800],[OpType.ACC,1,0,8,0x0100]],True,False], ["MULCAC",0xc400,0xe600,1,3,[[OpType.ACCM,1,0,12,0x1000],[OpType.REG1A,1,0,11,0x0800],[OpType.ACC,1,0,8,0x0100]],True,False], ["MULCMV",0xc600,0xe600,1,3,[[OpType.ACCM,1,0,12,0x1000],[OpType.REG1A,1,0,11,0x0800],[OpType.ACC,1,0,8,0x0100]],True,False],