Summary:
Pull Request resolved: https://github.com/facebookresearch/faiss/pull/5069
Remove the 10 global bare-name using declarations (simd16uint16,
simd32uint8, simd8uint32, simd8float32, simd256bit, simd512bit,
simd32uint16, simd64uint8, simd16float32) from simdlib_dispatch.h.
These aliases resolved through SINGLE_SIMD_LEVEL which is NONE in DD
mode, creating a trap where per-ISA TU code accidentally uses scalar
emulation. Each file that needs the aliases now declares its own using
with an explicit SIMD level, making the dependency visible.
Behavior-preserving: all files use the same SINGLE_SIMD_LEVEL they
used before, but now explicitly.
Reviewed By: mdouze
Differential Revision: D100033901
fbshipit-source-id: 2db034c2868de275a5f018d886264762776548c5
Summary:
Pull Request resolved: https://github.com/facebookresearch/faiss/pull/4866
Templatize all simd wrapper types (simd16uint16, simd32uint8, simd8float32,
etc.) on SIMDLevel. This is the foundation for PQ4 fast scan Dynamic Dispatch.
Primary templates are declared in simdlib.h. Each platform header provides
explicit specializations:
- simdlib_avx2.h: simd16uint16<AVX2>, simd32uint8<AVX2>, etc.
- simdlib_avx512.h: simd32uint16<AVX512>, simd64uint8<AVX512>, etc.
- simdlib_neon.h: simd16uint16<ARM_NEON>, etc.
- simdlib_emulated.h: simd16uint16<NONE>, etc. (always included)
- simdlib_ppc64.h: simd16uint16<NONE>, etc. (PPC-optimized scalar)
SINGLE_SIMD_LEVEL (inline constexpr in simd_levels.h) resolves to NONE in DD
mode and to the compiled-in level in static mode. SINGLE_SIMD_LEVEL_256 maps
through simd256_level_selector for 256-bit types (AVX512->AVX2, SVE->NEON).
Code without explicit SL context uses these. This is migration scaffolding —
subsequent diffs will replace SINGLE_SIMD_LEVEL usages with proper SL dispatch.
simd_result_handlers.h is no longer %include'd by SWIG (the templatized types
are unparseable by SWIG). make_knn_handler methods are %ignore'd. The Python
API does not use these internal SIMD handler types.
Pre-existing bug fixes bundled with this refactor:
- simdlib_avx512.h: simd512bit::bin() stack buffer overflow (char[257] -> char[513])
- simdlib_avx2.h: simd256bit constructor used aligned _mm256_load_si256 instead
of unaligned _mm256_loadu_si256
- All platform headers: simd16uint16/simd32uint8 operator+=/operator-= returned
by value instead of by reference
Static builds: zero performance change. Template specializations produce
identical layout, ABI, and codegen as the old plain structs.
Reviewed By: mdouze
Differential Revision: D95392150
fbshipit-source-id: 435b643f96a7e08d777796390066964d99295f63
Summary:
Pull Request resolved: https://github.com/facebookresearch/faiss/pull/2568
Add a fused kernel for exhaustive_L2sqr_blas() call that combines a computation of dot product and the search for the nearest centroid. As a result, no temporary dot product values are written and read in RAM.
Speeds up the training of PQx[1] indices for dsub = 1, 2, 4, 8, and the effect is higher for higher values of [1]. AVX512 version provides additional overloads for dsub = 12, 16.
The speedup is also beneficial for higher values of pq.cp.max_points_per_centroid (which is 256 by default).
Speeds up IVFPQ training as well.
AVX512 kernel is not enabled, but I've seen it speeding up the training TWICE versus AVX2 version. So, please feel free to use it by enabling AVX512 manually.
Reviewed By: mdouze
Differential Revision: D41166766
fbshipit-source-id: 443014e2e59396b3a90b9171fec8c8191052bcf4
Gergely Szilvasy