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Summary: Pull Request resolved: https://github.com/facebookresearch/faiss/pull/4897 Add `FastScanCodeScanner`, a virtual base that bundles handler + kernel behind the SIMD dispatch boundary. In DD mode, `SINGLE_SIMD_LEVEL = NONE` so the existing fast scan code path uses emulated SIMD types. The new scanner provides per-SIMD translation units (AVX2, AVX512, ARM_NEON) compiled with the correct ISA flags, and a factory function (`make_fast_scan_knn_scanner`) that uses `DISPATCH_SIMDLevel` to select the right TU at runtime. This follows the proven `THE_LEVEL_TO_DISPATCH` pattern from the scalar quantizer per-SIMD TUs (`sq-dispatch.h`). Each per-SIMD TU includes `dispatching.h` which provides: - `ScannerMixIn<Handler>`: wraps a concrete handler and calls accumulation kernels (both search_1 multi-BB and QBS paths) - Factory specialization `make_fast_scan_scanner_impl<SL>()` with combinatorial dispatch over `is_max × with_id_map × handler_type` (SingleResultHandler for k=1, HeapHandler for k≤20, ReservoirHandler for k>20) New files: - `impl/fast_scan/dispatching.h` — dispatch template header - `impl/fast_scan/impl-avx2.cpp` — AVX2 per-SIMD TU - `impl/fast_scan/impl-avx512.cpp` — AVX512 per-SIMD TU - `impl/fast_scan/impl-neon.cpp` — ARM NEON TU (with ARM_SVE forwarding) Modified files: - `impl/fast_scan/pq4_fast_scan.h` — FastScanCodeScanner base + factory decl - `impl/fast_scan/pq4_fast_scan.cpp` — NONE specialization + dispatch wrapper - `xplat.bzl` / `CMakeLists.txt` — register SIMD files and header Note: RaBitQ handler is not wired through FastScanCodeScanner in this diff. That comes in later diffs when callers are switched. Reviewed By: mdouze Differential Revision: D95950483 fbshipit-source-id: 03841671f59c0d99de7d0c7408a64e7a8383a8e7
114 lines
3.6 KiB
C++
114 lines
3.6 KiB
C++
/*
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* Copyright (c) Meta Platforms, Inc. and affiliates.
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*
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* This source code is licensed under the MIT license found in the
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* LICENSE file in the root directory of this source tree.
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*/
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#include <gtest/gtest.h>
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#include <cstddef>
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#include <cstring>
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#include <vector>
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#include <faiss/IndexIVF.h>
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#include <faiss/impl/fast_scan/fast_scan.h>
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#include <faiss/utils/AlignedTable.h>
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#include <faiss/utils/random.h>
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/**
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* This validates we can run fast scan with unaligned codes and get the same
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* results as aligned codes. On modern CPUs, unaligned codes appear to have
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* similar performance characteristics to aligned codes.
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*/
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namespace {
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std::vector<uint8_t> create_aligned_buffer(size_t size, size_t alignment) {
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// Allocate extra space for alignment adjustment
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std::vector<uint8_t> buffer(size + alignment);
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return buffer;
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}
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uint8_t* get_aligned_ptr(std::vector<uint8_t>& buffer, size_t alignment) {
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uint8_t* new_ptr;
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int ret = posix_memalign(
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(void**)&new_ptr, alignment, buffer.size() * sizeof(uint8_t));
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if (ret != 0) {
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throw std::bad_alloc();
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}
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return new_ptr;
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}
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uint8_t* get_unaligned_ptr(std::vector<uint8_t>& buffer, size_t alignment) {
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uint8_t* aligned = get_aligned_ptr(buffer, alignment);
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// Return pointer that is off by 1 byte from alignment
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return aligned + 1;
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}
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} // namespace
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TEST(FastScanUnaligned, TestUnalignedCodesAccess) {
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constexpr size_t alignment = 32;
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constexpr int nsq = 8;
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size_t code_size;
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#ifdef __AVX512F__
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code_size = 512;
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#else
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code_size = 256;
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#endif
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std::random_device rd;
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std::mt19937 gen(rd());
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std::uniform_int_distribution<uint8_t> dist(
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std::numeric_limits<uint8_t>::min(),
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std::numeric_limits<uint8_t>::max());
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std::vector<uint8_t> aligned_buffer =
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create_aligned_buffer(code_size, alignment);
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// unaligned_buffer itself is aligned but it's the buffer for the unaligned
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// pointer.
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std::vector<uint8_t> unaligned_buffer =
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create_aligned_buffer(code_size, alignment);
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uint8_t* codes_aligned = get_aligned_ptr(aligned_buffer, alignment);
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uint8_t* codes_unaligned = get_unaligned_ptr(unaligned_buffer, alignment);
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for (size_t i = 0; i < code_size; i++) {
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uint8_t val = static_cast<uint8_t>(dist(gen));
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codes_aligned[i] = val;
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codes_unaligned[i] = val;
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}
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ASSERT_TRUE(faiss::is_aligned_pointer(codes_aligned));
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ASSERT_FALSE(faiss::is_aligned_pointer(codes_unaligned));
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constexpr int nq = 2;
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std::vector<uint8_t> LUT_aligned_buffer =
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create_aligned_buffer(nq * nsq * 16, alignment);
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uint8_t* LUT = get_aligned_ptr(LUT_aligned_buffer, alignment);
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for (size_t i = 0; i < nq * nsq * 16; i++) {
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LUT[i] = static_cast<uint8_t>(dist(gen));
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}
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// result_size is a subset of code_size, to not run off the unaligned buffer
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constexpr size_t result_size = 64;
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std::vector<uint16_t> accu_aligned(nq * result_size);
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std::vector<uint16_t> accu_unaligned(nq * result_size);
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faiss::accumulate_to_mem(
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nq, result_size, nsq, codes_aligned, LUT, accu_aligned.data());
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faiss::accumulate_to_mem(
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nq, result_size, nsq, codes_unaligned, LUT, accu_unaligned.data());
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// They should be the same, because codes_unaligned gets set to the same
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// values as aligned, it's just not aligned.
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ASSERT_EQ(accu_aligned, accu_unaligned)
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<< "Aligned and unaligned code paths should produce identical results";
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posix_memalign_free(codes_aligned);
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posix_memalign_free(codes_unaligned - 1);
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posix_memalign_free(LUT);
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}
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