mirror of
https://github.com/freebsd/freebsd-src.git
synced 2026-11-07 04:36:52 -10:00
ShengYi Hung
20b1998254
Only the default PSI IDs are supported, other controllers fall back to USB 3.0. Record the speed IDs the controller has: the root hub BOS lists those, and a link without one uses the closest lower ID. Per xHCI 6.2.2, take the parent hub slot ID and port number of SS and SSP devices from the closest higher-rank hub. Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D52347
368 lines
18 KiB
C
368 lines
18 KiB
C
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/*-
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2010 Hans Petter Selasky. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef _XHCIREG_H_
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#define _XHCIREG_H_
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/* XHCI PCI config registers */
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#define PCI_XHCI_CBMEM 0x10 /* configuration base MEM */
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#define PCI_XHCI_USBREV 0x60 /* RO USB protocol revision */
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#define PCI_USB_REV_3_0 0x30 /* USB 3.0 */
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#define PCI_XHCI_FLADJ 0x61 /* RW frame length adjust */
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#define PCI_XHCI_INTEL_XUSB2PR 0xD0 /* Intel USB2 Port Routing */
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#define PCI_XHCI_INTEL_USB2PRM 0xD4 /* Intel USB2 Port Routing Mask */
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#define PCI_XHCI_INTEL_USB3_PSSEN 0xD8 /* Intel USB3 Port SuperSpeed Enable */
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#define PCI_XHCI_INTEL_USB3PRM 0xDC /* Intel USB3 Port Routing Mask */
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/* XHCI capability registers */
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#define XHCI_CAPLENGTH 0x00 /* RO capability */
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#define XHCI_RESERVED 0x01 /* Reserved */
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#define XHCI_HCIVERSION 0x02 /* RO Interface version number */
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#define XHCI_HCIVERSION_0_9 0x0090 /* xHCI version 0.9 */
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#define XHCI_HCIVERSION_1_0 0x0100 /* xHCI version 1.0 */
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#define XHCI_HCSPARAMS1 0x04 /* RO structural parameters 1 */
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#define XHCI_HCS1_DEVSLOT_MAX(x)((x) & 0xFF)
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#define XHCI_HCS1_IRQ_MAX(x) (((x) >> 8) & 0x3FF)
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#define XHCI_HCS1_N_PORTS(x) (((x) >> 24) & 0xFF)
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#define XHCI_HCSPARAMS2 0x08 /* RO structural parameters 2 */
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#define XHCI_HCS2_IST(x) ((x) & 0xF)
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#define XHCI_HCS2_ERST_MAX(x) (((x) >> 4) & 0xF)
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#define XHCI_HCS2_SPR(x) (((x) >> 26) & 0x1)
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#define XHCI_HCS2_SPB_MAX(x) ((((x) >> 16) & 0x3E0) | (((x) >> 27) & 0x1F))
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#define XHCI_HCSPARAMS3 0x0C /* RO structural parameters 3 */
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#define XHCI_HCS3_U1_DEL(x) ((x) & 0xFF)
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#define XHCI_HCS3_U2_DEL(x) (((x) >> 16) & 0xFFFF)
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#define XHCI_HCCPARAMS1 0x10 /* RO capability parameters */
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#define XHCI_HCS0_AC64(x) ((x) & 0x1) /* 64-bit capable */
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#define XHCI_HCS0_BNC(x) (((x) >> 1) & 0x1) /* BW negotiation */
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#define XHCI_HCS0_CSZ(x) (((x) >> 2) & 0x1) /* context size */
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#define XHCI_HCS0_PPC(x) (((x) >> 3) & 0x1) /* port power control */
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#define XHCI_HCS0_PIND(x) (((x) >> 4) & 0x1) /* port indicators */
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#define XHCI_HCS0_LHRC(x) (((x) >> 5) & 0x1) /* light HC reset */
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#define XHCI_HCS0_LTC(x) (((x) >> 6) & 0x1) /* latency tolerance msg */
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#define XHCI_HCS0_NSS(x) (((x) >> 7) & 0x1) /* no secondary sid */
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#define XHCI_HCS0_PSA_SZ_MAX(x) (((x) >> 12) & 0xF) /* max pri. stream array size */
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#define XHCI_HCS0_XECP(x) (((x) >> 16) & 0xFFFF) /* extended capabilities pointer */
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#define XHCI_DBOFF 0x14 /* RO doorbell offset */
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#define XHCI_RTSOFF 0x18 /* RO runtime register space offset */
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/* XHCI operational registers. Offset given by XHCI_CAPLENGTH register */
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#define XHCI_USBCMD 0x00 /* XHCI command */
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#define XHCI_CMD_RS 0x00000001 /* RW Run/Stop */
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#define XHCI_CMD_HCRST 0x00000002 /* RW Host Controller Reset */
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#define XHCI_CMD_INTE 0x00000004 /* RW Interrupter Enable */
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#define XHCI_CMD_HSEE 0x00000008 /* RW Host System Error Enable */
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#define XHCI_CMD_LHCRST 0x00000080 /* RO/RW Light Host Controller Reset */
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#define XHCI_CMD_CSS 0x00000100 /* RW Controller Save State */
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#define XHCI_CMD_CRS 0x00000200 /* RW Controller Restore State */
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#define XHCI_CMD_EWE 0x00000400 /* RW Enable Wrap Event */
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#define XHCI_CMD_EU3S 0x00000800 /* RW Enable U3 MFINDEX Stop */
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#define XHCI_USBSTS 0x04 /* XHCI status */
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#define XHCI_STS_HCH 0x00000001 /* RO - Host Controller Halted */
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#define XHCI_STS_HSE 0x00000004 /* RW - Host System Error */
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#define XHCI_STS_EINT 0x00000008 /* RW - Event Interrupt */
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#define XHCI_STS_PCD 0x00000010 /* RW - Port Change Detect */
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#define XHCI_STS_SSS 0x00000100 /* RO - Save State Status */
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#define XHCI_STS_RSS 0x00000200 /* RO - Restore State Status */
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#define XHCI_STS_SRE 0x00000400 /* RW - Save/Restore Error */
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#define XHCI_STS_CNR 0x00000800 /* RO - Controller Not Ready */
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#define XHCI_STS_HCE 0x00001000 /* RO - Host Controller Error */
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#define XHCI_PAGESIZE 0x08 /* XHCI page size mask */
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#define XHCI_PAGESIZE_4K 0x00000001 /* 4K Page Size */
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#define XHCI_PAGESIZE_8K 0x00000002 /* 8K Page Size */
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#define XHCI_PAGESIZE_16K 0x00000004 /* 16K Page Size */
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#define XHCI_PAGESIZE_32K 0x00000008 /* 32K Page Size */
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#define XHCI_PAGESIZE_64K 0x00000010 /* 64K Page Size */
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#define XHCI_DNCTRL 0x14 /* XHCI device notification control */
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#define XHCI_DNCTRL_MASK(n) (1U << (n))
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#define XHCI_CRCR_LO 0x18 /* XHCI command ring control */
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#define XHCI_CRCR_LO_RCS 0x00000001 /* RW - consumer cycle state */
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#define XHCI_CRCR_LO_CS 0x00000002 /* RW - command stop */
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#define XHCI_CRCR_LO_CA 0x00000004 /* RW - command abort */
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#define XHCI_CRCR_LO_CRR 0x00000008 /* RW - command ring running */
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#define XHCI_CRCR_LO_MASK 0x0000000F
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#define XHCI_CRCR_HI 0x1C /* XHCI command ring control */
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#define XHCI_DCBAAP_LO 0x30 /* XHCI dev context BA pointer */
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#define XHCI_DCBAAP_HI 0x34 /* XHCI dev context BA pointer */
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#define XHCI_CONFIG 0x38
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#define XHCI_CONFIG_SLOTS_MASK 0x000000FF /* RW - number of device slots enabled */
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/* XHCI port status registers */
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#define XHCI_PORTSC(n) (0x3F0 + (0x10 * (n))) /* XHCI port status */
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#define XHCI_PS_CCS 0x00000001 /* RO - current connect status */
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#define XHCI_PS_PED 0x00000002 /* RW - port enabled / disabled */
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#define XHCI_PS_OCA 0x00000008 /* RO - over current active */
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#define XHCI_PS_PR 0x00000010 /* RW - port reset */
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#define XHCI_PS_PLS_GET(x) (((x) >> 5) & 0xF) /* RW - port link state */
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#define XHCI_PS_PLS_SET(x) (((x) & 0xF) << 5) /* RW - port link state */
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#define XHCI_PS_PP 0x00000200 /* RW - port power */
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#define XHCI_PS_SPEED_GET(x) (((x) >> 10) & 0xF) /* RO - port speed */
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#define XHCI_PS_SPEED_FULL 0x1 /* Full Speed USB */
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#define XHCI_PS_SPEED_LOW 0x2 /* Low Speed USB */
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#define XHCI_PS_SPEED_HIGH 0x3 /* High Speed USB */
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#define XHCI_PS_SPEED_SS 0x4 /* Super Speed USB */
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#define XHCI_PS_SPEED_SS_PLUS_GEN2 0x5 /* Super Speed Plus Gen2x1 */
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#define XHCI_PS_SPEED_SS_PLUS_GEN1_x2 0x6 /* Super Speed Plus Gen1x2 */
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#define XHCI_PS_SPEED_SS_PLUS_GEN2_x2 0x7 /* Super Speed Plus Gen2x2 */
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#define XHCI_PS_PIC_GET(x) (((x) >> 14) & 0x3) /* RW - port indicator */
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#define XHCI_PS_PIC_SET(x) (((x) & 0x3) << 14) /* RW - port indicator */
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#define XHCI_PS_LWS 0x00010000 /* RW - port link state write strobe */
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#define XHCI_PS_CSC 0x00020000 /* RW - connect status change */
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#define XHCI_PS_PEC 0x00040000 /* RW - port enable/disable change */
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#define XHCI_PS_WRC 0x00080000 /* RW - warm port reset change */
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#define XHCI_PS_OCC 0x00100000 /* RW - over-current change */
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#define XHCI_PS_PRC 0x00200000 /* RW - port reset change */
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#define XHCI_PS_PLC 0x00400000 /* RW - port link state change */
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#define XHCI_PS_CEC 0x00800000 /* RW - config error change */
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#define XHCI_PS_CAS 0x01000000 /* RO - cold attach status */
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#define XHCI_PS_WCE 0x02000000 /* RW - wake on connect enable */
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#define XHCI_PS_WDE 0x04000000 /* RW - wake on disconnect enable */
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#define XHCI_PS_WOE 0x08000000 /* RW - wake on over-current enable */
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#define XHCI_PS_DR 0x40000000 /* RO - device removable */
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#define XHCI_PS_WPR 0x80000000U /* RW - warm port reset */
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#define XHCI_PS_CLEAR 0x80FF01FFU /* command bits */
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#define XHCI_PORTPMSC(n) (0x3F4 + (0x10 * (n))) /* XHCI status and control */
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#define XHCI_PM3_U1TO_GET(x) (((x) >> 0) & 0xFF) /* RW - U1 timeout */
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#define XHCI_PM3_U1TO_SET(x) (((x) & 0xFF) << 0) /* RW - U1 timeout */
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#define XHCI_PM3_U2TO_GET(x) (((x) >> 8) & 0xFF) /* RW - U2 timeout */
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#define XHCI_PM3_U2TO_SET(x) (((x) & 0xFF) << 8) /* RW - U2 timeout */
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#define XHCI_PM3_FLA 0x00010000 /* RW - Force Link PM Accept */
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#define XHCI_PM2_L1S_GET(x) (((x) >> 0) & 0x7) /* RO - L1 status */
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#define XHCI_PM2_RWE 0x00000008 /* RW - remote wakup enable */
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#define XHCI_PM2_HIRD_GET(x) (((x) >> 4) & 0xF) /* RW - host initiated resume duration */
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#define XHCI_PM2_HIRD_SET(x) (((x) & 0xF) << 4) /* RW - host initiated resume duration */
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#define XHCI_PM2_L1SLOT_GET(x) (((x) >> 8) & 0xFF) /* RW - L1 device slot */
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#define XHCI_PM2_L1SLOT_SET(x) (((x) & 0xFF) << 8) /* RW - L1 device slot */
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#define XHCI_PM2_HLE 0x00010000 /* RW - hardware LPM enable */
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#define XHCI_PORTLI(n) (0x3F8 + (0x10 * (n))) /* XHCI port link info */
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#define XHCI_PLI3_ERR_GET(x) (((x) >> 0) & 0xFFFF) /* RO - port link errors */
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#define XHCI_PORTRSV(n) (0x3FC + (0x10 * (n))) /* XHCI port reserved */
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/* XHCI runtime registers. Offset given by XHCI_CAPLENGTH + XHCI_RTSOFF registers */
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#define XHCI_MFINDEX 0x0000 /* RO - microframe index */
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#define XHCI_MFINDEX_GET(x) ((x) & 0x3FFF)
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#define XHCI_IMAN(n) (0x0020 + (0x20 * (n))) /* XHCI interrupt management */
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#define XHCI_IMAN_INTR_PEND 0x00000001 /* RW - interrupt pending */
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#define XHCI_IMAN_INTR_ENA 0x00000002 /* RW - interrupt enable */
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#define XHCI_IMOD(n) (0x0024 + (0x20 * (n))) /* XHCI interrupt moderation */
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#define XHCI_IMOD_IVAL_GET(x) (((x) >> 0) & 0xFFFF) /* 250ns unit */
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#define XHCI_IMOD_IVAL_SET(x) (((x) & 0xFFFF) << 0) /* 250ns unit */
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#define XHCI_IMOD_ICNT_GET(x) (((x) >> 16) & 0xFFFF) /* 250ns unit */
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#define XHCI_IMOD_ICNT_SET(x) (((x) & 0xFFFF) << 16) /* 250ns unit */
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#define XHCI_IMOD_DEFAULT 0x000001F4U /* 8000 IRQs/second */
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#define XHCI_IMOD_DEFAULT_LP 0x000003F8U /* 4000 IRQs/second - LynxPoint */
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#define XHCI_ERSTSZ(n) (0x0028 + (0x20 * (n))) /* XHCI event ring segment table size */
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#define XHCI_ERSTS_GET(x) ((x) & 0xFFFF)
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#define XHCI_ERSTS_SET(x) ((x) & 0xFFFF)
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#define XHCI_ERSTBA_LO(n) (0x0030 + (0x20 * (n))) /* XHCI event ring segment table BA */
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#define XHCI_ERSTBA_HI(n) (0x0034 + (0x20 * (n))) /* XHCI event ring segment table BA */
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#define XHCI_ERDP_LO(n) (0x0038 + (0x20 * (n))) /* XHCI event ring dequeue pointer */
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#define XHCI_ERDP_LO_SINDEX(x) ((x) & 0x7) /* RO - dequeue segment index */
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#define XHCI_ERDP_LO_BUSY 0x00000008 /* RW - event handler busy */
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#define XHCI_ERDP_HI(n) (0x003C + (0x20 * (n))) /* XHCI event ring dequeue pointer */
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/* XHCI doorbell registers. Offset given by XHCI_CAPLENGTH + XHCI_DBOFF registers */
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#define XHCI_DOORBELL(n) (0x0000 + (4 * (n)))
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#define XHCI_DB_TARGET_GET(x) ((x) & 0xFF) /* RW - doorbell target */
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#define XHCI_DB_TARGET_SET(x) ((x) & 0xFF) /* RW - doorbell target */
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#define XHCI_DB_SID_GET(x) (((x) >> 16) & 0xFFFF) /* RW - doorbell stream ID */
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#define XHCI_DB_SID_SET(x) (((x) & 0xFFFF) << 16) /* RW - doorbell stream ID */
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/* XHCI legacy support */
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#define XHCI_XECP_ID(x) ((x) & 0xFF)
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#define XHCI_XECP_NEXT(x) (((x) >> 8) & 0xFF)
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#define XHCI_XECP_MAJOR(x) (((x) >> 24) & 0xFF)
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#define XHCI_XECP_MINOR(x) (((x) >> 16) & 0xFF)
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#define XHCI_XECP_BIOS_SEM 0x0002
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#define XHCI_XECP_OS_SEM 0x0003
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/* Support protocol */
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#define XHCI_XECP_PSIC_GET(x) (((x) >> 28) & 0x0F)
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#define XHCI_XECP_PSI_RSVD 0x00003E00
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#define XHCI_XECP_PSI_LP 0x0000C000
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#define XHCI_XECP_PSIV_GET(x) ((x) & 0x0F)
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#define XHCI_PSIV_BIT(x) (1U << (x))
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/* XHCI capability ID's */
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#define XHCI_ID_USB_LEGACY 0x0001
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#define XHCI_ID_PROTOCOLS 0x0002
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#define XHCI_ID_POWER_MGMT 0x0003
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#define XHCI_ID_VIRTUALIZATION 0x0004
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#define XHCI_ID_MSG_IRQ 0x0005
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#define XHCI_ID_USB_LOCAL_MEM 0x0006
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/* values 7-9 are reserved */
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#define XHCI_ID_USB_DEBUG 0x000a
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/* values 11-16 are reserved */
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#define XHCI_ID_EXT_MSI 0x0011
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#define XHCI_ID_USB3_TUN 0x0012
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/*
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* XHCI Debug Capability
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* From Section 7.6 of xHCI April 2023 Revision 1.2b.
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*/
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#define XHCI_DCID 0x0000
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#define XHCI_DCDB 0x0004 /* Doorbell */
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#define XHCI_DCDB_OUT 0x00000000
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#define XHCI_DCDB_IN 0x00000100
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#define XHCI_DCDB_INVAL 0x0000FE00
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#define XHCI_DCERSTSZ 0x0008 /* Event Ring Segment Table size */
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#define XHCI_DCERSTBA_LO 0x0010
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#define XHCI_DCERSTBA_HI 0x0014
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#define XHCI_DCERDP_LO 0x0018
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#define XHCI_DCERDP_HI 0x001C
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#define XHCI_DCCTRL 0x0020 /* Debug Control */
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#define XHCI_DCCTRL_DCR 0x00000001
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#define XHCI_DCCTRL_DCR_GET(x) (((x) ) & 0x01)
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#define XHCI_DCCTRL_LSE 0x00000002
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#define XHCI_DCCTRL_LSE_GET(x) (((x) >> 1) & 0x01)
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#define XHCI_DCCTRL_HOT 0x00000004
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#define XHCI_DCCTRL_HOT_GET(x) (((x) >> 2) & 0x01)
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#define XHCI_DCCTRL_HIT 0x00000008
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#define XHCI_DCCTRL_HIT_GET(x) (((x) >> 3) & 0x01)
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#define XHCI_DCCTRL_DRC 0x00000010
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#define XHCI_DCCTRL_DRC_GET(x) (((x) >> 4) & 0x01)
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#define XHCI_DCCTRL_MBS_GET(x) (((x) >> 16) & 0xFF)
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#define XHCI_DCCTRL_ADDR_GET(x) (((x) >> 24) & 0x7F)
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#define XHCI_DCCTRL_DCE 0x80000000
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#define XHCI_DCCTRL_DCE_GET(x) (((x) >> 31) & 0x01)
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#define XHCI_DCST 0x0024 /* Status */
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#define XHCI_DCST_ER 0x00000001
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#define XHCI_DCST_ER_GET(x) (((x) ) & 0x01)
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#define XHCI_DCST_SBR 0x00000002
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#define XHCI_DCST_SBR_GET(x) (((x) >> 1) & 0x01)
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#define XHCI_DCST_PORT_GET(x) (((x) >> 24) & 0xFF)
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#define XHCI_DCPORTSC 0x0028 /* Port Control */
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#define XHCI_DCPORTSC_CCS 0x00000001
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#define XHCI_DCPORTSC_CCS_GET(x) (((x) ) & 0x01)
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#define XHCI_DCPORTSC_PED 0x00000002
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#define XHCI_DCPORTSC_PED_GET(x) (((x) >> 1) & 0x01)
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#define XHCI_DCPORTSC_PR 0x00000010
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#define XHCI_DCPORTSC_PR_GET(x) (((x) >> 4) & 0x01)
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#define XHCI_DCPORTSC_PLS_GET(x) (((x) >> 5) & 0x0F)
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#define XHCI_DCPORTSC_PLS_U0 0x00
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#define XHCI_DCPORTSC_PLS_U1 0x01
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#define XHCI_DCPORTSC_PLS_U2 0x02
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#define XHCI_DCPORTSC_PLS_U3 0x03
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#define XHCI_DCPORTSC_PLS_DISABLED 0x04
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#define XHCI_DCPORTSC_PLS_RXDETECTED 0x05
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#define XHCI_DCPORTSC_PLS_INACTIVE 0x06
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#define XHCI_DCPORTSC_PLS_POLLING 0x07
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#define XHCI_DCPORTSC_PLS_RECOVERY 0x08
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#define XHCI_DCPORTSC_PLS_HOTRESET 0x09
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#define XHCI_DCPORTSC_SPEED_GET(x) (((x) >> 10) & 0x0F)
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#define XHCI_DCPORTSC_CSC 0x00020000
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#define XHCI_DCPORTSC_CSC_GET(x) (((x) >> 17) & 0x01)
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#define XHCI_DCPORTSC_PRC 0x00200000
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#define XHCI_DCPORTSC_PRC_GET(x) (((x) >> 21) & 0x01)
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#define XHCI_DCPORTSC_PLC 0x00400000
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#define XHCI_DCPORTSC_PLC_GET(x) (((x) >> 22) & 0x01)
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#define XHCI_DCPORTSC_CEC 0x00800000
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#define XHCI_DCPORTSC_CEC_GET(x) (((x) >> 23) & 0x01)
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#define XHCI_DCCP_LO 0x0030 /* Context Pointer */
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#define XHCI_DCCP_HI 0x0034
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#define XHCI_DCDDI1 0x0038 /* Device Descriptor Info */
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#define XHCI_DCDDI2 0x003C /* Device Descriptor Info */
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/* DbC CIC offset in uint32 */
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#define XHCI_DCDBCIC_STR0DESC_LO 0x0000
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#define XHCI_DCDBCIC_STR0DESC_HI 0x0001
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#define XHCI_DCDBCIC_MANUDESC_LO 0x0002
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#define XHCI_DCDBCIC_MANUDESC_HI 0x0003
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#define XHCI_DCDBCIC_PRODDESC_LO 0x0004
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#define XHCI_DCDBCIC_PRODDESC_HI 0x0005
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#define XHCI_DCDBCIC_SERIALDESC_LO 0x0006
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#define XHCI_DCDBCIC_SERIALDESC_HI 0x0007
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#define XHCI_DCDBCIC_DESCLEN 0x0008
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#define XHCI_DCDBCIC_STR0DESC_LEN_GET(x) (((x) >> 0) & 0xff)
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#define XHCI_DCDBCIC_STR0DESC_LEN_SET(x) (((x) & 0xff) << 0)
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#define XHCI_DCDBCIC_MANUDESC_LEN_GET(x) (((x) >> 8) & 0xff)
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#define XHCI_DCDBCIC_MANUDESC_LEN_SET(x) (((x) & 0xff) << 8)
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#define XHCI_DCDBCIC_PRODDESC_LEN_GET(x) (((x) >> 16) & 0xff)
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#define XHCI_DCDBCIC_PRODDESC_LEN_SET(x) (((x) & 0xff) << 16)
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#define XHCI_DCDBCIC_SERIALDESC_LEN_GET(x) (((x) >> 24) & 0xff)
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#define XHCI_DCDBCIC_SERIALDESC_LEN_SET(x) (((x) & 0xff) << 24)
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#define XHCI_DCSTATUS(ctrl, portsc) \
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(XHCI_DCCTRL_DCE_GET(ctrl) << 4 | \
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XHCI_DCPORTSC_CCS_GET(portsc) << 3 | \
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XHCI_DCPORTSC_PED_GET(portsc) << 2 | \
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XHCI_DCPORTSC_PR_GET(portsc) << 1 | \
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XHCI_DCCTRL_DCR_GET(ctrl))
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#define XHCI_DCPORTSC_ACK_MASK \
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(XHCI_DCPORTSC_PED | \
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XHCI_DCPORTSC_CSC | XHCI_DCPORTSC_PRC | \
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XHCI_DCPORTSC_PLC | XHCI_DCPORTSC_CEC)
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#define XHCI_DCPORT_ST_OFF 0x00
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#define XHCI_DCPORT_ST_DISCONNECTED 0x10 /* DCE only */
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#define XHCI_DCPORT_ST_DISCONNECTED_RUNNING 0x11 /* XXX: DCE + DCR */
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#define XHCI_DCPORT_ST_DISABLED 0x18 /* DCE + CCS */
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#define XHCI_DCPORT_ST_RESETTING 0x1a /* DCE + CCS + PR */
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#define XHCI_DCPORT_ST_ENABLED 0x1c /* DCE + CCS + PED */
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#define XHCI_DCPORT_ST_CONFIGURED 0x1d /* DCE + CCS + PED + DCR */
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#define XHCI_DC_MAXPACKETLEN 1024
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/*
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* While Sec 7.6.3.2 describes Endpoint IDs should be 0 or 1,
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* Intel chips use Device Context Index (Sec 4.5.1) instead.
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*/
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#define XHCI_DC_EPID_OUT 0
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#define XHCI_DC_EPID_IN 1
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#define XHCI_DC_EPID_OUT_INTEL 2
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#define XHCI_DC_EPID_IN_INTEL 3
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#define XHCI_DC_SLOT 1
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/* XHCI register R/W wrappers */
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#define XREAD1(sc, what, a) \
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bus_space_read_1((sc)->sc_io_tag, (sc)->sc_io_hdl, \
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(a) + (sc)->sc_##what##_off)
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#define XREAD2(sc, what, a) \
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bus_space_read_2((sc)->sc_io_tag, (sc)->sc_io_hdl, \
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(a) + (sc)->sc_##what##_off)
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#define XREAD4(sc, what, a) \
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bus_space_read_4((sc)->sc_io_tag, (sc)->sc_io_hdl, \
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(a) + (sc)->sc_##what##_off)
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#define XWRITE1(sc, what, a, x) \
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bus_space_write_1((sc)->sc_io_tag, (sc)->sc_io_hdl, \
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(a) + (sc)->sc_##what##_off, (x))
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#define XWRITE2(sc, what, a, x) \
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bus_space_write_2((sc)->sc_io_tag, (sc)->sc_io_hdl, \
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(a) + (sc)->sc_##what##_off, (x))
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#define XWRITE4(sc, what, a, x) \
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bus_space_write_4((sc)->sc_io_tag, (sc)->sc_io_hdl, \
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(a) + (sc)->sc_##what##_off, (x))
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#endif /* _XHCIREG_H_ */
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