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84 lines
4.1 KiB
C
84 lines
4.1 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2021 Adrian Chadd <[email protected]>.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice unmodified, this list of conditions, and the following
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* disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef __QCOM_ESS_EDMA_HW_H__
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#define __QCOM_ESS_EDMA_HW_H__
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extern int qcom_ess_edma_hw_reset(struct qcom_ess_edma_softc *sc);
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extern int qcom_ess_edma_hw_get_tx_intr_moderation(
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struct qcom_ess_edma_softc *sc, uint32_t *usec);
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extern int qcom_ess_edma_hw_set_tx_intr_moderation(
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struct qcom_ess_edma_softc *sc, uint32_t usec);
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extern int qcom_ess_edma_hw_set_rx_intr_moderation(
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struct qcom_ess_edma_softc *sc, uint32_t usec);
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extern int qcom_ess_edma_hw_intr_disable(struct qcom_ess_edma_softc *sc);
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extern int qcom_ess_edma_hw_intr_rx_intr_set_enable(
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struct qcom_ess_edma_softc *sc, int rxq, bool state);
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extern int qcom_ess_edma_hw_intr_tx_intr_set_enable(
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struct qcom_ess_edma_softc *sc, int txq, bool state);
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extern int qcom_ess_edma_hw_intr_enable(struct qcom_ess_edma_softc *sc);
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extern int qcom_ess_edma_hw_intr_status_clear(
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struct qcom_ess_edma_softc *sc);
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extern int qcom_ess_edma_hw_intr_rx_ack(struct qcom_ess_edma_softc *sc,
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int rx_queue);
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extern int qcom_ess_edma_hw_intr_tx_ack(struct qcom_ess_edma_softc *sc,
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int tx_queue);
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extern int qcom_ess_edma_hw_configure_rss_table(
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struct qcom_ess_edma_softc *sc);
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extern int qcom_ess_edma_hw_configure_load_balance_table(
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struct qcom_ess_edma_softc *sc);
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extern int qcom_ess_edma_hw_configure_tx_virtual_queue(
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struct qcom_ess_edma_softc *sc);
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extern int qcom_ess_edma_hw_configure_default_axi_transaction_size(
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struct qcom_ess_edma_softc *sc);
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extern int qcom_ess_edma_hw_stop_txrx_queues(struct qcom_ess_edma_softc *sc);
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extern int qcom_ess_edma_hw_stop(struct qcom_ess_edma_softc *sc);
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extern int qcom_ess_edma_hw_rfd_prod_index_update(
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struct qcom_ess_edma_softc *sc, int queue, int idx);
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extern int qcom_ess_edma_hw_rfd_get_cons_index(
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struct qcom_ess_edma_softc *sc, int queue);
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extern int qcom_ess_edma_hw_rfd_sw_cons_index_update(
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struct qcom_ess_edma_softc *sc, int queue, int idx);
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extern int qcom_ess_edma_hw_setup(struct qcom_ess_edma_softc *sc);
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extern int qcom_ess_edma_hw_setup_tx(struct qcom_ess_edma_softc *sc);
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extern int qcom_ess_edma_hw_setup_rx(struct qcom_ess_edma_softc *sc);
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extern int qcom_ess_edma_hw_setup_txrx_desc_rings(
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struct qcom_ess_edma_softc *sc);
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extern int qcom_ess_edma_hw_tx_enable(struct qcom_ess_edma_softc *sc);
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extern int qcom_ess_edma_hw_rx_enable(struct qcom_ess_edma_softc *sc);
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extern int qcom_ess_edma_hw_tx_read_tpd_cons_idx(
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struct qcom_ess_edma_softc *sc, int queue_id, uint16_t *idx);
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extern int qcom_ess_edma_hw_tx_update_tpd_prod_idx(
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struct qcom_ess_edma_softc *sc, int queue_id, uint16_t idx);
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extern int qcom_ess_edma_hw_tx_update_cons_idx(
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struct qcom_ess_edma_softc *sc, int queue_id, uint16_t idx);
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#endif /* __QCOM_ESS_EDMA_VAR_H__ */
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