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clocksource: sunxi: Rename sunxi to sun4i
During the introduction of the Allwinner SoC platforms, sunxi was initially meant as a generic name for all the variants of the Allwinner SoC. It was ok at the time of the support of only the A10 and A13 that looks pretty much the same, but it's beginning to be troublesome with the future addition of the Allwinner A31 (sun6i) that is quite different, and would introduce some weird logic, where sunxi would actually mean in some case sun4i and sun5i but without sun6i... Moreover, it makes the compatible strings naming scheme not consistent with other architectures, where usually for this kind of compability, we just use the oldest SoC name that has this IP, so let's do just this. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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@ -2,7 +2,7 @@ Allwinner A1X SoCs Timer Controller
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Required properties:
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Required properties:
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- compatible : should be "allwinner,sunxi-timer"
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- compatible : should be "allwinner,sun4i-timer"
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- reg : Specifies base physical address and size of the registers.
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- reg : Specifies base physical address and size of the registers.
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- interrupts : The interrupt of the first timer
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- interrupts : The interrupt of the first timer
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- clocks: phandle to the source clock (usually a 24 MHz fixed clock)
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- clocks: phandle to the source clock (usually a 24 MHz fixed clock)
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@ -10,7 +10,7 @@ Required properties:
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Example:
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Example:
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timer {
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timer {
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compatible = "allwinner,sunxi-timer";
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compatible = "allwinner,sun4i-timer";
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reg = <0x01c20c00 0x400>;
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reg = <0x01c20c00 0x400>;
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interrupts = <22>;
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interrupts = <22>;
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clocks = <&osc>;
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clocks = <&osc>;
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@ -7,5 +7,5 @@ config ARCH_SUNXI
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select GENERIC_IRQ_CHIP
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select GENERIC_IRQ_CHIP
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select PINCTRL
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select PINCTRL
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select SPARSE_IRQ
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select SPARSE_IRQ
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select SUNXI_TIMER
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select SUN4I_TIMER
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select PINCTRL_SUNXI
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select PINCTRL_SUNXI
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@ -25,7 +25,7 @@ config DW_APB_TIMER_OF
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config ARMADA_370_XP_TIMER
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config ARMADA_370_XP_TIMER
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bool
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bool
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config SUNXI_TIMER
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config SUN4I_TIMER
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bool
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bool
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config VT8500_TIMER
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config VT8500_TIMER
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@ -16,7 +16,7 @@ obj-$(CONFIG_CLKSRC_NOMADIK_MTU) += nomadik-mtu.o
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obj-$(CONFIG_CLKSRC_DBX500_PRCMU) += clksrc-dbx500-prcmu.o
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obj-$(CONFIG_CLKSRC_DBX500_PRCMU) += clksrc-dbx500-prcmu.o
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obj-$(CONFIG_ARMADA_370_XP_TIMER) += time-armada-370-xp.o
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obj-$(CONFIG_ARMADA_370_XP_TIMER) += time-armada-370-xp.o
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obj-$(CONFIG_ARCH_BCM2835) += bcm2835_timer.o
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obj-$(CONFIG_ARCH_BCM2835) += bcm2835_timer.o
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obj-$(CONFIG_SUNXI_TIMER) += sunxi_timer.o
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obj-$(CONFIG_SUN4I_TIMER) += sun4i_timer.o
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obj-$(CONFIG_ARCH_TEGRA) += tegra20_timer.o
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obj-$(CONFIG_ARCH_TEGRA) += tegra20_timer.o
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obj-$(CONFIG_VT8500_TIMER) += vt8500_timer.o
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obj-$(CONFIG_VT8500_TIMER) += vt8500_timer.o
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@ -37,7 +37,7 @@
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static void __iomem *timer_base;
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static void __iomem *timer_base;
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static void sunxi_clkevt_mode(enum clock_event_mode mode,
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static void sun4i_clkevt_mode(enum clock_event_mode mode,
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struct clock_event_device *clk)
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struct clock_event_device *clk)
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{
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{
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u32 u = readl(timer_base + TIMER_CTL_REG(0));
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u32 u = readl(timer_base + TIMER_CTL_REG(0));
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@ -59,7 +59,7 @@ static void sunxi_clkevt_mode(enum clock_event_mode mode,
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}
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}
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}
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}
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static int sunxi_clkevt_next_event(unsigned long evt,
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static int sun4i_clkevt_next_event(unsigned long evt,
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struct clock_event_device *unused)
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struct clock_event_device *unused)
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{
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{
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u32 u = readl(timer_base + TIMER_CTL_REG(0));
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u32 u = readl(timer_base + TIMER_CTL_REG(0));
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@ -70,16 +70,16 @@ static int sunxi_clkevt_next_event(unsigned long evt,
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return 0;
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return 0;
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}
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}
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static struct clock_event_device sunxi_clockevent = {
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static struct clock_event_device sun4i_clockevent = {
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.name = "sunxi_tick",
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.name = "sun4i_tick",
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.rating = 300,
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.rating = 300,
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.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
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.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
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.set_mode = sunxi_clkevt_mode,
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.set_mode = sun4i_clkevt_mode,
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.set_next_event = sunxi_clkevt_next_event,
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.set_next_event = sun4i_clkevt_next_event,
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};
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};
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static irqreturn_t sunxi_timer_interrupt(int irq, void *dev_id)
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static irqreturn_t sun4i_timer_interrupt(int irq, void *dev_id)
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{
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{
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struct clock_event_device *evt = (struct clock_event_device *)dev_id;
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struct clock_event_device *evt = (struct clock_event_device *)dev_id;
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@ -89,14 +89,14 @@ static irqreturn_t sunxi_timer_interrupt(int irq, void *dev_id)
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return IRQ_HANDLED;
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return IRQ_HANDLED;
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}
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}
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static struct irqaction sunxi_timer_irq = {
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static struct irqaction sun4i_timer_irq = {
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.name = "sunxi_timer0",
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.name = "sun4i_timer0",
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.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
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.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
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.handler = sunxi_timer_interrupt,
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.handler = sun4i_timer_interrupt,
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.dev_id = &sunxi_clockevent,
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.dev_id = &sun4i_clockevent,
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};
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};
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static void __init sunxi_timer_init(struct device_node *node)
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static void __init sun4i_timer_init(struct device_node *node)
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{
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{
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unsigned long rate = 0;
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unsigned long rate = 0;
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struct clk *clk;
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struct clk *clk;
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@ -131,7 +131,7 @@ static void __init sunxi_timer_init(struct device_node *node)
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val = readl(timer_base + TIMER_CTL_REG(0));
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val = readl(timer_base + TIMER_CTL_REG(0));
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writel(val | TIMER_CTL_AUTORELOAD, timer_base + TIMER_CTL_REG(0));
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writel(val | TIMER_CTL_AUTORELOAD, timer_base + TIMER_CTL_REG(0));
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ret = setup_irq(irq, &sunxi_timer_irq);
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ret = setup_irq(irq, &sun4i_timer_irq);
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if (ret)
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if (ret)
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pr_warn("failed to setup irq %d\n", irq);
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pr_warn("failed to setup irq %d\n", irq);
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@ -139,10 +139,10 @@ static void __init sunxi_timer_init(struct device_node *node)
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val = readl(timer_base + TIMER_IRQ_EN_REG);
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val = readl(timer_base + TIMER_IRQ_EN_REG);
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writel(val | TIMER_IRQ_EN(0), timer_base + TIMER_IRQ_EN_REG);
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writel(val | TIMER_IRQ_EN(0), timer_base + TIMER_IRQ_EN_REG);
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sunxi_clockevent.cpumask = cpumask_of(0);
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sun4i_clockevent.cpumask = cpumask_of(0);
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clockevents_config_and_register(&sunxi_clockevent, rate / TIMER_SCAL,
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clockevents_config_and_register(&sun4i_clockevent, rate / TIMER_SCAL,
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0x1, 0xff);
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0x1, 0xff);
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}
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}
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CLOCKSOURCE_OF_DECLARE(sunxi, "allwinner,sunxi-timer",
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CLOCKSOURCE_OF_DECLARE(sun4i, "allwinner,sun4i-timer",
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sunxi_timer_init);
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sun4i_timer_init);
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