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e1000e: Disable L1 ASPM power savings for 82573 mobile variants
L1 ASPM link (pci-e link power savings) has significant benefits (~1W savings when link is active) but unfortunately does not work correctly on any of the chipsets that have 82573 on mobile platforms which causes various nuisances: - eeprom reads return garbage information leading to bad eeprom checksums - long ping times (up to 2 seconds) - complete system hangs (freeze/lockup) A lot of T60 owners have been plagued by this, but other mobile solutions also suffer from these symptoms. Disabling L1 ASPM before we activate the PCI-E link fixes all of these issues at the cost of some power consumption. Remove a workaround RDTR adjustment that is no longer needed with this new one. Signed-off-by: Auke Kok <auke-jan.h.kok@intel.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
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@ -1343,7 +1343,6 @@ struct e1000_info e1000_82573_info = {
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| FLAG_HAS_STATS_ICR_ICT
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| FLAG_HAS_SMART_POWER_DOWN
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| FLAG_HAS_AMT
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| FLAG_HAS_ASPM
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| FLAG_HAS_ERT
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| FLAG_HAS_SWSM_ON_LOAD,
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.pba = 20,
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@ -288,7 +288,6 @@ struct e1000_info {
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#define FLAG_HAS_CTRLEXT_ON_LOAD (1 << 5)
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#define FLAG_HAS_SWSM_ON_LOAD (1 << 6)
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#define FLAG_HAS_JUMBO_FRAMES (1 << 7)
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#define FLAG_HAS_ASPM (1 << 8)
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#define FLAG_HAS_STATS_ICR_ICT (1 << 9)
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#define FLAG_HAS_STATS_PTC_PRC (1 << 10)
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#define FLAG_HAS_SMART_POWER_DOWN (1 << 11)
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@ -3509,6 +3509,33 @@ static int e1000_suspend(struct pci_dev *pdev, pm_message_t state)
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return 0;
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}
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static void e1000e_disable_l1aspm(struct pci_dev *pdev)
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{
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int pos;
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u32 cap;
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u16 val;
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/*
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* 82573 workaround - disable L1 ASPM on mobile chipsets
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*
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* L1 ASPM on various mobile (ich7) chipsets do not behave properly
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* resulting in lost data or garbage information on the pci-e link
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* level. This could result in (false) bad EEPROM checksum errors,
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* long ping times (up to 2s) or even a system freeze/hang.
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*
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* Unfortunately this feature saves about 1W power consumption when
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* active.
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*/
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pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
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pci_read_config_dword(pdev, pos + PCI_EXP_LNKCAP, &cap);
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pci_read_config_word(pdev, pos + PCI_EXP_LNKCTL, &val);
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if (val & 0x2) {
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dev_warn(&pdev->dev, "Disabling L1 ASPM\n");
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val &= ~0x2;
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pci_write_config_word(pdev, pos + PCI_EXP_LNKCTL, val);
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}
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}
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#ifdef CONFIG_PM
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static int e1000_resume(struct pci_dev *pdev)
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{
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@ -3519,6 +3546,7 @@ static int e1000_resume(struct pci_dev *pdev)
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pci_set_power_state(pdev, PCI_D0);
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pci_restore_state(pdev);
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e1000e_disable_l1aspm(pdev);
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err = pci_enable_device(pdev);
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if (err) {
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dev_err(&pdev->dev,
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@ -3619,6 +3647,7 @@ static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev)
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struct e1000_adapter *adapter = netdev_priv(netdev);
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struct e1000_hw *hw = &adapter->hw;
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e1000e_disable_l1aspm(pdev);
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if (pci_enable_device(pdev)) {
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dev_err(&pdev->dev,
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"Cannot re-enable PCI device after reset.\n");
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@ -3720,6 +3749,7 @@ static int __devinit e1000_probe(struct pci_dev *pdev,
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u16 eeprom_data = 0;
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u16 eeprom_apme_mask = E1000_EEPROM_APME;
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e1000e_disable_l1aspm(pdev);
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err = pci_enable_device(pdev);
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if (err)
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return err;
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@ -262,13 +262,6 @@ void __devinit e1000e_check_options(struct e1000_adapter *adapter)
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.max = MAX_RXDELAY } }
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};
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/* modify min and default if 82573 for slow ping w/a,
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* a value greater than 8 needs to be set for RDTR */
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if (adapter->flags & FLAG_HAS_ASPM) {
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opt.def = 32;
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opt.arg.r.min = 8;
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}
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if (num_RxIntDelay > bd) {
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adapter->rx_int_delay = RxIntDelay[bd];
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e1000_validate_option(&adapter->rx_int_delay, &opt,
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