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https://github.com/joel16/android_kernel_sony_msm8994.git
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[PATCH] spufs: set irq affinity for running threads
For far, all SPU triggered interrupts always end up on the first SMT thread, which is a bad solution. This patch implements setting the affinity to the CPU that was running last when entering execution on an SPU. This should result in a significant reduction in IPI calls and better cache locality for SPE thread specific data. Signed-off-by: Arnd Bergmann <arndb@de.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
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@ -23,6 +23,7 @@
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#include <linux/config.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/module.h>
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#include <linux/percpu.h>
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#include <linux/types.h>
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@ -55,6 +56,7 @@ struct iic_regs {
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struct iic {
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struct iic_regs __iomem *regs;
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u8 target_id;
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};
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static DEFINE_PER_CPU(struct iic, iic);
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@ -172,12 +174,11 @@ int iic_get_irq(struct pt_regs *regs)
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return irq;
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}
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static struct iic_regs __iomem *find_iic(int cpu)
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static int setup_iic(int cpu, struct iic *iic)
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{
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struct device_node *np;
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int nodeid = cpu / 2;
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unsigned long regs;
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struct iic_regs __iomem *iic_regs;
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for (np = of_find_node_by_type(NULL, "cpu");
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np;
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@ -188,20 +189,23 @@ static struct iic_regs __iomem *find_iic(int cpu)
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if (!np) {
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printk(KERN_WARNING "IIC: CPU %d not found\n", cpu);
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iic_regs = NULL;
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} else {
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regs = *(long *)get_property(np, "iic", NULL);
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/* hack until we have decided on the devtree info */
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regs += 0x400;
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if (cpu & 1)
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regs += 0x20;
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printk(KERN_DEBUG "IIC for CPU %d at %lx\n", cpu, regs);
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iic_regs = __ioremap(regs, sizeof(struct iic_regs),
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_PAGE_NO_CACHE);
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iic->regs = NULL;
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iic->target_id = 0xff;
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return -ENODEV;
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}
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return iic_regs;
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regs = *(long *)get_property(np, "iic", NULL);
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/* hack until we have decided on the devtree info */
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regs += 0x400;
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if (cpu & 1)
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regs += 0x20;
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printk(KERN_DEBUG "IIC for CPU %d at %lx\n", cpu, regs);
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iic->regs = __ioremap(regs, sizeof(struct iic_regs),
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_PAGE_NO_CACHE);
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iic->target_id = (nodeid << 4) + ((cpu & 1) ? 0xf : 0xe);
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return 0;
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}
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#ifdef CONFIG_SMP
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@ -227,6 +231,12 @@ void iic_cause_IPI(int cpu, int mesg)
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out_be64(&per_cpu(iic, cpu).regs->generate, (IIC_NUM_IPIS - 1 - mesg) << 4);
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}
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u8 iic_get_target_id(int cpu)
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{
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return per_cpu(iic, cpu).target_id;
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}
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EXPORT_SYMBOL_GPL(iic_get_target_id);
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static irqreturn_t iic_ipi_action(int irq, void *dev_id, struct pt_regs *regs)
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{
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smp_message_recv(iic_irq_to_ipi(irq), regs);
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@ -276,7 +286,7 @@ void iic_init_IRQ(void)
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irq_offset = 0;
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for_each_cpu(cpu) {
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iic = &per_cpu(iic, cpu);
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iic->regs = find_iic(cpu);
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setup_iic(cpu, iic);
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if (iic->regs)
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out_be64(&iic->regs->prio, 0xff);
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}
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@ -54,6 +54,7 @@ extern void iic_setup_cpu(void);
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extern void iic_local_enable(void);
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extern void iic_local_disable(void);
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extern u8 iic_get_target_id(int cpu);
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extern void spider_init_IRQ(void);
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extern int spider_get_irq(unsigned long int_pending);
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@ -507,6 +507,14 @@ int spu_irq_class_1_bottom(struct spu *spu)
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return ret;
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}
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void spu_irq_setaffinity(struct spu *spu, int cpu)
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{
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u64 target = iic_get_target_id(cpu);
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u64 route = target << 48 | target << 32 | target << 16;
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spu_int_route_set(spu, route);
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}
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EXPORT_SYMBOL_GPL(spu_irq_setaffinity);
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static void __iomem * __init map_spe_prop(struct device_node *n,
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const char *name)
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{
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@ -357,6 +357,11 @@ int spu_activate(struct spu_context *ctx, u64 flags)
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if (!spu)
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return (signal_pending(current)) ? -ERESTARTSYS : -EAGAIN;
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bind_context(spu, ctx);
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/*
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* We're likely to wait for interrupts on the same
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* CPU that we are now on, so send them here.
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*/
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spu_irq_setaffinity(spu, raw_smp_processor_id());
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put_active_spu(spu);
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return 0;
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}
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@ -147,6 +147,7 @@ struct spu *spu_alloc(void);
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void spu_free(struct spu *spu);
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int spu_irq_class_0_bottom(struct spu *spu);
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int spu_irq_class_1_bottom(struct spu *spu);
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void spu_irq_setaffinity(struct spu *spu, int cpu);
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extern struct spufs_calls {
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asmlinkage long (*create_thread)(const char __user *name,
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