mirror of
https://github.com/joel16/android_kernel_sony_msm8994.git
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[PATCH] CRIS update: pci
Patches to make it possible to add PCI support. Signed-off-by: Mikael Starvik <starvik@axis.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
This commit is contained in:
Mikael Starvik
Linus Torvalds
parent
4f18cfbf09
commit
59c61138a5
@ -1,125 +1,179 @@
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/* DMA mapping. Nothing tricky here, just virt_to_phys */
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#ifndef _ASM_CRIS_DMA_MAPPING_H
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#define _ASM_CRIS_DMA_MAPPING_H
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#include "scatterlist.h"
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#include <linux/mm.h>
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#include <linux/kernel.h>
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static inline int
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dma_supported(struct device *dev, u64 mask)
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{
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BUG();
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return 0;
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}
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#include <asm/cache.h>
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#include <asm/io.h>
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#include <asm/scatterlist.h>
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static inline int
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dma_set_mask(struct device *dev, u64 dma_mask)
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{
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BUG();
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return 1;
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}
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#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
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#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
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#ifdef CONFIG_PCI
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void *dma_alloc_coherent(struct device *dev, size_t size,
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dma_addr_t *dma_handle, int flag);
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void dma_free_coherent(struct device *dev, size_t size,
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void *vaddr, dma_addr_t dma_handle);
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#else
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static inline void *
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dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_handle,
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int flag)
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int flag)
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{
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BUG();
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return NULL;
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BUG();
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return NULL;
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}
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static inline void
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dma_free_coherent(struct device *dev, size_t size, void *cpu_addr,
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dma_addr_t dma_handle)
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dma_addr_t dma_handle)
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{
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BUG();
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BUG();
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}
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#endif
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static inline dma_addr_t
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dma_map_single(struct device *dev, void *cpu_addr, size_t size,
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dma_map_single(struct device *dev, void *ptr, size_t size,
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enum dma_data_direction direction)
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{
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BUG();
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return 0;
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BUG_ON(direction == DMA_NONE);
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return virt_to_phys(ptr);
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}
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static inline void
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dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size,
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enum dma_data_direction direction)
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{
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BUG();
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}
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static inline dma_addr_t
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dma_map_page(struct device *dev, struct page *page,
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unsigned long offset, size_t size,
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enum dma_data_direction direction)
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{
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BUG();
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return 0;
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}
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static inline void
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dma_unmap_page(struct device *dev, dma_addr_t dma_address, size_t size,
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enum dma_data_direction direction)
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{
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BUG();
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BUG_ON(direction == DMA_NONE);
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}
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static inline int
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dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
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enum dma_data_direction direction)
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{
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BUG();
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return 1;
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printk("Map sg\n");
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return nents;
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}
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static inline dma_addr_t
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dma_map_page(struct device *dev, struct page *page, unsigned long offset,
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size_t size, enum dma_data_direction direction)
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{
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BUG_ON(direction == DMA_NONE);
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return page_to_phys(page) + offset;
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}
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static inline void
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dma_unmap_page(struct device *dev, dma_addr_t dma_address, size_t size,
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enum dma_data_direction direction)
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{
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BUG_ON(direction == DMA_NONE);
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}
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static inline void
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dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nhwentries,
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enum dma_data_direction direction)
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{
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BUG();
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BUG_ON(direction == DMA_NONE);
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}
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static inline void
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dma_sync_single(struct device *dev, dma_addr_t dma_handle, size_t size,
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enum dma_data_direction direction)
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dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle, size_t size,
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enum dma_data_direction direction)
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{
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BUG();
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}
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static inline void
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dma_sync_sg(struct device *dev, struct scatterlist *sg, int nelems,
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enum dma_data_direction direction)
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dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle, size_t size,
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enum dma_data_direction direction)
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{
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BUG();
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}
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/* Now for the API extensions over the pci_ one */
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static inline void
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dma_sync_single_range_for_cpu(struct device *dev, dma_addr_t dma_handle,
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unsigned long offset, size_t size,
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enum dma_data_direction direction)
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{
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}
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#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
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#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
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#define dma_is_consistent(d) (1)
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static inline void
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dma_sync_single_range_for_device(struct device *dev, dma_addr_t dma_handle,
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unsigned long offset, size_t size,
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enum dma_data_direction direction)
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{
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}
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static inline void
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dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nelems,
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enum dma_data_direction direction)
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{
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}
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static inline void
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dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, int nelems,
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enum dma_data_direction direction)
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{
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}
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static inline int
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dma_mapping_error(dma_addr_t dma_addr)
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{
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return 0;
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}
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static inline int
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dma_supported(struct device *dev, u64 mask)
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{
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/*
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* we fall back to GFP_DMA when the mask isn't all 1s,
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* so we can't guarantee allocations that must be
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* within a tighter range than GFP_DMA..
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*/
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if(mask < 0x00ffffff)
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return 0;
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return 1;
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}
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static inline int
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dma_set_mask(struct device *dev, u64 mask)
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{
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if(!dev->dma_mask || !dma_supported(dev, mask))
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return -EIO;
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*dev->dma_mask = mask;
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return 0;
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}
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static inline int
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dma_get_cache_alignment(void)
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{
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/* no easy way to get cache size on all processors, so return
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* the maximum possible, to be safe */
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return (1 << L1_CACHE_SHIFT_MAX);
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}
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static inline void
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dma_sync_single_range(struct device *dev, dma_addr_t dma_handle,
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unsigned long offset, size_t size,
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enum dma_data_direction direction)
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{
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BUG();
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}
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#define dma_is_consistent(d) (1)
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static inline void
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dma_cache_sync(void *vaddr, size_t size,
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enum dma_data_direction direction)
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{
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BUG();
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}
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#endif
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#define ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY
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extern int
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dma_declare_coherent_memory(struct device *dev, dma_addr_t bus_addr,
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dma_addr_t device_addr, size_t size, int flags);
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extern void
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dma_release_declared_memory(struct device *dev);
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extern void *
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dma_mark_declared_memory_occupied(struct device *dev,
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dma_addr_t device_addr, size_t size);
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#endif
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@ -10,4 +10,12 @@
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#define MAX_DMA_ADDRESS PAGE_OFFSET
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/* From PCI */
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#ifdef CONFIG_PCI
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extern int isa_dma_bridge_buggy;
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#else
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#define isa_dma_bridge_buggy (0)
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#endif
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#endif /* _ASM_DMA_H */
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@ -3,6 +3,21 @@
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#include <asm/page.h> /* for __va, __pa */
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#include <asm/arch/io.h>
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#include <linux/kernel.h>
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struct cris_io_operations
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{
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u32 (*read_mem)(void *addr, int size);
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void (*write_mem)(u32 val, int size, void *addr);
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u32 (*read_io)(u32 port, void *addr, int size, int count);
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void (*write_io)(u32 port, void *addr, int size, int count);
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};
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#ifdef CONFIG_PCI
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extern struct cris_io_operations *cris_iops;
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#else
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#define cris_iops ((struct cris_io_operations*)NULL)
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#endif
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/*
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* Change virtual addresses to physical addresses and vv.
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@ -18,14 +33,17 @@ extern inline void * phys_to_virt(unsigned long address)
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return __va(address);
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}
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extern void * __ioremap(unsigned long offset, unsigned long size, unsigned long flags);
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extern void __iomem * __ioremap(unsigned long offset, unsigned long size, unsigned long flags);
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extern void __iomem * __ioremap_prot(unsigned long phys_addr, unsigned long size, pgprot_t prot);
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extern inline void * ioremap (unsigned long offset, unsigned long size)
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extern inline void __iomem * ioremap (unsigned long offset, unsigned long size)
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{
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return __ioremap(offset, size, 0);
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}
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extern void iounmap(void *addr);
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extern void iounmap(volatile void * __iomem addr);
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extern void __iomem * ioremap_nocache(unsigned long offset, unsigned long size);
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/*
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* IO bus memory addresses are also 1:1 with the physical address
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@ -39,9 +57,32 @@ extern void iounmap(void *addr);
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* differently. On the CRIS architecture, we just read/write the
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* memory location directly.
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*/
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#define readb(addr) (*(volatile unsigned char *) (addr))
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#define readw(addr) (*(volatile unsigned short *) (addr))
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#define readl(addr) (*(volatile unsigned int *) (addr))
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#ifdef CONFIG_PCI
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#define PCI_SPACE(x) ((((unsigned)(x)) & 0x10000000) == 0x10000000)
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#else
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#define PCI_SPACE(x) 0
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#endif
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static inline unsigned char readb(const volatile void __iomem *addr)
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{
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if (PCI_SPACE(addr) && cris_iops)
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return cris_iops->read_mem((void*)addr, 1);
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else
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return *(volatile unsigned char __force *) addr;
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}
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static inline unsigned short readw(const volatile void __iomem *addr)
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{
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if (PCI_SPACE(addr) && cris_iops)
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return cris_iops->read_mem((void*)addr, 2);
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else
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return *(volatile unsigned short __force *) addr;
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}
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static inline unsigned int readl(const volatile void __iomem *addr)
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{
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if (PCI_SPACE(addr) && cris_iops)
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return cris_iops->read_mem((void*)addr, 4);
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else
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return *(volatile unsigned int __force *) addr;
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}
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#define readb_relaxed(addr) readb(addr)
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#define readw_relaxed(addr) readw(addr)
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#define readl_relaxed(addr) readl(addr)
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@ -49,9 +90,27 @@ extern void iounmap(void *addr);
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#define __raw_readw readw
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#define __raw_readl readl
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#define writeb(b,addr) ((*(volatile unsigned char *) (addr)) = (b))
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#define writew(b,addr) ((*(volatile unsigned short *) (addr)) = (b))
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#define writel(b,addr) ((*(volatile unsigned int *) (addr)) = (b))
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static inline void writeb(unsigned char b, volatile void __iomem *addr)
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{
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if (PCI_SPACE(addr) && cris_iops)
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cris_iops->write_mem(b, 1, (void*)addr);
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else
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*(volatile unsigned char __force *) addr = b;
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}
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static inline void writew(unsigned short b, volatile void __iomem *addr)
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{
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if (PCI_SPACE(addr) && cris_iops)
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cris_iops->write_mem(b, 2, (void*)addr);
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else
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*(volatile unsigned short __force *) addr = b;
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}
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static inline void writel(unsigned int b, volatile void __iomem *addr)
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{
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if (PCI_SPACE(addr) && cris_iops)
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cris_iops->write_mem(b, 4, (void*)addr);
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else
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*(volatile unsigned int __force *) addr = b;
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}
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#define __raw_writeb writeb
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#define __raw_writew writew
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#define __raw_writel writel
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@ -66,25 +125,25 @@ extern void iounmap(void *addr);
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* Again, CRIS does not require mem IO specific function.
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*/
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#define eth_io_copy_and_sum(a,b,c,d) eth_copy_and_sum((a),(void *)(b),(c),(d))
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#define eth_io_copy_and_sum(a,b,c,d) eth_copy_and_sum((a),(void __force *)(b),(c),(d))
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/* The following is junk needed for the arch-independent code but which
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* we never use in the CRIS port
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*/
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#define IO_SPACE_LIMIT 0xffff
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#define inb(x) (0)
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#define inw(x) (0)
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#define inl(x) (0)
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#define outb(x,y)
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#define outw(x,y)
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#define outl(x,y)
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#define insb(x,y,z)
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#define insw(x,y,z)
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#define insl(x,y,z)
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#define outsb(x,y,z)
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#define outsw(x,y,z)
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#define outsl(x,y,z)
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#define inb(port) (cris_iops ? cris_iops->read_io(port,NULL,1,1) : 0)
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#define inw(port) (cris_iops ? cris_iops->read_io(port,NULL,2,1) : 0)
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#define inl(port) (cris_iops ? cris_iops->read_io(port,NULL,4,1) : 0)
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#define insb(port,addr,count) (cris_iops ? cris_iops->read_io(port,addr,1,count) : 0)
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#define insw(port,addr,count) (cris_iops ? cris_iops->read_io(port,addr,2,count) : 0)
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#define insl(port,addr,count) (cris_iops ? cris_iops->read_io(port,addr,4,count) : 0)
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#define outb(data,port) if (cris_iops) cris_iops->write_io(port,(void*)(unsigned)data,1,1)
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#define outw(data,port) if (cris_iops) cris_iops->write_io(port,(void*)(unsigned)data,2,1)
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#define outl(data,port) if (cris_iops) cris_iops->write_io(port,(void*)(unsigned)data,4,1)
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#define outsb(port,addr,count) if(cris_iops) cris_iops->write_io(port,(void*)addr,1,count)
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#define outsw(port,addr,count) if(cris_iops) cris_iops->write_io(port,(void*)addr,2,count)
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#define outsl(port,addr,count) if(cris_iops) cris_iops->write_io(port,(void*)addr,3,count)
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/*
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* Convert a physical pointer to a virtual kernel pointer for /dev/mem
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@ -1,13 +1,105 @@
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#ifndef __ASM_CRIS_PCI_H
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#define __ASM_CRIS_PCI_H
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#include <linux/config.h>
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#ifdef __KERNEL__
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#include <linux/mm.h> /* for struct page */
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/* Can be used to override the logic in pci_scan_bus for skipping
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already-configured bus numbers - to be used for buggy BIOSes
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or architectures with incomplete PCI setup by the loader */
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#define pcibios_assign_all_busses(void) 1
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extern unsigned long pci_mem_start;
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#define PCIBIOS_MIN_IO 0x1000
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#define PCIBIOS_MIN_MEM 0x10000000
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#define PCIBIOS_MIN_CARDBUS_IO 0x4000
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void pcibios_config_init(void);
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struct pci_bus * pcibios_scan_root(int bus);
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int pcibios_assign_resources(void);
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void pcibios_set_master(struct pci_dev *dev);
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void pcibios_penalize_isa_irq(int irq);
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struct irq_routing_table *pcibios_get_irq_routing_table(void);
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int pcibios_set_irq_routing(struct pci_dev *dev, int pin, int irq);
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/* Dynamic DMA mapping stuff.
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* i386 has everything mapped statically.
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*/
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#include <linux/types.h>
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#include <linux/slab.h>
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#include <asm/scatterlist.h>
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#include <linux/string.h>
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#include <asm/io.h>
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struct pci_dev;
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/* The PCI address space does equal the physical memory
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* address space. The networking and block device layers use
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* this boolean for bounce buffer decisions.
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*/
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#define PCI_DMA_BUS_IS_PHYS (1)
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/* pci_unmap_{page,single} is a nop so... */
|
||||
#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)
|
||||
#define DECLARE_PCI_UNMAP_LEN(LEN_NAME)
|
||||
#define pci_unmap_addr(PTR, ADDR_NAME) (0)
|
||||
#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) do { } while (0)
|
||||
#define pci_unmap_len(PTR, LEN_NAME) (0)
|
||||
#define pci_unmap_len_set(PTR, LEN_NAME, VAL) do { } while (0)
|
||||
|
||||
/* This is always fine. */
|
||||
#define pci_dac_dma_supported(pci_dev, mask) (1)
|
||||
|
||||
static inline dma64_addr_t
|
||||
pci_dac_page_to_dma(struct pci_dev *pdev, struct page *page, unsigned long offset, int direction)
|
||||
{
|
||||
return ((dma64_addr_t) page_to_phys(page) +
|
||||
(dma64_addr_t) offset);
|
||||
}
|
||||
|
||||
static inline struct page *
|
||||
pci_dac_dma_to_page(struct pci_dev *pdev, dma64_addr_t dma_addr)
|
||||
{
|
||||
return pfn_to_page(dma_addr >> PAGE_SHIFT);
|
||||
}
|
||||
|
||||
static inline unsigned long
|
||||
pci_dac_dma_to_offset(struct pci_dev *pdev, dma64_addr_t dma_addr)
|
||||
{
|
||||
return (dma_addr & ~PAGE_MASK);
|
||||
}
|
||||
|
||||
static inline void
|
||||
pci_dac_dma_sync_single_for_cpu(struct pci_dev *pdev, dma64_addr_t dma_addr, size_t len, int direction)
|
||||
{
|
||||
}
|
||||
|
||||
static inline void
|
||||
pci_dac_dma_sync_single_for_device(struct pci_dev *pdev, dma64_addr_t dma_addr, size_t len, int direction)
|
||||
{
|
||||
}
|
||||
|
||||
#define HAVE_PCI_MMAP
|
||||
extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
|
||||
enum pci_mmap_state mmap_state, int write_combine);
|
||||
|
||||
|
||||
static inline void pcibios_add_platform_entries(struct pci_dev *dev)
|
||||
{
|
||||
}
|
||||
|
||||
#endif /* __KERNEL__ */
|
||||
|
||||
/* implement the pci_ DMA API in terms of the generic device dma_ one */
|
||||
#include <asm-generic/pci-dma-compat.h>
|
||||
|
||||
/* ETRAX chips don't have a PCI bus. This file is just here because some stupid .c code
|
||||
* includes it even if CONFIG_PCI is not set.
|
||||
*/
|
||||
#define PCI_DMA_BUS_IS_PHYS (1)
|
||||
/* generic pci stuff */
|
||||
#include <asm-generic/pci.h>
|
||||
|
||||
#endif /* __ASM_CRIS_PCI_H */
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user