mirror of
https://github.com/joel16/android_kernel_sony_msm8994.git
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siimage: coding style cleanup (take 2)
Fix 18 errors and several warnings given by checkpatch.pl: - use of C99 // comments; - trailing whitespace; - 'switch' and 'case' not at the same indentation level; - no space before the open parenthesis of the 'if' and 'switch' statements; - space between function name and open parenthesis (though I have introduced such warnins in some places since the code looks prettier with the spaces); - including <asm/io.h> instead of <linux/io.h>; - line over 80 characters. In addition to these changes, also do the following: - make the arrays in sil_set_pio_mode() 'static', and make the arrays in sil_set_dma_mode() 'static const'; - change the string of the 'if' statements into the 'switch' statement in sil_pata_udma_filter(); - drop the needless '==' operators from the 'if' statements where a condition is a mere bit test; - remove needless initializer for the 'tmp' variable in init_chipset_siimage(); - beautify groups of the variable initializers and assignment operators; - add new line after variable definitions; - remove new line between the comment and the statements it refers to; - remove needless curly braces and parentheses; - fix typos, capitalize acronyms, etc. in the comments... Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
This commit is contained in:
Sergei Shtylyov
Bartlomiej Zolnierkiewicz
parent
eee49298dd
commit
7b255436df
@ -1,7 +1,7 @@
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/*
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* Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org>
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* Copyright (C) 2003 Red Hat <alan@redhat.com>
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* Copyright (C) 2007 MontaVista Software, Inc.
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* Copyright (C) 2007-2008 MontaVista Software, Inc.
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* Copyright (C) 2007-2008 Bartlomiej Zolnierkiewicz
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*
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* May be copied or modified under the terms of the GNU General Public License
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@ -17,10 +17,10 @@
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*
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* FAQ Items:
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* If you are using Marvell SATA-IDE adapters with Maxtor drives
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* ensure the system is set up for ATA100/UDMA5 not UDMA6.
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* ensure the system is set up for ATA100/UDMA5, not UDMA6.
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*
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* If you are using WD drives with SATA bridges you must set the
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* drive to "Single". "Master" will hang
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* drive to "Single". "Master" will hang.
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*
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* If you have strange problems with nVidia chipset systems please
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* see the SI support documentation and update your system BIOS
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@ -42,25 +42,24 @@
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#include <linux/hdreg.h>
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#include <linux/ide.h>
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#include <linux/init.h>
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#include <asm/io.h>
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#include <linux/io.h>
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/**
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* pdev_is_sata - check if device is SATA
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* @pdev: PCI device to check
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*
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*
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* Returns true if this is a SATA controller
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*/
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static int pdev_is_sata(struct pci_dev *pdev)
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{
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#ifdef CONFIG_BLK_DEV_IDE_SATA
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switch(pdev->device) {
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case PCI_DEVICE_ID_SII_3112:
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case PCI_DEVICE_ID_SII_1210SA:
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return 1;
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case PCI_DEVICE_ID_SII_680:
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return 0;
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switch (pdev->device) {
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case PCI_DEVICE_ID_SII_3112:
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case PCI_DEVICE_ID_SII_1210SA:
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return 1;
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case PCI_DEVICE_ID_SII_680:
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return 0;
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}
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BUG();
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#endif
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@ -70,10 +69,10 @@ static int pdev_is_sata(struct pci_dev *pdev)
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/**
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* is_sata - check if hwif is SATA
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* @hwif: interface to check
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*
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*
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* Returns true if this is a SATA controller
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*/
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static inline int is_sata(ide_hwif_t *hwif)
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{
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return pdev_is_sata(to_pci_dev(hwif->dev));
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@ -86,21 +85,22 @@ static inline int is_sata(ide_hwif_t *hwif)
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*
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* Turn a config register offset into the right address in either
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* PCI space or MMIO space to access the control register in question
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* Thankfully this is a configuration operation so isnt performance
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* criticial.
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* Thankfully this is a configuration operation, so isn't performance
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* critical.
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*/
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static unsigned long siimage_selreg(ide_hwif_t *hwif, int r)
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{
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unsigned long base = (unsigned long)hwif->hwif_data;
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base += 0xA0 + r;
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if(hwif->mmio)
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base += (hwif->channel << 6);
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if (hwif->mmio)
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base += hwif->channel << 6;
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else
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base += (hwif->channel << 4);
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base += hwif->channel << 4;
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return base;
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}
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/**
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* siimage_seldev - return register base
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* @hwif: interface
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@ -110,16 +110,17 @@ static unsigned long siimage_selreg(ide_hwif_t *hwif, int r)
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* PCI space or MMIO space to access the control register in question
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* including accounting for the unit shift.
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*/
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static inline unsigned long siimage_seldev(ide_drive_t *drive, int r)
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{
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ide_hwif_t *hwif = HWIF(drive);
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unsigned long base = (unsigned long)hwif->hwif_data;
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unsigned long base = (unsigned long)hwif->hwif_data;
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base += 0xA0 + r;
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if(hwif->mmio)
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base += (hwif->channel << 6);
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if (hwif->mmio)
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base += hwif->channel << 6;
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else
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base += (hwif->channel << 4);
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base += hwif->channel << 4;
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base |= drive->select.b.unit << drive->select.b.unit;
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return base;
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}
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@ -184,21 +185,26 @@ static void sil_iowrite32(struct pci_dev *dev, u32 val, unsigned long addr)
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static u8 sil_pata_udma_filter(ide_drive_t *drive)
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{
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ide_hwif_t *hwif = drive->hwif;
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struct pci_dev *dev = to_pci_dev(hwif->dev);
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unsigned long base = (unsigned long) hwif->hwif_data;
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u8 mask = 0, scsc;
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ide_hwif_t *hwif = drive->hwif;
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struct pci_dev *dev = to_pci_dev(hwif->dev);
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unsigned long base = (unsigned long)hwif->hwif_data;
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u8 scsc, mask = 0;
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scsc = sil_ioread8(dev, base + (hwif->mmio ? 0x4A : 0x8A));
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if ((scsc & 0x30) == 0x10) /* 133 */
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switch (scsc & 0x30) {
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case 0x10: /* 133 */
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mask = ATA_UDMA6;
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else if ((scsc & 0x30) == 0x20) /* 2xPCI */
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break;
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case 0x20: /* 2xPCI */
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mask = ATA_UDMA6;
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else if ((scsc & 0x30) == 0x00) /* 100 */
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break;
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case 0x00: /* 100 */
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mask = ATA_UDMA5;
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else /* Disabled ? */
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break;
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default: /* Disabled ? */
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BUG();
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}
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return mask;
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}
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@ -220,8 +226,8 @@ static u8 sil_sata_udma_filter(ide_drive_t *drive)
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static void sil_set_pio_mode(ide_drive_t *drive, u8 pio)
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{
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const u16 tf_speed[] = { 0x328a, 0x2283, 0x1281, 0x10c3, 0x10c1 };
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const u16 data_speed[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 };
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static const u16 tf_speed[] = { 0x328a, 0x2283, 0x1281, 0x10c3, 0x10c1 };
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static const u16 data_speed[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 };
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ide_hwif_t *hwif = HWIF(drive);
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struct pci_dev *dev = to_pci_dev(hwif->dev);
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@ -229,7 +235,7 @@ static void sil_set_pio_mode(ide_drive_t *drive, u8 pio)
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u32 speedt = 0;
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u16 speedp = 0;
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unsigned long addr = siimage_seldev(drive, 0x04);
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unsigned long tfaddr = siimage_selreg(hwif, 0x02);
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unsigned long tfaddr = siimage_selreg(hwif, 0x02);
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unsigned long base = (unsigned long)hwif->hwif_data;
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u8 tf_pio = pio;
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u8 addr_mask = hwif->channel ? (hwif->mmio ? 0xF4 : 0x84)
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@ -261,7 +267,7 @@ static void sil_set_pio_mode(ide_drive_t *drive, u8 pio)
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mode = sil_ioread8(dev, base + addr_mask);
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mode &= ~(unit ? 0x30 : 0x03);
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mode |= (unit ? 0x10 : 0x01);
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mode |= unit ? 0x10 : 0x01;
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sil_iowrite8(dev, mode, base + addr_mask);
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}
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@ -275,44 +281,43 @@ static void sil_set_pio_mode(ide_drive_t *drive, u8 pio)
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static void sil_set_dma_mode(ide_drive_t *drive, const u8 speed)
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{
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u8 ultra6[] = { 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 };
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u8 ultra5[] = { 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01 };
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u16 dma[] = { 0x2208, 0x10C2, 0x10C1 };
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static const u8 ultra6[] = { 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 };
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static const u8 ultra5[] = { 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01 };
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static const u16 dma[] = { 0x2208, 0x10C2, 0x10C1 };
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ide_hwif_t *hwif = HWIF(drive);
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struct pci_dev *dev = to_pci_dev(hwif->dev);
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u16 ultra = 0, multi = 0;
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u8 mode = 0, unit = drive->select.b.unit;
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unsigned long base = (unsigned long)hwif->hwif_data;
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u8 scsc = 0, addr_mask = ((hwif->channel) ?
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((hwif->mmio) ? 0xF4 : 0x84) :
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((hwif->mmio) ? 0xB4 : 0x80));
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u8 scsc = 0, addr_mask = hwif->channel ?
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(hwif->mmio ? 0xF4 : 0x84) :
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(hwif->mmio ? 0xB4 : 0x80);
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unsigned long ma = siimage_seldev(drive, 0x08);
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unsigned long ua = siimage_seldev(drive, 0x0C);
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scsc = sil_ioread8(dev, base + (hwif->mmio ? 0x4A : 0x8A));
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mode = sil_ioread8(dev, base + addr_mask);
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scsc = sil_ioread8 (dev, base + (hwif->mmio ? 0x4A : 0x8A));
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mode = sil_ioread8 (dev, base + addr_mask);
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multi = sil_ioread16(dev, ma);
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ultra = sil_ioread16(dev, ua);
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mode &= ~((unit) ? 0x30 : 0x03);
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mode &= ~(unit ? 0x30 : 0x03);
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ultra &= ~0x3F;
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scsc = ((scsc & 0x30) == 0x00) ? 0 : 1;
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scsc = is_sata(hwif) ? 1 : scsc;
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if (speed >= XFER_UDMA_0) {
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multi = dma[2];
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ultra |= (scsc ? ultra6[speed - XFER_UDMA_0] :
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ultra5[speed - XFER_UDMA_0]);
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mode |= (unit ? 0x30 : 0x03);
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multi = dma[2];
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ultra |= scsc ? ultra6[speed - XFER_UDMA_0] :
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ultra5[speed - XFER_UDMA_0];
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mode |= unit ? 0x30 : 0x03;
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} else {
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multi = dma[speed - XFER_MW_DMA_0];
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mode |= (unit ? 0x20 : 0x02);
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mode |= unit ? 0x20 : 0x02;
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}
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sil_iowrite8(dev, mode, base + addr_mask);
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sil_iowrite8 (dev, mode, base + addr_mask);
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sil_iowrite16(dev, multi, ma);
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sil_iowrite16(dev, ultra, ua);
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}
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@ -326,13 +331,14 @@ static int siimage_io_dma_test_irq(ide_drive_t *drive)
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unsigned long addr = siimage_selreg(hwif, 1);
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/* return 1 if INTR asserted */
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if ((hwif->INB(hwif->dma_status) & 4) == 4)
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if (hwif->INB(hwif->dma_status) & 4)
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return 1;
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/* return 1 if Device INTR asserted */
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pci_read_config_byte(dev, addr, &dma_altstat);
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if (dma_altstat & 8)
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return 0; //return 1;
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return 0; /* return 1; */
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return 0;
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}
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@ -352,9 +358,9 @@ static int siimage_mmio_dma_test_irq(ide_drive_t *drive)
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= (void __iomem *)hwif->sata_scr[SATA_ERROR_OFFSET];
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if (sata_error_addr) {
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unsigned long base = (unsigned long)hwif->hwif_data;
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u32 ext_stat = readl((void __iomem *)(base + 0x10));
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u8 watchdog = 0;
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unsigned long base = (unsigned long)hwif->hwif_data;
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u32 ext_stat = readl((void __iomem *)(base + 0x10));
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u8 watchdog = 0;
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if (ext_stat & ((hwif->channel) ? 0x40 : 0x10)) {
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u32 sata_error = readl(sata_error_addr);
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@ -363,25 +369,22 @@ static int siimage_mmio_dma_test_irq(ide_drive_t *drive)
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watchdog = (sata_error & 0x00680000) ? 1 : 0;
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printk(KERN_WARNING "%s: sata_error = 0x%08x, "
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"watchdog = %d, %s\n",
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drive->name, sata_error, watchdog,
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__func__);
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} else {
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drive->name, sata_error, watchdog, __func__);
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} else
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watchdog = (ext_stat & 0x8000) ? 1 : 0;
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}
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ext_stat >>= 16;
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ext_stat >>= 16;
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if (!(ext_stat & 0x0404) && !watchdog)
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return 0;
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}
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/* return 1 if INTR asserted */
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if ((readb((void __iomem *)hwif->dma_status) & 0x04) == 0x04)
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if (readb((void __iomem *)hwif->dma_status) & 0x04)
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return 1;
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/* return 1 if Device INTR asserted */
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if ((readb((void __iomem *)addr) & 8) == 8)
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return 0; //return 1;
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if (readb((void __iomem *)addr) & 8)
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return 0; /* return 1; */
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return 0;
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}
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@ -440,33 +443,32 @@ static void sil_sata_pre_reset(ide_drive_t *drive)
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}
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/**
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* setup_mmio_siimage - switch an SI controller into MMIO
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* setup_mmio_siimage - switch controller into MMIO mode
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* @dev: PCI device we are configuring
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* @name: device name
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*
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* Attempt to put the device into mmio mode. There are some slight
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* complications here with certain systems where the mmio bar isnt
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* mapped so we have to be sure we can fall back to I/O.
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* Attempt to put the device into MMIO mode. There are some slight
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* complications here with certain systems where the MMIO BAR isn't
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* mapped, so we have to be sure that we can fall back to I/O.
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*/
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static unsigned int setup_mmio_siimage (struct pci_dev *dev, const char *name)
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static unsigned int setup_mmio_siimage(struct pci_dev *dev, const char *name)
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{
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resource_size_t bar5 = pci_resource_start(dev, 5);
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unsigned long barsize = pci_resource_len(dev, 5);
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void __iomem *ioaddr;
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/*
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* Drop back to PIO if we can't map the mmio. Some
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* systems seem to get terminally confused in the PCI
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* spaces.
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* Drop back to PIO if we can't map the MMIO. Some systems
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* seem to get terminally confused in the PCI spaces.
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*/
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if (!request_mem_region(bar5, barsize, name)) {
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printk(KERN_WARNING "siimage: IDE controller MMIO ports not available.\n");
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printk(KERN_WARNING "siimage: IDE controller MMIO ports not "
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"available.\n");
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return 0;
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}
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ioaddr = ioremap(bar5, barsize);
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if (ioaddr == NULL) {
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release_mem_region(bar5, barsize);
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return 0;
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@ -484,23 +486,23 @@ static unsigned int setup_mmio_siimage (struct pci_dev *dev, const char *name)
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* @name: device name
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*
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* Perform the initial PCI set up for this device. Attempt to switch
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* to 133MHz clocking if the system isn't already set up to do it.
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* to 133 MHz clocking if the system isn't already set up to do it.
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*/
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static unsigned int __devinit init_chipset_siimage(struct pci_dev *dev, const char *name)
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static unsigned int __devinit init_chipset_siimage(struct pci_dev *dev,
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const char *name)
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{
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unsigned long base, scsc_addr;
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void __iomem *ioaddr = NULL;
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u8 rev = dev->revision, tmp = 0, BA5_EN = 0;
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u8 rev = dev->revision, tmp, BA5_EN;
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pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, rev ? 1 : 255);
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pci_read_config_byte(dev, 0x8A, &BA5_EN);
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if ((BA5_EN & 0x01) || pci_resource_start(dev, 5)) {
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if ((BA5_EN & 0x01) || pci_resource_start(dev, 5))
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if (setup_mmio_siimage(dev, name))
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ioaddr = pci_get_drvdata(dev);
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}
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base = (unsigned long)ioaddr;
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@ -527,7 +529,7 @@ static unsigned int __devinit init_chipset_siimage(struct pci_dev *dev, const ch
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switch (tmp & 0x30) {
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case 0x00:
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/* On 100MHz clocking, try and switch to 133MHz */
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/* On 100 MHz clocking, try and switch to 133 MHz */
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sil_iowrite8(dev, tmp | 0x10, scsc_addr);
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break;
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case 0x30:
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@ -543,12 +545,12 @@ static unsigned int __devinit init_chipset_siimage(struct pci_dev *dev, const ch
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tmp = sil_ioread8(dev, scsc_addr);
|
||||
|
||||
sil_iowrite8(dev, 0x72, base + 0xA1);
|
||||
sil_iowrite8 (dev, 0x72, base + 0xA1);
|
||||
sil_iowrite16(dev, 0x328A, base + 0xA2);
|
||||
sil_iowrite32(dev, 0x62DD62DD, base + 0xA4);
|
||||
sil_iowrite32(dev, 0x43924392, base + 0xA8);
|
||||
sil_iowrite32(dev, 0x40094009, base + 0xAC);
|
||||
sil_iowrite8(dev, 0x72, base ? (base + 0xE1) : 0xB1);
|
||||
sil_iowrite8 (dev, 0x72, base ? (base + 0xE1) : 0xB1);
|
||||
sil_iowrite16(dev, 0x328A, base ? (base + 0xE2) : 0xB2);
|
||||
sil_iowrite32(dev, 0x62DD62DD, base ? (base + 0xE4) : 0xB4);
|
||||
sil_iowrite32(dev, 0x43924392, base ? (base + 0xE8) : 0xB8);
|
||||
@ -579,8 +581,7 @@ static unsigned int __devinit init_chipset_siimage(struct pci_dev *dev, const ch
|
||||
*
|
||||
* The basic setup here is fairly simple, we can use standard MMIO
|
||||
* operations. However we do have to set the taskfile register offsets
|
||||
* by hand as there isnt a standard defined layout for them this
|
||||
* time.
|
||||
* by hand as there isn't a standard defined layout for them this time.
|
||||
*
|
||||
* The hardware supports buffered taskfiles and also some rather nice
|
||||
* extended PRD tables. For better SI3112 support use the libata driver
|
||||
@ -591,24 +592,20 @@ static void __devinit init_mmio_iops_siimage(ide_hwif_t *hwif)
|
||||
struct pci_dev *dev = to_pci_dev(hwif->dev);
|
||||
void *addr = pci_get_drvdata(dev);
|
||||
u8 ch = hwif->channel;
|
||||
unsigned long base;
|
||||
|
||||
struct ide_io_ports *io_ports = &hwif->io_ports;
|
||||
unsigned long base;
|
||||
|
||||
/*
|
||||
* Fill in the basic HWIF bits
|
||||
* Fill in the basic hwif bits
|
||||
*/
|
||||
|
||||
hwif->host_flags |= IDE_HFLAG_MMIO;
|
||||
default_hwif_mmiops(hwif);
|
||||
hwif->hwif_data = addr;
|
||||
hwif->hwif_data = addr;
|
||||
|
||||
/*
|
||||
* Now set up the hw. We have to do this ourselves as
|
||||
* the MMIO layout isnt the same as the standard port
|
||||
* based I/O
|
||||
* Now set up the hw. We have to do this ourselves as the
|
||||
* MMIO layout isn't the same as the standard port based I/O.
|
||||
*/
|
||||
|
||||
memset(io_ports, 0, sizeof(*io_ports));
|
||||
|
||||
base = (unsigned long)addr;
|
||||
@ -618,10 +615,9 @@ static void __devinit init_mmio_iops_siimage(ide_hwif_t *hwif)
|
||||
base += 0x80;
|
||||
|
||||
/*
|
||||
* The buffered task file doesn't have status/control
|
||||
* so we can't currently use it sanely since we want to
|
||||
* use LBA48 mode.
|
||||
*/
|
||||
* The buffered task file doesn't have status/control, so we
|
||||
* can't currently use it sanely since we want to use LBA48 mode.
|
||||
*/
|
||||
io_ports->data_addr = base;
|
||||
io_ports->error_addr = base + 1;
|
||||
io_ports->nsect_addr = base + 2;
|
||||
@ -650,19 +646,17 @@ static void __devinit init_mmio_iops_siimage(ide_hwif_t *hwif)
|
||||
|
||||
static int is_dev_seagate_sata(ide_drive_t *drive)
|
||||
{
|
||||
const char *s = &drive->id->model[0];
|
||||
unsigned len;
|
||||
const char *s = &drive->id->model[0];
|
||||
unsigned len = strnlen(s, sizeof(drive->id->model));
|
||||
|
||||
len = strnlen(s, sizeof(drive->id->model));
|
||||
|
||||
if ((len > 4) && (!memcmp(s, "ST", 2))) {
|
||||
if ((len > 4) && (!memcmp(s, "ST", 2)))
|
||||
if ((!memcmp(s + len - 2, "AS", 2)) ||
|
||||
(!memcmp(s + len - 3, "ASL", 3))) {
|
||||
printk(KERN_INFO "%s: applying pessimistic Seagate "
|
||||
"errata fix\n", drive->name);
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -679,7 +673,7 @@ static void __devinit sil_quirkproc(ide_drive_t *drive)
|
||||
{
|
||||
ide_hwif_t *hwif = drive->hwif;
|
||||
|
||||
/* Try and raise the rqsize */
|
||||
/* Try and rise the rqsize */
|
||||
if (!is_sata(hwif) || !is_dev_seagate_sata(drive))
|
||||
hwif->rqsize = 128;
|
||||
}
|
||||
@ -713,15 +707,14 @@ static void __devinit init_iops_siimage(ide_hwif_t *hwif)
|
||||
* sil_cable_detect - cable detection
|
||||
* @hwif: interface to check
|
||||
*
|
||||
* Check for the presence of an ATA66 capable cable on the
|
||||
* interface.
|
||||
* Check for the presence of an ATA66 capable cable on the interface.
|
||||
*/
|
||||
|
||||
static u8 __devinit sil_cable_detect(ide_hwif_t *hwif)
|
||||
{
|
||||
struct pci_dev *dev = to_pci_dev(hwif->dev);
|
||||
unsigned long addr = siimage_selreg(hwif, 0);
|
||||
u8 ata66 = sil_ioread8(dev, addr);
|
||||
struct pci_dev *dev = to_pci_dev(hwif->dev);
|
||||
unsigned long addr = siimage_selreg(hwif, 0);
|
||||
u8 ata66 = sil_ioread8(dev, addr);
|
||||
|
||||
return (ata66 & 0x01) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
|
||||
}
|
||||
@ -767,15 +760,16 @@ static const struct ide_port_info siimage_chipsets[] __devinitdata = {
|
||||
};
|
||||
|
||||
/**
|
||||
* siimage_init_one - pci layer discovery entry
|
||||
* siimage_init_one - PCI layer discovery entry
|
||||
* @dev: PCI device
|
||||
* @id: ident table entry
|
||||
*
|
||||
* Called by the PCI code when it finds an SI680 or SI3112 controller.
|
||||
* Called by the PCI code when it finds an SiI680 or SiI3112 controller.
|
||||
* We then use the IDE PCI generic helper to do most of the work.
|
||||
*/
|
||||
|
||||
static int __devinit siimage_init_one(struct pci_dev *dev, const struct pci_device_id *id)
|
||||
|
||||
static int __devinit siimage_init_one(struct pci_dev *dev,
|
||||
const struct pci_device_id *id)
|
||||
{
|
||||
struct ide_port_info d;
|
||||
u8 idx = id->driver_data;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user