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[ARM] 4123/1: xsc3: general cleanup
This patch cleans up proc-xsc3: - Correct a number of typos. - Fix up indentation in a number of places. - Change references to the various caches to be more clear about whether we're talking about the L1 D, the L1 I or the unified L2 cache. - Rename "drain write buffer" to "data write barrier", the official name used in the Manzano manual. - Change the xsc3 cpu name from "XScale-Core3" to "XScale-V3 based processor". Also, since a previously merged patch implements proper support for using a MAC or iWMMXt coprocessor on xsc3 platforms, we no longer need to enable access to CP0 on boot. Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Lennert Buytenhek
Russell King
parent
ae0a846e41
commit
850b42933e
@ -5,23 +5,23 @@
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* Current Maintainer: Lennert Buytenhek <buytenh@wantstofly.org>
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*
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* Copyright 2004 (C) Intel Corp.
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* Copyright 2005 (c) MontaVista Software, Inc.
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* Copyright 2005 (C) MontaVista Software, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* MMU functions for the Intel XScale3 Core (XSC3). The XSC3 core is an
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* extension to Intel's original XScale core that adds the following
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* MMU functions for the Intel XScale3 Core (XSC3). The XSC3 core is
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* an extension to Intel's original XScale core that adds the following
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* features:
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*
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* - ARMv6 Supersections
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* - Low Locality Reference pages (replaces mini-cache)
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* - 36-bit addressing
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* - L2 cache
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* - Cache-coherency if chipset supports it
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* - Cache coherency if chipset supports it
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*
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* Based on orignal XScale code by Nicolas Pitre
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* Based on original XScale code by Nicolas Pitre.
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*/
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#include <linux/linkage.h>
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@ -42,12 +42,12 @@
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#define MAX_AREA_SIZE 32768
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/*
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* The cache line size of the I and D cache.
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* The cache line size of the L1 I, L1 D and unified L2 cache.
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*/
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#define CACHELINESIZE 32
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/*
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* The size of the data cache.
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* The size of the L1 D cache.
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*/
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#define CACHESIZE 32768
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@ -57,9 +57,9 @@
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#define L2_CACHE_ENABLE 1
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/*
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* This macro is used to wait for a CP15 write and is needed
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* when we have to ensure that the last operation to the co-pro
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* was completed before continuing with operation.
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* This macro is used to wait for a CP15 write and is needed when we
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* have to ensure that the last operation to the coprocessor was
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* completed before continuing with operation.
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*/
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.macro cpwait_ret, lr, rd
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mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15
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@ -68,13 +68,13 @@
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.endm
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/*
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* This macro cleans & invalidates the entire xsc3 dcache by set & way.
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* This macro cleans and invalidates the entire L1 D cache.
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*/
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.macro clean_d_cache rd, rs
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mov \rd, #0x1f00
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orr \rd, \rd, #0x00e0
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1: mcr p15, 0, \rd, c7, c14, 2 @ clean/inv set/way
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1: mcr p15, 0, \rd, c7, c14, 2 @ clean/invalidate L1 D line
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adds \rd, \rd, #0x40000000
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bcc 1b
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subs \rd, \rd, #0x20
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@ -119,15 +119,15 @@ ENTRY(cpu_xsc3_reset)
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mov r1, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
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msr cpsr_c, r1 @ reset CPSR
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mrc p15, 0, r1, c1, c0, 0 @ ctrl register
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bic r1, r1, #0x0086 @ ........B....CA.
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bic r1, r1, #0x3900 @ ..VIZ..S........
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bic r1, r1, #0x0086 @ ........B....CA.
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mcr p15, 0, r1, c1, c0, 0 @ ctrl register
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mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches & BTB
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mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB
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bic r1, r1, #0x0001 @ ...............M
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mcr p15, 0, r1, c1, c0, 0 @ ctrl register
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@ CAUTION: MMU turned off from this point. We count on the pipeline
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@ already containing those two last instructions to survive.
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mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
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mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs
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mov pc, r0
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/*
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@ -139,14 +139,12 @@ ENTRY(cpu_xsc3_reset)
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*
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* XScale supports clock switching, but using idle mode support
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* allows external hardware to react to system state changes.
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MMG: Come back to this one.
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*/
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.align 5
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ENTRY(cpu_xsc3_do_idle)
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mov r0, #1
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mcr p14, 0, r0, c7, c0, 0 @ Go to IDLE
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mcr p14, 0, r0, c7, c0, 0 @ go to idle
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mov pc, lr
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/* ================================= CACHE ================================ */
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@ -171,9 +169,9 @@ ENTRY(xsc3_flush_kern_cache_all)
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__flush_whole_cache:
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clean_d_cache r0, r1
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tst r2, #VM_EXEC
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mcrne p15, 0, ip, c7, c5, 0 @ Invalidate I cache & BTB
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mcrne p15, 0, ip, c7, c10, 4 @ Drain Write Buffer
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mcrne p15, 0, ip, c7, c5, 4 @ Prefetch Flush
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mcrne p15, 0, ip, c7, c5, 0 @ invalidate L1 I cache and BTB
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mcrne p15, 0, ip, c7, c10, 4 @ data write barrier
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mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush
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mov pc, lr
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/*
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@ -194,21 +192,21 @@ ENTRY(xsc3_flush_user_cache_range)
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bhs __flush_whole_cache
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1: tst r2, #VM_EXEC
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mcrne p15, 0, r0, c7, c5, 1 @ Invalidate I cache line
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mcr p15, 0, r0, c7, c14, 1 @ Clean/invalidate D cache line
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mcrne p15, 0, r0, c7, c5, 1 @ invalidate L1 I line
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mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line
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add r0, r0, #CACHELINESIZE
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cmp r0, r1
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blo 1b
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tst r2, #VM_EXEC
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mcrne p15, 0, ip, c7, c5, 6 @ Invalidate BTB
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mcrne p15, 0, ip, c7, c10, 4 @ Drain Write Buffer
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mcrne p15, 0, ip, c7, c5, 4 @ Prefetch Flush
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mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB
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mcrne p15, 0, ip, c7, c10, 4 @ data write barrier
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mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush
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mov pc, lr
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/*
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* coherent_kern_range(start, end)
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*
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* Ensure coherency between the Icache and the Dcache in the
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* Ensure coherency between the I cache and the D cache in the
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* region described by start. If you have non-snooping
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* Harvard caches, you need to implement this function.
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*
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@ -222,34 +220,34 @@ ENTRY(xsc3_coherent_kern_range)
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/* FALLTHROUGH */
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ENTRY(xsc3_coherent_user_range)
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bic r0, r0, #CACHELINESIZE - 1
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1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
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1: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
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add r0, r0, #CACHELINESIZE
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cmp r0, r1
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blo 1b
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB
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mcr p15, 0, r0, c7, c10, 4 @ Drain Write Buffer
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mcr p15, 0, r0, c7, c5, 4 @ Prefetch Flush
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mcr p15, 0, r0, c7, c5, 0 @ invalidate L1 I cache and BTB
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mcr p15, 0, r0, c7, c10, 4 @ data write barrier
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mcr p15, 0, r0, c7, c5, 4 @ prefetch flush
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mov pc, lr
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/*
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* flush_kern_dcache_page(void *page)
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*
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* Ensure no D cache aliasing occurs, either with itself or
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* the I cache
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* the I cache.
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*
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* - addr - page aligned address
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*/
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ENTRY(xsc3_flush_kern_dcache_page)
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add r1, r0, #PAGE_SZ
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1: mcr p15, 0, r0, c7, c14, 1 @ Clean/Invalidate D Cache line
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1: mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line
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add r0, r0, #CACHELINESIZE
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cmp r0, r1
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blo 1b
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB
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mcr p15, 0, r0, c7, c10, 4 @ Drain Write Buffer
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mcr p15, 0, r0, c7, c5, 4 @ Prefetch Flush
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mcr p15, 0, r0, c7, c5, 0 @ invalidate L1 I cache and BTB
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mcr p15, 0, r0, c7, c10, 4 @ data write barrier
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mcr p15, 0, r0, c7, c5, 4 @ prefetch flush
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mov pc, lr
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/*
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@ -266,17 +264,17 @@ ENTRY(xsc3_flush_kern_dcache_page)
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ENTRY(xsc3_dma_inv_range)
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tst r0, #CACHELINESIZE - 1
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bic r0, r0, #CACHELINESIZE - 1
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mcrne p15, 0, r0, c7, c10, 1 @ clean L1 D entry
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mcrne p15, 1, r0, c7, c11, 1 @ clean L2 D entry
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mcrne p15, 0, r0, c7, c10, 1 @ clean L1 D line
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mcrne p15, 1, r0, c7, c11, 1 @ clean L2 line
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tst r1, #CACHELINESIZE - 1
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mcrne p15, 0, r1, c7, c10, 1 @ clean L1 D entry
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mcrne p15, 1, r1, c7, c11, 1 @ clean L2 D entry
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1: mcr p15, 0, r0, c7, c6, 1 @ invalidate L1 D entry
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mcr p15, 1, r0, c7, c7, 1 @ Invalidate L2 D cache line
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mcrne p15, 0, r1, c7, c10, 1 @ clean L1 D line
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mcrne p15, 1, r1, c7, c11, 1 @ clean L2 line
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1: mcr p15, 0, r0, c7, c6, 1 @ invalidate L1 D line
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mcr p15, 1, r0, c7, c7, 1 @ invalidate L2 line
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add r0, r0, #CACHELINESIZE
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cmp r0, r1
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blo 1b
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mcr p15, 0, r0, c7, c10, 4 @ Drain Write Buffer
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mcr p15, 0, r0, c7, c10, 4 @ data write barrier
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mov pc, lr
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/*
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@ -289,12 +287,12 @@ ENTRY(xsc3_dma_inv_range)
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*/
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ENTRY(xsc3_dma_clean_range)
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bic r0, r0, #CACHELINESIZE - 1
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1: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D entry
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mcr p15, 1, r0, c7, c11, 1 @ clean L2 D entry
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1: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
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mcr p15, 1, r0, c7, c11, 1 @ clean L2 line
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add r0, r0, #CACHELINESIZE
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cmp r0, r1
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blo 1b
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mcr p15, 0, r0, c7, c10, 4 @ Drain Write Buffer
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mcr p15, 0, r0, c7, c10, 4 @ data write barrier
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mov pc, lr
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/*
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@ -307,13 +305,13 @@ ENTRY(xsc3_dma_clean_range)
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*/
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ENTRY(xsc3_dma_flush_range)
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bic r0, r0, #CACHELINESIZE - 1
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1: mcr p15, 0, r0, c7, c14, 1 @ Clean/invalidate L1 D cache line
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mcr p15, 1, r0, c7, c11, 1 @ Clean L2 D cache line
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mcr p15, 1, r0, c7, c7, 1 @ Invalidate L2 D cache line
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1: mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line
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mcr p15, 1, r0, c7, c11, 1 @ clean L2 line
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mcr p15, 1, r0, c7, c7, 1 @ invalidate L2 line
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add r0, r0, #CACHELINESIZE
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cmp r0, r1
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blo 1b
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mcr p15, 0, r0, c7, c10, 4 @ Drain Write Buffer
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mcr p15, 0, r0, c7, c10, 4 @ data write barrier
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mov pc, lr
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ENTRY(xsc3_cache_fns)
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@ -328,7 +326,7 @@ ENTRY(xsc3_cache_fns)
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.long xsc3_dma_flush_range
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ENTRY(cpu_xsc3_dcache_clean_area)
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1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
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1: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
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add r0, r0, #CACHELINESIZE
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subs r1, r1, #CACHELINESIZE
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bhi 1b
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@ -346,14 +344,14 @@ ENTRY(cpu_xsc3_dcache_clean_area)
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.align 5
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ENTRY(cpu_xsc3_switch_mm)
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clean_d_cache r1, r2
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mcr p15, 0, ip, c7, c5, 0 @ Invalidate I cache & BTB
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mcr p15, 0, ip, c7, c10, 4 @ Drain Write Buffer
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mcr p15, 0, ip, c7, c5, 4 @ Prefetch Flush
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mcr p15, 0, ip, c7, c5, 0 @ invalidate L1 I cache and BTB
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mcr p15, 0, ip, c7, c10, 4 @ data write barrier
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mcr p15, 0, ip, c7, c5, 4 @ prefetch flush
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#ifdef L2_CACHE_ENABLE
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orr r0, r0, #0x18 @ cache the page table in L2
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#endif
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mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
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mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
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mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs
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cpwait_ret lr, ip
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/*
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@ -366,34 +364,34 @@ ENTRY(cpu_xsc3_switch_mm)
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ENTRY(cpu_xsc3_set_pte_ext)
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str r1, [r0], #-2048 @ linux version
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bic r2, r1, #0xff0 @ Keep C, B bits
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bic r2, r1, #0xff0 @ keep C, B bits
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orr r2, r2, #PTE_TYPE_EXT @ extended page
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tst r1, #L_PTE_SHARED @ Shared?
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tst r1, #L_PTE_SHARED @ shared?
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orrne r2, r2, #0x200
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eor r3, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
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tst r3, #L_PTE_USER @ User?
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tst r3, #L_PTE_USER @ user?
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orrne r2, r2, #PTE_EXT_AP_URO_SRW @ yes -> user r/o, system r/w
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tst r3, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty?
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tst r3, #L_PTE_WRITE | L_PTE_DIRTY @ write and dirty?
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orreq r2, r2, #PTE_EXT_AP_UNO_SRW @ yes -> user n/a, system r/w
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@ combined with user -> user r/w
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#if L2_CACHE_ENABLE
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@ If its cacheable it needs to be in L2 also.
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@ If it's cacheable, it needs to be in L2 also.
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eor ip, r1, #L_PTE_CACHEABLE
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tst ip, #L_PTE_CACHEABLE
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orreq r2, r2, #PTE_EXT_TEX(0x5)
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#endif
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tst r3, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young?
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tst r3, #L_PTE_PRESENT | L_PTE_YOUNG @ present and young?
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movne r2, #0 @ no -> fault
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str r2, [r0] @ hardware version
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mov ip, #0
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mcr p15, 0, r0, c7, c10, 1 @ Clean D cache line mcr
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mcr p15, 0, ip, c7, c10, 4 @ Drain Write Buffer
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mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
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mcr p15, 0, ip, c7, c10, 4 @ data write barrier
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mov pc, lr
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.ltorg
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@ -406,17 +404,18 @@ ENTRY(cpu_xsc3_set_pte_ext)
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__xsc3_setup:
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mov r0, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
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msr cpsr_c, r0
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mcr p15, 0, ip, c7, c7, 0 @ invalidate I, D caches & BTB
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mcr p15, 0, ip, c7, c10, 4 @ Drain Write Buffer
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mcr p15, 0, ip, c7, c5, 4 @ Prefetch Flush
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mcr p15, 0, ip, c8, c7, 0 @ invalidate I, D TLBs
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mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB
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mcr p15, 0, ip, c7, c10, 4 @ data write barrier
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mcr p15, 0, ip, c7, c5, 4 @ prefetch flush
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mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs
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#if L2_CACHE_ENABLE
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orr r4, r4, #0x18 @ cache the page table in L2
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#endif
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mcr p15, 0, r4, c2, c0, 0 @ load page table pointer
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mov r0, #1 @ Allow access to CP0 and CP13
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orr r0, r0, #1 << 13 @ Its undefined whether this
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mcr p15, 0, r0, c15, c1, 0 @ affects USR or SVC modes
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mov r0, #0 @ don't allow CP access
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mcr p15, 0, r0, c15, c1, 0 @ write CP access register
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mrc p15, 0, r0, c1, c0, 1 @ get auxiliary control reg
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and r0, r0, #2 @ preserve bit P bit setting
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#if L2_CACHE_ENABLE
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@ -427,9 +426,9 @@ __xsc3_setup:
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adr r5, xsc3_crval
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ldmia r5, {r5, r6}
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mrc p15, 0, r0, c1, c0, 0 @ get control register
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bic r0, r0, r5 @ .... .... .... ..A.
|
||||
orr r0, r0, r6 @ .... .... .... .C.M
|
||||
orr r0, r0, #0x00000800 @ ..VI Z..S .... ....
|
||||
bic r0, r0, r5 @ ..V. ..R. .... ..A.
|
||||
orr r0, r0, r6 @ ..VI Z..S .... .C.M (mmu)
|
||||
@ ...I Z..S .... .... (uc)
|
||||
#if L2_CACHE_ENABLE
|
||||
orr r0, r0, #0x04000000 @ L2 enable
|
||||
#endif
|
||||
@ -439,7 +438,7 @@ __xsc3_setup:
|
||||
|
||||
.type xsc3_crval, #object
|
||||
xsc3_crval:
|
||||
crval clear=0x04003b02, mmuset=0x00003105, ucset=0x00001100
|
||||
crval clear=0x04002202, mmuset=0x00003905, ucset=0x00001900
|
||||
|
||||
__INITDATA
|
||||
|
||||
@ -474,7 +473,7 @@ cpu_elf_name:
|
||||
|
||||
.type cpu_xsc3_name, #object
|
||||
cpu_xsc3_name:
|
||||
.asciz "XScale-Core3"
|
||||
.asciz "XScale-V3 based processor"
|
||||
.size cpu_xsc3_name, . - cpu_xsc3_name
|
||||
|
||||
.align
|
||||
@ -490,7 +489,7 @@ __xsc3_proc_info:
|
||||
PMD_SECT_CACHEABLE | \
|
||||
PMD_SECT_AP_WRITE | \
|
||||
PMD_SECT_AP_READ
|
||||
.long PMD_TYPE_SECT | \
|
||||
.long PMD_TYPE_SECT | \
|
||||
PMD_SECT_AP_WRITE | \
|
||||
PMD_SECT_AP_READ
|
||||
b __xsc3_setup
|
||||
|
||||
Loading…
Reference in New Issue
Block a user