mirror of
https://github.com/joel16/android_kernel_sony_msm8994.git
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[ARM] 4370/3: AT91: Support for Atmel AT91SAM9RL processors.
Add support for Atmel's new AT91SAM9RL range of processors. Includes similar peripherals as other AT91SAM9 processors, but with a High-speed USB controller and various sizes of internal SRAM. Signed-off-by: Nicolas Ferre <nicolas.ferre@rfo.atmel.com> Signed-off-by: Andrew Victor <andrew@sanpeople.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Andrew Victor
Russell King
parent
9da7cf23a4
commit
877d7720f5
@ -17,6 +17,9 @@ config ARCH_AT91SAM9261
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config ARCH_AT91SAM9263
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bool "AT91SAM9263"
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config ARCH_AT91SAM9RL
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bool "AT91SAM9RL"
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endchoice
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# ----------------------------------------------------------
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@ -14,6 +14,7 @@ obj-$(CONFIG_ARCH_AT91RM9200) += at91rm9200.o at91rm9200_time.o at91rm9200_devic
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obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o
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obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o
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obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o at91sam9263_devices.o
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obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o
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# AT91RM9200 board-specific support
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obj-$(CONFIG_MACH_ONEARM) += board-1arm.o
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341
arch/arm/mach-at91/at91sam9rl.c
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341
arch/arm/mach-at91/at91sam9rl.c
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@ -0,0 +1,341 @@
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/*
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* arch/arm/mach-at91/at91sam9rl.c
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*
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* Copyright (C) 2005 SAN People
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* Copyright (C) 2007 Atmel Corporation
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file COPYING in the main directory of this archive for
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* more details.
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*/
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#include <linux/module.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/at91sam9rl.h>
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#include <asm/arch/at91_pmc.h>
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#include <asm/arch/at91_rstc.h>
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#include "generic.h"
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#include "clock.h"
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static struct map_desc at91sam9rl_io_desc[] __initdata = {
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{
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.virtual = AT91_VA_BASE_SYS,
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.pfn = __phys_to_pfn(AT91_BASE_SYS),
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.length = SZ_16K,
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.type = MT_DEVICE,
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},
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};
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static struct map_desc at91sam9rl_sram_desc[] __initdata = {
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{
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.pfn = __phys_to_pfn(AT91SAM9RL_SRAM_BASE),
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.type = MT_DEVICE,
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}
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};
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/* --------------------------------------------------------------------
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* Clocks
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* -------------------------------------------------------------------- */
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/*
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* The peripheral clocks.
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*/
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static struct clk pioA_clk = {
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.name = "pioA_clk",
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.pmc_mask = 1 << AT91SAM9RL_ID_PIOA,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk pioB_clk = {
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.name = "pioB_clk",
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.pmc_mask = 1 << AT91SAM9RL_ID_PIOB,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk pioC_clk = {
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.name = "pioC_clk",
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.pmc_mask = 1 << AT91SAM9RL_ID_PIOC,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk pioD_clk = {
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.name = "pioD_clk",
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.pmc_mask = 1 << AT91SAM9RL_ID_PIOD,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk usart0_clk = {
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.name = "usart0_clk",
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.pmc_mask = 1 << AT91SAM9RL_ID_US0,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk usart1_clk = {
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.name = "usart1_clk",
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.pmc_mask = 1 << AT91SAM9RL_ID_US1,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk usart2_clk = {
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.name = "usart2_clk",
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.pmc_mask = 1 << AT91SAM9RL_ID_US2,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk usart3_clk = {
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.name = "usart3_clk",
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.pmc_mask = 1 << AT91SAM9RL_ID_US3,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk mmc_clk = {
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.name = "mci_clk",
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.pmc_mask = 1 << AT91SAM9RL_ID_MCI,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk twi0_clk = {
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.name = "twi0_clk",
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.pmc_mask = 1 << AT91SAM9RL_ID_TWI0,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk twi1_clk = {
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.name = "twi1_clk",
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.pmc_mask = 1 << AT91SAM9RL_ID_TWI1,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk spi_clk = {
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.name = "spi_clk",
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.pmc_mask = 1 << AT91SAM9RL_ID_SPI,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk ssc0_clk = {
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.name = "ssc0_clk",
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.pmc_mask = 1 << AT91SAM9RL_ID_SSC0,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk ssc1_clk = {
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.name = "ssc1_clk",
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.pmc_mask = 1 << AT91SAM9RL_ID_SSC1,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk tc0_clk = {
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.name = "tc0_clk",
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.pmc_mask = 1 << AT91SAM9RL_ID_TC0,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk tc1_clk = {
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.name = "tc1_clk",
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.pmc_mask = 1 << AT91SAM9RL_ID_TC1,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk tc2_clk = {
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.name = "tc2_clk",
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.pmc_mask = 1 << AT91SAM9RL_ID_TC2,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk pwmc_clk = {
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.name = "pwmc_clk",
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.pmc_mask = 1 << AT91SAM9RL_ID_PWMC,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk tsc_clk = {
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.name = "tsc_clk",
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.pmc_mask = 1 << AT91SAM9RL_ID_TSC,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk dma_clk = {
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.name = "dma_clk",
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.pmc_mask = 1 << AT91SAM9RL_ID_DMA,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk udphs_clk = {
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.name = "udphs_clk",
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.pmc_mask = 1 << AT91SAM9RL_ID_UDPHS,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk lcdc_clk = {
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.name = "lcdc_clk",
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.pmc_mask = 1 << AT91SAM9RL_ID_LCDC,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk ac97_clk = {
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.name = "ac97_clk",
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.pmc_mask = 1 << AT91SAM9RL_ID_AC97C,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk *periph_clocks[] __initdata = {
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&pioA_clk,
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&pioB_clk,
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&pioC_clk,
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&pioD_clk,
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&usart0_clk,
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&usart1_clk,
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&usart2_clk,
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&usart3_clk,
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&mmc_clk,
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&twi0_clk,
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&twi1_clk,
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&spi_clk,
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&ssc0_clk,
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&ssc1_clk,
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&tc0_clk,
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&tc1_clk,
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&tc2_clk,
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&pwmc_clk,
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&tsc_clk,
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&dma_clk,
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&udphs_clk,
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&lcdc_clk,
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&ac97_clk,
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// irq0
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};
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/*
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* The two programmable clocks.
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* You must configure pin multiplexing to bring these signals out.
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*/
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static struct clk pck0 = {
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.name = "pck0",
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.pmc_mask = AT91_PMC_PCK0,
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.type = CLK_TYPE_PROGRAMMABLE,
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.id = 0,
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};
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static struct clk pck1 = {
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.name = "pck1",
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.pmc_mask = AT91_PMC_PCK1,
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.type = CLK_TYPE_PROGRAMMABLE,
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.id = 1,
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};
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static void __init at91sam9rl_register_clocks(void)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
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clk_register(periph_clocks[i]);
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clk_register(&pck0);
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clk_register(&pck1);
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}
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/* --------------------------------------------------------------------
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* GPIO
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* -------------------------------------------------------------------- */
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static struct at91_gpio_bank at91sam9rl_gpio[] = {
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{
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.id = AT91SAM9RL_ID_PIOA,
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.offset = AT91_PIOA,
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.clock = &pioA_clk,
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}, {
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.id = AT91SAM9RL_ID_PIOB,
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.offset = AT91_PIOB,
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.clock = &pioB_clk,
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}, {
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.id = AT91SAM9RL_ID_PIOC,
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.offset = AT91_PIOC,
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.clock = &pioC_clk,
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}, {
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.id = AT91SAM9RL_ID_PIOD,
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.offset = AT91_PIOD,
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.clock = &pioD_clk,
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}
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};
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static void at91sam9rl_reset(void)
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{
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at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
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}
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/* --------------------------------------------------------------------
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* AT91SAM9RL processor initialization
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* -------------------------------------------------------------------- */
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void __init at91sam9rl_initialize(unsigned long main_clock)
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{
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unsigned long cidr, sram_size;
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/* Map peripherals */
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iotable_init(at91sam9rl_io_desc, ARRAY_SIZE(at91sam9rl_io_desc));
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cidr = at91_sys_read(AT91_DBGU_CIDR);
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switch (cidr & AT91_CIDR_SRAMSIZ) {
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case AT91_CIDR_SRAMSIZ_32K:
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sram_size = 2 * SZ_16K;
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break;
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case AT91_CIDR_SRAMSIZ_16K:
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default:
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sram_size = SZ_16K;
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}
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at91sam9rl_sram_desc->virtual = AT91_IO_VIRT_BASE - sram_size;
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at91sam9rl_sram_desc->length = sram_size;
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/* Map SRAM */
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iotable_init(at91sam9rl_sram_desc, ARRAY_SIZE(at91sam9rl_sram_desc));
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at91_arch_reset = at91sam9rl_reset;
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at91_extern_irq = (1 << AT91SAM9RL_ID_IRQ0);
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/* Init clock subsystem */
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at91_clock_init(main_clock);
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/* Register the processor-specific clocks */
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at91sam9rl_register_clocks();
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/* Register GPIO subsystem */
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at91_gpio_init(at91sam9rl_gpio, 4);
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}
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/* --------------------------------------------------------------------
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* Interrupt initialization
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* -------------------------------------------------------------------- */
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/*
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* The default interrupt priority levels (0 = lowest, 7 = highest).
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*/
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static unsigned int at91sam9rl_default_irq_priority[NR_AIC_IRQS] __initdata = {
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7, /* Advanced Interrupt Controller */
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7, /* System Peripherals */
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1, /* Parallel IO Controller A */
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1, /* Parallel IO Controller B */
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1, /* Parallel IO Controller C */
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1, /* Parallel IO Controller D */
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5, /* USART 0 */
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5, /* USART 1 */
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5, /* USART 2 */
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5, /* USART 3 */
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0, /* Multimedia Card Interface */
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6, /* Two-Wire Interface 0 */
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6, /* Two-Wire Interface 1 */
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5, /* Serial Peripheral Interface */
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4, /* Serial Synchronous Controller 0 */
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4, /* Serial Synchronous Controller 1 */
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0, /* Timer Counter 0 */
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0, /* Timer Counter 1 */
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0, /* Timer Counter 2 */
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0,
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0, /* Touch Screen Controller */
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0, /* DMA Controller */
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2, /* USB Device High speed port */
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2, /* LCD Controller */
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6, /* AC97 Controller */
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0,
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0,
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0,
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0,
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0,
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0,
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0, /* Advanced Interrupt Controller */
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};
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void __init at91sam9rl_init_interrupts(unsigned int priority[NR_AIC_IRQS])
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{
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if (!priority)
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priority = at91sam9rl_default_irq_priority;
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/* Initialize the AIC interrupt controller */
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at91_aic_init(priority);
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/* Enable GPIO interrupts */
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at91_gpio_irq_setup();
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}
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634
arch/arm/mach-at91/at91sam9rl_devices.c
Normal file
634
arch/arm/mach-at91/at91sam9rl_devices.c
Normal file
@ -0,0 +1,634 @@
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/*
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* Copyright (C) 2007 Atmel Corporation
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file COPYING in the main directory of this archive for
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* more details.
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*/
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <linux/platform_device.h>
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#include <linux/fb.h>
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#include <video/atmel_lcdc.h>
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#include <asm/arch/board.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/at91sam9rl.h>
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#include <asm/arch/at91sam9rl_matrix.h>
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#include <asm/arch/at91sam926x_mc.h>
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#include "generic.h"
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#define SZ_512 0x00000200
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#define SZ_256 0x00000100
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#define SZ_16 0x00000010
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/* --------------------------------------------------------------------
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* MMC / SD
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* -------------------------------------------------------------------- */
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#if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
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static u64 mmc_dmamask = 0xffffffffUL;
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static struct at91_mmc_data mmc_data;
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static struct resource mmc_resources[] = {
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[0] = {
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.start = AT91SAM9RL_BASE_MCI,
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.end = AT91SAM9RL_BASE_MCI + SZ_16K - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = AT91SAM9RL_ID_MCI,
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.end = AT91SAM9RL_ID_MCI,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device at91sam9rl_mmc_device = {
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.name = "at91_mci",
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.id = -1,
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.dev = {
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.dma_mask = &mmc_dmamask,
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.coherent_dma_mask = 0xffffffff,
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.platform_data = &mmc_data,
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},
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.resource = mmc_resources,
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.num_resources = ARRAY_SIZE(mmc_resources),
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};
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void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
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{
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if (!data)
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return;
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/* input/irq */
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if (data->det_pin) {
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at91_set_gpio_input(data->det_pin, 1);
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at91_set_deglitch(data->det_pin, 1);
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}
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if (data->wp_pin)
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at91_set_gpio_input(data->wp_pin, 1);
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if (data->vcc_pin)
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at91_set_gpio_output(data->vcc_pin, 0);
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/* CLK */
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at91_set_A_periph(AT91_PIN_PA2, 0);
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/* CMD */
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at91_set_A_periph(AT91_PIN_PA1, 1);
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/* DAT0, maybe DAT1..DAT3 */
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at91_set_A_periph(AT91_PIN_PA0, 1);
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if (data->wire4) {
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at91_set_A_periph(AT91_PIN_PA3, 1);
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at91_set_A_periph(AT91_PIN_PA4, 1);
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at91_set_A_periph(AT91_PIN_PA5, 1);
|
||||
}
|
||||
|
||||
mmc_data = *data;
|
||||
platform_device_register(&at91sam9rl_mmc_device);
|
||||
}
|
||||
#else
|
||||
void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
|
||||
#endif
|
||||
|
||||
|
||||
/* --------------------------------------------------------------------
|
||||
* NAND / SmartMedia
|
||||
* -------------------------------------------------------------------- */
|
||||
|
||||
#if defined(CONFIG_MTD_NAND_AT91) || defined(CONFIG_MTD_NAND_AT91_MODULE)
|
||||
static struct at91_nand_data nand_data;
|
||||
|
||||
#define NAND_BASE AT91_CHIPSELECT_3
|
||||
|
||||
static struct resource nand_resources[] = {
|
||||
{
|
||||
.start = NAND_BASE,
|
||||
.end = NAND_BASE + SZ_256M - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
}
|
||||
};
|
||||
|
||||
static struct platform_device at91_nand_device = {
|
||||
.name = "at91_nand",
|
||||
.id = -1,
|
||||
.dev = {
|
||||
.platform_data = &nand_data,
|
||||
},
|
||||
.resource = nand_resources,
|
||||
.num_resources = ARRAY_SIZE(nand_resources),
|
||||
};
|
||||
|
||||
void __init at91_add_device_nand(struct at91_nand_data *data)
|
||||
{
|
||||
unsigned long csa;
|
||||
|
||||
if (!data)
|
||||
return;
|
||||
|
||||
csa = at91_sys_read(AT91_MATRIX_EBICSA);
|
||||
at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
|
||||
|
||||
/* set the bus interface characteristics */
|
||||
at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0)
|
||||
| AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
|
||||
|
||||
at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(2) | AT91_SMC_NCS_WRPULSE_(5)
|
||||
| AT91_SMC_NRDPULSE_(2) | AT91_SMC_NCS_RDPULSE_(5));
|
||||
|
||||
at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(7));
|
||||
|
||||
at91_sys_write(AT91_SMC_MODE(3), AT91_SMC_DBW_8 | AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(1));
|
||||
|
||||
/* enable pin */
|
||||
if (data->enable_pin)
|
||||
at91_set_gpio_output(data->enable_pin, 1);
|
||||
|
||||
/* ready/busy pin */
|
||||
if (data->rdy_pin)
|
||||
at91_set_gpio_input(data->rdy_pin, 1);
|
||||
|
||||
/* card detect pin */
|
||||
if (data->det_pin)
|
||||
at91_set_gpio_input(data->det_pin, 1);
|
||||
|
||||
at91_set_A_periph(AT91_PIN_PB4, 0); /* NANDOE */
|
||||
at91_set_A_periph(AT91_PIN_PB5, 0); /* NANDWE */
|
||||
|
||||
nand_data = *data;
|
||||
platform_device_register(&at91_nand_device);
|
||||
}
|
||||
|
||||
#else
|
||||
void __init at91_add_device_nand(struct at91_nand_data *data) {}
|
||||
#endif
|
||||
|
||||
|
||||
/* --------------------------------------------------------------------
|
||||
* TWI (i2c)
|
||||
* -------------------------------------------------------------------- */
|
||||
|
||||
#if defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
|
||||
|
||||
static struct resource twi_resources[] = {
|
||||
[0] = {
|
||||
.start = AT91SAM9RL_BASE_TWI0,
|
||||
.end = AT91SAM9RL_BASE_TWI0 + SZ_16K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = AT91SAM9RL_ID_TWI0,
|
||||
.end = AT91SAM9RL_ID_TWI0,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device at91sam9rl_twi_device = {
|
||||
.name = "at91_i2c",
|
||||
.id = -1,
|
||||
.resource = twi_resources,
|
||||
.num_resources = ARRAY_SIZE(twi_resources),
|
||||
};
|
||||
|
||||
void __init at91_add_device_i2c(void)
|
||||
{
|
||||
/* pins used for TWI interface */
|
||||
at91_set_A_periph(AT91_PIN_PA23, 0); /* TWD */
|
||||
at91_set_multi_drive(AT91_PIN_PA23, 1);
|
||||
|
||||
at91_set_A_periph(AT91_PIN_PA24, 0); /* TWCK */
|
||||
at91_set_multi_drive(AT91_PIN_PA24, 1);
|
||||
|
||||
platform_device_register(&at91sam9rl_twi_device);
|
||||
}
|
||||
#else
|
||||
void __init at91_add_device_i2c(void) {}
|
||||
#endif
|
||||
|
||||
|
||||
/* --------------------------------------------------------------------
|
||||
* SPI
|
||||
* -------------------------------------------------------------------- */
|
||||
|
||||
#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
|
||||
static u64 spi_dmamask = 0xffffffffUL;
|
||||
|
||||
static struct resource spi_resources[] = {
|
||||
[0] = {
|
||||
.start = AT91SAM9RL_BASE_SPI,
|
||||
.end = AT91SAM9RL_BASE_SPI + SZ_16K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = AT91SAM9RL_ID_SPI,
|
||||
.end = AT91SAM9RL_ID_SPI,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device at91sam9rl_spi_device = {
|
||||
.name = "atmel_spi",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.dma_mask = &spi_dmamask,
|
||||
.coherent_dma_mask = 0xffffffff,
|
||||
},
|
||||
.resource = spi_resources,
|
||||
.num_resources = ARRAY_SIZE(spi_resources),
|
||||
};
|
||||
|
||||
static const unsigned spi_standard_cs[4] = { AT91_PIN_PA28, AT91_PIN_PB7, AT91_PIN_PD8, AT91_PIN_PD9 };
|
||||
|
||||
|
||||
void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
|
||||
{
|
||||
int i;
|
||||
unsigned long cs_pin;
|
||||
|
||||
at91_set_A_periph(AT91_PIN_PA25, 0); /* MISO */
|
||||
at91_set_A_periph(AT91_PIN_PA26, 0); /* MOSI */
|
||||
at91_set_A_periph(AT91_PIN_PA27, 0); /* SPCK */
|
||||
|
||||
/* Enable SPI chip-selects */
|
||||
for (i = 0; i < nr_devices; i++) {
|
||||
if (devices[i].controller_data)
|
||||
cs_pin = (unsigned long) devices[i].controller_data;
|
||||
else
|
||||
cs_pin = spi_standard_cs[devices[i].chip_select];
|
||||
|
||||
/* enable chip-select pin */
|
||||
at91_set_gpio_output(cs_pin, 1);
|
||||
|
||||
/* pass chip-select pin to driver */
|
||||
devices[i].controller_data = (void *) cs_pin;
|
||||
}
|
||||
|
||||
spi_register_board_info(devices, nr_devices);
|
||||
platform_device_register(&at91sam9rl_spi_device);
|
||||
}
|
||||
#else
|
||||
void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
|
||||
#endif
|
||||
|
||||
|
||||
/* --------------------------------------------------------------------
|
||||
* LCD Controller
|
||||
* -------------------------------------------------------------------- */
|
||||
|
||||
#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
|
||||
static u64 lcdc_dmamask = 0xffffffffUL;
|
||||
static struct atmel_lcdfb_info lcdc_data;
|
||||
|
||||
static struct resource lcdc_resources[] = {
|
||||
[0] = {
|
||||
.start = AT91SAM9RL_LCDC_BASE,
|
||||
.end = AT91SAM9RL_LCDC_BASE + SZ_4K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = AT91SAM9RL_ID_LCDC,
|
||||
.end = AT91SAM9RL_ID_LCDC,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
#if defined(CONFIG_FB_INTSRAM)
|
||||
[2] = {
|
||||
.start = AT91SAM9RL_SRAM_BASE,
|
||||
.end = AT91SAM9RL_SRAM_BASE + AT91SAM9RL_SRAM_SIZE - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
#endif
|
||||
};
|
||||
|
||||
static struct platform_device at91_lcdc_device = {
|
||||
.name = "atmel_lcdfb",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.dma_mask = &lcdc_dmamask,
|
||||
.coherent_dma_mask = 0xffffffff,
|
||||
.platform_data = &lcdc_data,
|
||||
},
|
||||
.resource = lcdc_resources,
|
||||
.num_resources = ARRAY_SIZE(lcdc_resources),
|
||||
};
|
||||
|
||||
void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
|
||||
{
|
||||
if (!data) {
|
||||
return;
|
||||
}
|
||||
|
||||
at91_set_B_periph(AT91_PIN_PC1, 0); /* LCDPWR */
|
||||
at91_set_A_periph(AT91_PIN_PC5, 0); /* LCDHSYNC */
|
||||
at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDDOTCK */
|
||||
at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDDEN */
|
||||
at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDCC */
|
||||
at91_set_B_periph(AT91_PIN_PC9, 0); /* LCDD3 */
|
||||
at91_set_B_periph(AT91_PIN_PC10, 0); /* LCDD4 */
|
||||
at91_set_B_periph(AT91_PIN_PC11, 0); /* LCDD5 */
|
||||
at91_set_B_periph(AT91_PIN_PC12, 0); /* LCDD6 */
|
||||
at91_set_B_periph(AT91_PIN_PC13, 0); /* LCDD7 */
|
||||
at91_set_B_periph(AT91_PIN_PC15, 0); /* LCDD11 */
|
||||
at91_set_B_periph(AT91_PIN_PC16, 0); /* LCDD12 */
|
||||
at91_set_B_periph(AT91_PIN_PC17, 0); /* LCDD13 */
|
||||
at91_set_B_periph(AT91_PIN_PC18, 0); /* LCDD14 */
|
||||
at91_set_B_periph(AT91_PIN_PC19, 0); /* LCDD15 */
|
||||
at91_set_B_periph(AT91_PIN_PC20, 0); /* LCDD18 */
|
||||
at91_set_B_periph(AT91_PIN_PC21, 0); /* LCDD19 */
|
||||
at91_set_B_periph(AT91_PIN_PC22, 0); /* LCDD20 */
|
||||
at91_set_B_periph(AT91_PIN_PC23, 0); /* LCDD21 */
|
||||
at91_set_B_periph(AT91_PIN_PC24, 0); /* LCDD22 */
|
||||
at91_set_B_periph(AT91_PIN_PC25, 0); /* LCDD23 */
|
||||
|
||||
lcdc_data = *data;
|
||||
platform_device_register(&at91_lcdc_device);
|
||||
}
|
||||
#else
|
||||
void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
|
||||
#endif
|
||||
|
||||
|
||||
/* --------------------------------------------------------------------
|
||||
* LEDs
|
||||
* -------------------------------------------------------------------- */
|
||||
|
||||
#if defined(CONFIG_LEDS)
|
||||
u8 at91_leds_cpu;
|
||||
u8 at91_leds_timer;
|
||||
|
||||
void __init at91_init_leds(u8 cpu_led, u8 timer_led)
|
||||
{
|
||||
/* Enable GPIO to access the LEDs */
|
||||
at91_set_gpio_output(cpu_led, 1);
|
||||
at91_set_gpio_output(timer_led, 1);
|
||||
|
||||
at91_leds_cpu = cpu_led;
|
||||
at91_leds_timer = timer_led;
|
||||
}
|
||||
#else
|
||||
void __init at91_init_leds(u8 cpu_led, u8 timer_led) {}
|
||||
#endif
|
||||
|
||||
|
||||
/* --------------------------------------------------------------------
|
||||
* UART
|
||||
* -------------------------------------------------------------------- */
|
||||
|
||||
#if defined(CONFIG_SERIAL_ATMEL)
|
||||
static struct resource dbgu_resources[] = {
|
||||
[0] = {
|
||||
.start = AT91_VA_BASE_SYS + AT91_DBGU,
|
||||
.end = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = AT91_ID_SYS,
|
||||
.end = AT91_ID_SYS,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct atmel_uart_data dbgu_data = {
|
||||
.use_dma_tx = 0,
|
||||
.use_dma_rx = 0, /* DBGU not capable of receive DMA */
|
||||
.regs = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU),
|
||||
};
|
||||
|
||||
static struct platform_device at91sam9rl_dbgu_device = {
|
||||
.name = "atmel_usart",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = &dbgu_data,
|
||||
.coherent_dma_mask = 0xffffffff,
|
||||
},
|
||||
.resource = dbgu_resources,
|
||||
.num_resources = ARRAY_SIZE(dbgu_resources),
|
||||
};
|
||||
|
||||
static inline void configure_dbgu_pins(void)
|
||||
{
|
||||
at91_set_A_periph(AT91_PIN_PA21, 0); /* DRXD */
|
||||
at91_set_A_periph(AT91_PIN_PA22, 1); /* DTXD */
|
||||
}
|
||||
|
||||
static struct resource uart0_resources[] = {
|
||||
[0] = {
|
||||
.start = AT91SAM9RL_BASE_US0,
|
||||
.end = AT91SAM9RL_BASE_US0 + SZ_16K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = AT91SAM9RL_ID_US0,
|
||||
.end = AT91SAM9RL_ID_US0,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct atmel_uart_data uart0_data = {
|
||||
.use_dma_tx = 1,
|
||||
.use_dma_rx = 1,
|
||||
};
|
||||
|
||||
static struct platform_device at91sam9rl_uart0_device = {
|
||||
.name = "atmel_usart",
|
||||
.id = 1,
|
||||
.dev = {
|
||||
.platform_data = &uart0_data,
|
||||
.coherent_dma_mask = 0xffffffff,
|
||||
},
|
||||
.resource = uart0_resources,
|
||||
.num_resources = ARRAY_SIZE(uart0_resources),
|
||||
};
|
||||
|
||||
static inline void configure_usart0_pins(void)
|
||||
{
|
||||
at91_set_A_periph(AT91_PIN_PA6, 1); /* TXD0 */
|
||||
at91_set_A_periph(AT91_PIN_PA7, 0); /* RXD0 */
|
||||
at91_set_A_periph(AT91_PIN_PA9, 0); /* RTS0 */
|
||||
at91_set_A_periph(AT91_PIN_PA10, 0); /* CTS0 */
|
||||
}
|
||||
|
||||
static struct resource uart1_resources[] = {
|
||||
[0] = {
|
||||
.start = AT91SAM9RL_BASE_US1,
|
||||
.end = AT91SAM9RL_BASE_US1 + SZ_16K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = AT91SAM9RL_ID_US1,
|
||||
.end = AT91SAM9RL_ID_US1,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct atmel_uart_data uart1_data = {
|
||||
.use_dma_tx = 1,
|
||||
.use_dma_rx = 1,
|
||||
};
|
||||
|
||||
static struct platform_device at91sam9rl_uart1_device = {
|
||||
.name = "atmel_usart",
|
||||
.id = 2,
|
||||
.dev = {
|
||||
.platform_data = &uart1_data,
|
||||
.coherent_dma_mask = 0xffffffff,
|
||||
},
|
||||
.resource = uart1_resources,
|
||||
.num_resources = ARRAY_SIZE(uart1_resources),
|
||||
};
|
||||
|
||||
static inline void configure_usart1_pins(void)
|
||||
{
|
||||
at91_set_A_periph(AT91_PIN_PA11, 1); /* TXD1 */
|
||||
at91_set_A_periph(AT91_PIN_PA12, 0); /* RXD1 */
|
||||
}
|
||||
|
||||
static struct resource uart2_resources[] = {
|
||||
[0] = {
|
||||
.start = AT91SAM9RL_BASE_US2,
|
||||
.end = AT91SAM9RL_BASE_US2 + SZ_16K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = AT91SAM9RL_ID_US2,
|
||||
.end = AT91SAM9RL_ID_US2,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct atmel_uart_data uart2_data = {
|
||||
.use_dma_tx = 1,
|
||||
.use_dma_rx = 1,
|
||||
};
|
||||
|
||||
static struct platform_device at91sam9rl_uart2_device = {
|
||||
.name = "atmel_usart",
|
||||
.id = 3,
|
||||
.dev = {
|
||||
.platform_data = &uart2_data,
|
||||
.coherent_dma_mask = 0xffffffff,
|
||||
},
|
||||
.resource = uart2_resources,
|
||||
.num_resources = ARRAY_SIZE(uart2_resources),
|
||||
};
|
||||
|
||||
static inline void configure_usart2_pins(void)
|
||||
{
|
||||
at91_set_A_periph(AT91_PIN_PA13, 1); /* TXD2 */
|
||||
at91_set_A_periph(AT91_PIN_PA14, 0); /* RXD2 */
|
||||
}
|
||||
|
||||
static struct resource uart3_resources[] = {
|
||||
[0] = {
|
||||
.start = AT91SAM9RL_BASE_US3,
|
||||
.end = AT91SAM9RL_BASE_US3 + SZ_16K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = AT91SAM9RL_ID_US3,
|
||||
.end = AT91SAM9RL_ID_US3,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct atmel_uart_data uart3_data = {
|
||||
.use_dma_tx = 1,
|
||||
.use_dma_rx = 1,
|
||||
};
|
||||
|
||||
static struct platform_device at91sam9rl_uart3_device = {
|
||||
.name = "atmel_usart",
|
||||
.id = 4,
|
||||
.dev = {
|
||||
.platform_data = &uart3_data,
|
||||
.coherent_dma_mask = 0xffffffff,
|
||||
},
|
||||
.resource = uart3_resources,
|
||||
.num_resources = ARRAY_SIZE(uart3_resources),
|
||||
};
|
||||
|
||||
static inline void configure_usart3_pins(void)
|
||||
{
|
||||
at91_set_A_periph(AT91_PIN_PB0, 1); /* TXD3 */
|
||||
at91_set_A_periph(AT91_PIN_PB1, 0); /* RXD3 */
|
||||
}
|
||||
|
||||
struct platform_device *at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
|
||||
struct platform_device *atmel_default_console_device; /* the serial console device */
|
||||
|
||||
void __init at91_init_serial(struct at91_uart_config *config)
|
||||
{
|
||||
int i;
|
||||
|
||||
/* Fill in list of supported UARTs */
|
||||
for (i = 0; i < config->nr_tty; i++) {
|
||||
switch (config->tty_map[i]) {
|
||||
case 0:
|
||||
configure_usart0_pins();
|
||||
at91_uarts[i] = &at91sam9rl_uart0_device;
|
||||
at91_clock_associate("usart0_clk", &at91sam9rl_uart0_device.dev, "usart");
|
||||
break;
|
||||
case 1:
|
||||
configure_usart1_pins();
|
||||
at91_uarts[i] = &at91sam9rl_uart1_device;
|
||||
at91_clock_associate("usart1_clk", &at91sam9rl_uart1_device.dev, "usart");
|
||||
break;
|
||||
case 2:
|
||||
configure_usart2_pins();
|
||||
at91_uarts[i] = &at91sam9rl_uart2_device;
|
||||
at91_clock_associate("usart2_clk", &at91sam9rl_uart2_device.dev, "usart");
|
||||
break;
|
||||
case 3:
|
||||
configure_usart3_pins();
|
||||
at91_uarts[i] = &at91sam9rl_uart3_device;
|
||||
at91_clock_associate("usart3_clk", &at91sam9rl_uart3_device.dev, "usart");
|
||||
break;
|
||||
case 4:
|
||||
configure_dbgu_pins();
|
||||
at91_uarts[i] = &at91sam9rl_dbgu_device;
|
||||
at91_clock_associate("mck", &at91sam9rl_dbgu_device.dev, "usart");
|
||||
break;
|
||||
default:
|
||||
continue;
|
||||
}
|
||||
at91_uarts[i]->id = i; /* update ID number to mapped ID */
|
||||
}
|
||||
|
||||
/* Set serial console device */
|
||||
if (config->console_tty < ATMEL_MAX_UART)
|
||||
atmel_default_console_device = at91_uarts[config->console_tty];
|
||||
if (!atmel_default_console_device)
|
||||
printk(KERN_INFO "AT91: No default serial console defined.\n");
|
||||
}
|
||||
|
||||
void __init at91_add_device_serial(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ATMEL_MAX_UART; i++) {
|
||||
if (at91_uarts[i])
|
||||
platform_device_register(at91_uarts[i]);
|
||||
}
|
||||
}
|
||||
#else
|
||||
void __init at91_init_serial(struct at91_uart_config *config) {}
|
||||
void __init at91_add_device_serial(void) {}
|
||||
#endif
|
||||
|
||||
|
||||
/* -------------------------------------------------------------------- */
|
||||
|
||||
/*
|
||||
* These devices are always present and don't need any board-specific
|
||||
* setup.
|
||||
*/
|
||||
static int __init at91_add_standard_devices(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
arch_initcall(at91_add_standard_devices);
|
||||
@ -13,12 +13,14 @@ extern void __init at91rm9200_initialize(unsigned long main_clock, unsigned shor
|
||||
extern void __init at91sam9260_initialize(unsigned long main_clock);
|
||||
extern void __init at91sam9261_initialize(unsigned long main_clock);
|
||||
extern void __init at91sam9263_initialize(unsigned long main_clock);
|
||||
extern void __init at91sam9rl_initialize(unsigned long main_clock);
|
||||
|
||||
/* Interrupts */
|
||||
extern void __init at91rm9200_init_interrupts(unsigned int priority[]);
|
||||
extern void __init at91sam9260_init_interrupts(unsigned int priority[]);
|
||||
extern void __init at91sam9261_init_interrupts(unsigned int priority[]);
|
||||
extern void __init at91sam9263_init_interrupts(unsigned int priority[]);
|
||||
extern void __init at91sam9rl_init_interrupts(unsigned int priority[]);
|
||||
extern void __init at91_aic_init(unsigned int priority[]);
|
||||
|
||||
/* Timer */
|
||||
|
||||
@ -171,8 +171,8 @@ config CPU_ARM925T
|
||||
# ARM926T
|
||||
config CPU_ARM926T
|
||||
bool "Support ARM926T processor"
|
||||
depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || MACH_REALVIEW_EB || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_NS9XXX || ARCH_DAVINCI
|
||||
default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_NS9XXX || ARCH_DAVINCI
|
||||
depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || MACH_REALVIEW_EB || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_NS9XXX || ARCH_DAVINCI
|
||||
default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_NS9XXX || ARCH_DAVINCI
|
||||
select CPU_32v5
|
||||
select CPU_ABRT_EV5TJ
|
||||
select CPU_CACHE_VIVT
|
||||
|
||||
@ -210,7 +210,7 @@ config USB_OTG
|
||||
|
||||
config USB_GADGET_AT91
|
||||
boolean "AT91 USB Device Port"
|
||||
depends on ARCH_AT91
|
||||
depends on ARCH_AT91 && !ARCH_AT91SAM9RL
|
||||
select USB_GADGET_SELECTED
|
||||
help
|
||||
Many Atmel AT91 processors (such as the AT91RM2000) have a
|
||||
|
||||
110
include/asm-arm/arch-at91/at91sam9rl.h
Normal file
110
include/asm-arm/arch-at91/at91sam9rl.h
Normal file
@ -0,0 +1,110 @@
|
||||
/*
|
||||
* include/asm-arm/arch-at91/at91sam9260.h
|
||||
*
|
||||
* Copyright (C) 2007 Atmel Corporation
|
||||
*
|
||||
* Common definitions.
|
||||
* Based on AT91SAM9RL datasheet revision A. (Preliminary)
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file COPYING in the main directory of this archive for
|
||||
* more details.
|
||||
*/
|
||||
|
||||
#ifndef AT91SAM9RL_H
|
||||
#define AT91SAM9RL_H
|
||||
|
||||
/*
|
||||
* Peripheral identifiers/interrupts.
|
||||
*/
|
||||
#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
|
||||
#define AT91_ID_SYS 1 /* System Controller */
|
||||
#define AT91SAM9RL_ID_PIOA 2 /* Parallel IO Controller A */
|
||||
#define AT91SAM9RL_ID_PIOB 3 /* Parallel IO Controller B */
|
||||
#define AT91SAM9RL_ID_PIOC 4 /* Parallel IO Controller C */
|
||||
#define AT91SAM9RL_ID_PIOD 5 /* Parallel IO Controller D */
|
||||
#define AT91SAM9RL_ID_US0 6 /* USART 0 */
|
||||
#define AT91SAM9RL_ID_US1 7 /* USART 1 */
|
||||
#define AT91SAM9RL_ID_US2 8 /* USART 2 */
|
||||
#define AT91SAM9RL_ID_US3 9 /* USART 3 */
|
||||
#define AT91SAM9RL_ID_MCI 10 /* Multimedia Card Interface */
|
||||
#define AT91SAM9RL_ID_TWI0 11 /* TWI 0 */
|
||||
#define AT91SAM9RL_ID_TWI1 12 /* TWI 1 */
|
||||
#define AT91SAM9RL_ID_SPI 13 /* Serial Peripheral Interface */
|
||||
#define AT91SAM9RL_ID_SSC0 14 /* Serial Synchronous Controller 0 */
|
||||
#define AT91SAM9RL_ID_SSC1 15 /* Serial Synchronous Controller 1 */
|
||||
#define AT91SAM9RL_ID_TC0 16 /* Timer Counter 0 */
|
||||
#define AT91SAM9RL_ID_TC1 17 /* Timer Counter 1 */
|
||||
#define AT91SAM9RL_ID_TC2 18 /* Timer Counter 2 */
|
||||
#define AT91SAM9RL_ID_PWMC 19 /* Pulse Width Modulation Controller */
|
||||
#define AT91SAM9RL_ID_TSC 20 /* Touch Screen Controller */
|
||||
#define AT91SAM9RL_ID_DMA 21 /* DMA Controller */
|
||||
#define AT91SAM9RL_ID_UDPHS 22 /* USB Device HS */
|
||||
#define AT91SAM9RL_ID_LCDC 23 /* LCD Controller */
|
||||
#define AT91SAM9RL_ID_AC97C 24 /* AC97 Controller */
|
||||
#define AT91SAM9RL_ID_IRQ0 31 /* Advanced Interrupt Controller (IRQ0) */
|
||||
|
||||
|
||||
/*
|
||||
* User Peripheral physical base addresses.
|
||||
*/
|
||||
#define AT91SAM9RL_BASE_TCB0 0xfffa0000
|
||||
#define AT91SAM9RL_BASE_TC0 0xfffa0000
|
||||
#define AT91SAM9RL_BASE_TC1 0xfffa0040
|
||||
#define AT91SAM9RL_BASE_TC2 0xfffa0080
|
||||
#define AT91SAM9RL_BASE_MCI 0xfffa4000
|
||||
#define AT91SAM9RL_BASE_TWI0 0xfffa8000
|
||||
#define AT91SAM9RL_BASE_TWI1 0xfffac000
|
||||
#define AT91SAM9RL_BASE_US0 0xfffb0000
|
||||
#define AT91SAM9RL_BASE_US1 0xfffb4000
|
||||
#define AT91SAM9RL_BASE_US2 0xfffb8000
|
||||
#define AT91SAM9RL_BASE_US3 0xfffbc000
|
||||
#define AT91SAM9RL_BASE_SSC0 0xfffc0000
|
||||
#define AT91SAM9RL_BASE_SSC1 0xfffc4000
|
||||
#define AT91SAM9RL_BASE_PWMC 0xfffc8000
|
||||
#define AT91SAM9RL_BASE_SPI 0xfffcc000
|
||||
#define AT91SAM9RL_BASE_TSC 0xfffd0000
|
||||
#define AT91SAM9RL_BASE_UDPHS 0xfffd4000
|
||||
#define AT91SAM9RL_BASE_AC97C 0xfffd8000
|
||||
#define AT91_BASE_SYS 0xffffc000
|
||||
|
||||
|
||||
/*
|
||||
* System Peripherals (offset from AT91_BASE_SYS)
|
||||
*/
|
||||
#define AT91_DMA (0xffffe600 - AT91_BASE_SYS)
|
||||
#define AT91_ECC (0xffffe800 - AT91_BASE_SYS)
|
||||
#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS)
|
||||
#define AT91_SMC (0xffffec00 - AT91_BASE_SYS)
|
||||
#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
|
||||
#define AT91_CCFG (0xffffef10 - AT91_BASE_SYS)
|
||||
#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
|
||||
#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
|
||||
#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS)
|
||||
#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS)
|
||||
#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS)
|
||||
#define AT91_PIOD (0xfffffa00 - AT91_BASE_SYS)
|
||||
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
|
||||
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
|
||||
#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
|
||||
#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)
|
||||
#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
|
||||
#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
|
||||
#define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS)
|
||||
#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
|
||||
#define AT91_RTC (0xfffffe00 - AT91_BASE_SYS)
|
||||
|
||||
|
||||
/*
|
||||
* Internal Memory.
|
||||
*/
|
||||
#define AT91SAM9RL_SRAM_BASE 0x00300000 /* Internal SRAM base address */
|
||||
#define AT91SAM9RL_SRAM_SIZE SZ_16K /* Internal SRAM size (16Kb) */
|
||||
|
||||
#define AT91SAM9RL_ROM_BASE 0x00400000 /* Internal ROM base address */
|
||||
#define AT91SAM9RL_ROM_SIZE (2 * SZ_16K) /* Internal ROM size (32Kb) */
|
||||
|
||||
#define AT91SAM9RL_LCDC_BASE 0x00500000 /* LCD Controller */
|
||||
#define AT91SAM9RL_UDPHS_BASE 0x00600000 /* USB Device HS controller */
|
||||
|
||||
#endif
|
||||
96
include/asm-arm/arch-at91/at91sam9rl_matrix.h
Normal file
96
include/asm-arm/arch-at91/at91sam9rl_matrix.h
Normal file
@ -0,0 +1,96 @@
|
||||
/*
|
||||
* include/asm-arm/arch-at91/at91sam9rl_matrix.h
|
||||
*
|
||||
* Copyright (C) 2007 Atmel Corporation
|
||||
*
|
||||
* Memory Controllers (MATRIX, EBI) - System peripherals registers.
|
||||
* Based on AT91SAM9RL datasheet revision A. (Preliminary)
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file COPYING in the main directory of this archive for
|
||||
* more details.
|
||||
*/
|
||||
|
||||
#ifndef AT91SAM9RL_MATRIX_H
|
||||
#define AT91SAM9RL_MATRIX_H
|
||||
|
||||
#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */
|
||||
#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */
|
||||
#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */
|
||||
#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */
|
||||
#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */
|
||||
#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */
|
||||
#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
|
||||
#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
|
||||
#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
|
||||
#define AT91_MATRIX_ULBT_FOUR (2 << 0)
|
||||
#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
|
||||
#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
|
||||
|
||||
#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */
|
||||
#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */
|
||||
#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */
|
||||
#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */
|
||||
#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */
|
||||
#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */
|
||||
#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
|
||||
#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */
|
||||
#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */
|
||||
#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
|
||||
#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
|
||||
|
||||
#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */
|
||||
#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */
|
||||
#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */
|
||||
#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */
|
||||
#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */
|
||||
#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */
|
||||
#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
|
||||
#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
|
||||
#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
|
||||
#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
|
||||
#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
|
||||
#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
|
||||
|
||||
#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */
|
||||
#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
|
||||
#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
|
||||
#define AT91_MATRIX_RCB2 (1 << 2)
|
||||
#define AT91_MATRIX_RCB3 (1 << 3)
|
||||
#define AT91_MATRIX_RCB4 (1 << 4)
|
||||
#define AT91_MATRIX_RCB5 (1 << 5)
|
||||
|
||||
#define AT91_MATRIX_TCMR (AT91_MATRIX + 0x114) /* TCM Configuration Register */
|
||||
#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
|
||||
#define AT91_MATRIX_ITCM_0 (0 << 0)
|
||||
#define AT91_MATRIX_ITCM_16 (5 << 0)
|
||||
#define AT91_MATRIX_ITCM_32 (6 << 0)
|
||||
#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */
|
||||
#define AT91_MATRIX_DTCM_0 (0 << 4)
|
||||
#define AT91_MATRIX_DTCM_16 (5 << 4)
|
||||
#define AT91_MATRIX_DTCM_32 (6 << 4)
|
||||
|
||||
#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x120) /* EBI0 Chip Select Assignment Register */
|
||||
#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */
|
||||
#define AT91_MATRIX_CS1A_SMC (0 << 1)
|
||||
#define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
|
||||
#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */
|
||||
#define AT91_MATRIX_CS3A_SMC (0 << 3)
|
||||
#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
|
||||
#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */
|
||||
#define AT91_MATRIX_CS4A_SMC (0 << 4)
|
||||
#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4)
|
||||
#define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */
|
||||
#define AT91_MATRIX_CS5A_SMC (0 << 5)
|
||||
#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5)
|
||||
#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
|
||||
#define AT91_MATRIX_VDDIOMSEL (1 << 16) /* Memory voltage selection */
|
||||
#define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16)
|
||||
#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16)
|
||||
|
||||
|
||||
#endif
|
||||
@ -26,6 +26,8 @@
|
||||
#define ARCH_ID_AT91SAM9XE256 0x329a93a0
|
||||
#define ARCH_ID_AT91SAM9XE512 0x329aa3a0
|
||||
|
||||
#define ARCH_ID_AT91SAM9RL64 0x019b03a0
|
||||
|
||||
static inline unsigned long at91_cpu_identify(void)
|
||||
{
|
||||
return (at91_sys_read(AT91_DBGU_CIDR) & ~AT91_CIDR_VERSION);
|
||||
@ -68,6 +70,13 @@ static inline unsigned long at91_arch_identify(void)
|
||||
#define cpu_is_at91sam9263() (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_AT91SAM9RL
|
||||
#define cpu_is_at91sam9rl() (at91_cpu_identify() == ARCH_ID_AT91SAM9RL64)
|
||||
#else
|
||||
#define cpu_is_at91sam9rl() (0)
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* Since this is ARM, we will never run on any AVR32 CPU. But these
|
||||
* definitions may reduce clutter in common drivers.
|
||||
|
||||
@ -24,6 +24,8 @@
|
||||
#include <asm/arch/at91sam9261.h>
|
||||
#elif defined(CONFIG_ARCH_AT91SAM9263)
|
||||
#include <asm/arch/at91sam9263.h>
|
||||
#elif defined(CONFIG_ARCH_AT91SAM9RL)
|
||||
#include <asm/arch/at91sam9rl.h>
|
||||
#else
|
||||
#error "Unsupported AT91 processor"
|
||||
#endif
|
||||
|
||||
@ -37,6 +37,11 @@
|
||||
#define AT91SAM9_MASTER_CLOCK 99959500
|
||||
#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16)
|
||||
|
||||
#elif defined(CONFIG_ARCH_AT91SAM9RL)
|
||||
|
||||
#define AT91SAM9_MASTER_CLOCK 100000000
|
||||
#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16)
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
@ -29,5 +29,6 @@
|
||||
#define cpu_is_at91sam9260() (0)
|
||||
#define cpu_is_at91sam9261() (0)
|
||||
#define cpu_is_at91sam9263() (0)
|
||||
#define cpu_is_at91sam9rl() (0)
|
||||
|
||||
#endif /* __ASM_ARCH_CPU_H */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user