mirror of
https://github.com/joel16/android_kernel_sony_msm8994.git
synced 2024-12-03 01:41:00 +00:00
Merge branches 'x86/asm', 'x86/debug', 'x86/mm', 'x86/setup', 'x86/urgent' and 'linus' into x86/core
This commit is contained in:
Ingo Molnar
commit
a98fe7f342
@ -686,7 +686,7 @@ CONFIG_SERIAL_UARTLITE_CONSOLE=y
|
||||
CONFIG_SERIAL_CORE=y
|
||||
CONFIG_SERIAL_CORE_CONSOLE=y
|
||||
# CONFIG_SERIAL_JSM is not set
|
||||
# CONFIG_SERIAL_OF_PLATFORM is not set
|
||||
CONFIG_SERIAL_OF_PLATFORM=y
|
||||
# CONFIG_SERIAL_OF_PLATFORM_NWPSERIAL is not set
|
||||
CONFIG_UNIX98_PTYS=y
|
||||
# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
|
||||
|
||||
@ -691,7 +691,7 @@ CONFIG_SERIAL_UARTLITE_CONSOLE=y
|
||||
CONFIG_SERIAL_CORE=y
|
||||
CONFIG_SERIAL_CORE_CONSOLE=y
|
||||
# CONFIG_SERIAL_JSM is not set
|
||||
# CONFIG_SERIAL_OF_PLATFORM is not set
|
||||
CONFIG_SERIAL_OF_PLATFORM=y
|
||||
# CONFIG_SERIAL_OF_PLATFORM_NWPSERIAL is not set
|
||||
CONFIG_UNIX98_PTYS=y
|
||||
# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
|
||||
|
||||
@ -1,7 +1,7 @@
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||||
#
|
||||
# Automatically generated make config: don't edit
|
||||
# Linux kernel version: 2.6.29-rc2
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||||
# Mon Jan 26 15:35:29 2009
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||||
# Linux kernel version: 2.6.29-rc6
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||||
# Fri Mar 6 00:07:38 2009
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||||
#
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||||
# CONFIG_PPC64 is not set
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||||
|
||||
@ -71,6 +71,15 @@ CONFIG_POSIX_MQUEUE=y
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||||
# CONFIG_BSD_PROCESS_ACCT is not set
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||||
# CONFIG_TASKSTATS is not set
|
||||
# CONFIG_AUDIT is not set
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||||
|
||||
#
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||||
# RCU Subsystem
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||||
#
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||||
CONFIG_CLASSIC_RCU=y
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||||
# CONFIG_TREE_RCU is not set
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||||
# CONFIG_PREEMPT_RCU is not set
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||||
# CONFIG_TREE_RCU_TRACE is not set
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||||
# CONFIG_PREEMPT_RCU_TRACE is not set
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||||
CONFIG_IKCONFIG=y
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||||
CONFIG_IKCONFIG_PROC=y
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||||
CONFIG_LOG_BUF_SHIFT=14
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||||
@ -88,6 +97,7 @@ CONFIG_NAMESPACES=y
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||||
# CONFIG_IPC_NS is not set
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||||
# CONFIG_USER_NS is not set
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||||
# CONFIG_PID_NS is not set
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||||
# CONFIG_NET_NS is not set
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||||
CONFIG_BLK_DEV_INITRD=y
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||||
CONFIG_INITRAMFS_SOURCE=""
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||||
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
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||||
@ -153,11 +163,6 @@ CONFIG_DEFAULT_AS=y
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||||
# CONFIG_DEFAULT_CFQ is not set
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||||
# CONFIG_DEFAULT_NOOP is not set
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||||
CONFIG_DEFAULT_IOSCHED="anticipatory"
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||||
CONFIG_CLASSIC_RCU=y
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||||
# CONFIG_TREE_RCU is not set
|
||||
# CONFIG_PREEMPT_RCU is not set
|
||||
# CONFIG_TREE_RCU_TRACE is not set
|
||||
# CONFIG_PREEMPT_RCU_TRACE is not set
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||||
# CONFIG_FREEZER is not set
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||||
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||||
#
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||||
@ -294,7 +299,6 @@ CONFIG_NET=y
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||||
#
|
||||
# Networking options
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||||
#
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||||
# CONFIG_NET_NS is not set
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||||
CONFIG_COMPAT_NET_DEV_OPS=y
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||||
CONFIG_PACKET=y
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||||
CONFIG_PACKET_MMAP=y
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||||
@ -508,8 +512,8 @@ CONFIG_MTD_CONCAT=y
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||||
CONFIG_MTD_PARTITIONS=y
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||||
# CONFIG_MTD_TESTS is not set
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# CONFIG_MTD_REDBOOT_PARTS is not set
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# CONFIG_MTD_CMDLINE_PARTS is not set
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||||
# CONFIG_MTD_OF_PARTS is not set
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||||
CONFIG_MTD_CMDLINE_PARTS=y
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||||
CONFIG_MTD_OF_PARTS=y
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# CONFIG_MTD_AR7_PARTS is not set
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||||
#
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||||
@ -587,7 +591,6 @@ CONFIG_MTD_PHYSMAP=y
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||||
# LPDDR flash memory drivers
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||||
#
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||||
# CONFIG_MTD_LPDDR is not set
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||||
# CONFIG_MTD_QINFO_PROBE is not set
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||||
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||||
#
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||||
# UBI - Unsorted block images
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||||
@ -617,13 +620,19 @@ CONFIG_BLK_DEV_RAM_SIZE=8192
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||||
# CONFIG_BLK_DEV_HD is not set
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||||
CONFIG_MISC_DEVICES=y
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||||
# CONFIG_PHANTOM is not set
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||||
# CONFIG_EEPROM_93CX6 is not set
|
||||
# CONFIG_SGI_IOC4 is not set
|
||||
# CONFIG_TIFM_CORE is not set
|
||||
# CONFIG_ICS932S401 is not set
|
||||
# CONFIG_ENCLOSURE_SERVICES is not set
|
||||
# CONFIG_HP_ILO is not set
|
||||
# CONFIG_C2PORT is not set
|
||||
|
||||
#
|
||||
# EEPROM support
|
||||
#
|
||||
# CONFIG_EEPROM_AT24 is not set
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||||
CONFIG_EEPROM_LEGACY=m
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||||
# CONFIG_EEPROM_93CX6 is not set
|
||||
CONFIG_HAVE_IDE=y
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||||
# CONFIG_IDE is not set
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||||
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||||
@ -839,6 +848,7 @@ CONFIG_R8169=y
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||||
# CONFIG_QLA3XXX is not set
|
||||
# CONFIG_ATL1 is not set
|
||||
# CONFIG_ATL1E is not set
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||||
# CONFIG_ATL1C is not set
|
||||
# CONFIG_JME is not set
|
||||
CONFIG_NETDEV_10000=y
|
||||
# CONFIG_CHELSIO_T1 is not set
|
||||
@ -1037,8 +1047,6 @@ CONFIG_I2C_MPC=y
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||||
# Miscellaneous I2C Chip support
|
||||
#
|
||||
# CONFIG_DS1682 is not set
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||||
# CONFIG_EEPROM_AT24 is not set
|
||||
CONFIG_EEPROM_LEGACY=m
|
||||
# CONFIG_SENSORS_PCF8574 is not set
|
||||
# CONFIG_PCF8575 is not set
|
||||
# CONFIG_SENSORS_PCA9539 is not set
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
#
|
||||
# Automatically generated make config: don't edit
|
||||
# Linux kernel version: 2.6.29-rc2
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||||
# Mon Jan 26 15:35:46 2009
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# Linux kernel version: 2.6.29-rc6
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||||
# Fri Mar 6 00:09:08 2009
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#
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||||
# CONFIG_PPC64 is not set
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||||
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||||
@ -71,6 +71,15 @@ CONFIG_SYSVIPC_SYSCTL=y
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||||
# CONFIG_BSD_PROCESS_ACCT is not set
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||||
# CONFIG_TASKSTATS is not set
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||||
# CONFIG_AUDIT is not set
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||||
|
||||
#
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||||
# RCU Subsystem
|
||||
#
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||||
CONFIG_CLASSIC_RCU=y
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||||
# CONFIG_TREE_RCU is not set
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||||
# CONFIG_PREEMPT_RCU is not set
|
||||
# CONFIG_TREE_RCU_TRACE is not set
|
||||
# CONFIG_PREEMPT_RCU_TRACE is not set
|
||||
# CONFIG_IKCONFIG is not set
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||||
CONFIG_LOG_BUF_SHIFT=14
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||||
CONFIG_GROUP_SCHED=y
|
||||
@ -144,11 +153,6 @@ CONFIG_IOSCHED_CFQ=y
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||||
CONFIG_DEFAULT_CFQ=y
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||||
# CONFIG_DEFAULT_NOOP is not set
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||||
CONFIG_DEFAULT_IOSCHED="cfq"
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||||
CONFIG_CLASSIC_RCU=y
|
||||
# CONFIG_TREE_RCU is not set
|
||||
# CONFIG_PREEMPT_RCU is not set
|
||||
# CONFIG_TREE_RCU_TRACE is not set
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||||
# CONFIG_PREEMPT_RCU_TRACE is not set
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||||
# CONFIG_FREEZER is not set
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||||
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||||
#
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||||
@ -377,8 +381,8 @@ CONFIG_MTD=y
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||||
CONFIG_MTD_PARTITIONS=y
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||||
# CONFIG_MTD_TESTS is not set
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||||
# CONFIG_MTD_REDBOOT_PARTS is not set
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||||
# CONFIG_MTD_CMDLINE_PARTS is not set
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||||
# CONFIG_MTD_OF_PARTS is not set
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||||
CONFIG_MTD_CMDLINE_PARTS=y
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||||
CONFIG_MTD_OF_PARTS=y
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# CONFIG_MTD_AR7_PARTS is not set
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||||
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#
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@ -452,7 +456,6 @@ CONFIG_MTD_PHYSMAP=y
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||||
# LPDDR flash memory drivers
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||||
#
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||||
# CONFIG_MTD_LPDDR is not set
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||||
# CONFIG_MTD_QINFO_PROBE is not set
|
||||
|
||||
#
|
||||
# UBI - Unsorted block images
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||||
@ -478,13 +481,19 @@ CONFIG_BLK_DEV=y
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||||
# CONFIG_BLK_DEV_HD is not set
|
||||
CONFIG_MISC_DEVICES=y
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||||
# CONFIG_PHANTOM is not set
|
||||
# CONFIG_EEPROM_93CX6 is not set
|
||||
# CONFIG_SGI_IOC4 is not set
|
||||
# CONFIG_TIFM_CORE is not set
|
||||
# CONFIG_ICS932S401 is not set
|
||||
# CONFIG_ENCLOSURE_SERVICES is not set
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||||
# CONFIG_HP_ILO is not set
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||||
# CONFIG_C2PORT is not set
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||||
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||||
#
|
||||
# EEPROM support
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||||
#
|
||||
# CONFIG_EEPROM_AT24 is not set
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||||
# CONFIG_EEPROM_LEGACY is not set
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||||
# CONFIG_EEPROM_93CX6 is not set
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||||
CONFIG_HAVE_IDE=y
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||||
CONFIG_IDE=y
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||||
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||||
@ -677,6 +686,7 @@ CONFIG_R8169=y
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||||
# CONFIG_QLA3XXX is not set
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||||
# CONFIG_ATL1 is not set
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||||
# CONFIG_ATL1E is not set
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||||
# CONFIG_ATL1C is not set
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||||
# CONFIG_JME is not set
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||||
# CONFIG_NETDEV_10000 is not set
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||||
# CONFIG_TR is not set
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||||
@ -818,8 +828,6 @@ CONFIG_I2C_MPC=y
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||||
# Miscellaneous I2C Chip support
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||||
#
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||||
# CONFIG_DS1682 is not set
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||||
# CONFIG_EEPROM_AT24 is not set
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# CONFIG_EEPROM_LEGACY is not set
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||||
# CONFIG_SENSORS_PCF8574 is not set
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||||
# CONFIG_PCF8575 is not set
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# CONFIG_SENSORS_PCA9539 is not set
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@ -1159,6 +1167,7 @@ CONFIG_JFFS2_RTIME=y
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# CONFIG_SYSV_FS is not set
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# CONFIG_UFS_FS is not set
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# CONFIG_NETWORK_FILESYSTEMS is not set
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CONFIG_EXPORTFS=m
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||||
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#
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# Partition Types
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@ -12,7 +12,6 @@
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#include <linux/kernel.h>
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#include <linux/initrd.h>
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#include <linux/mtd/physmap.h>
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#include <linux/of_platform.h>
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#include <asm/time.h>
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@ -22,39 +21,6 @@
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#include "mpc10x.h"
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static struct mtd_partition linkstation_physmap_partitions[] = {
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{
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.name = "mtd_firmimg",
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.offset = 0x000000,
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.size = 0x300000,
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},
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{
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.name = "mtd_bootcode",
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.offset = 0x300000,
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.size = 0x070000,
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},
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{
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.name = "mtd_status",
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.offset = 0x370000,
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.size = 0x010000,
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},
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||||
{
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.name = "mtd_conf",
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.offset = 0x380000,
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.size = 0x080000,
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},
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||||
{
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.name = "mtd_allflash",
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.offset = 0x000000,
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.size = 0x400000,
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},
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{
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.name = "mtd_data",
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.offset = 0x310000,
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.size = 0x0f0000,
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},
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};
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||||
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static __initdata struct of_device_id of_bus_ids[] = {
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{ .type = "soc", },
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{ .compatible = "simple-bus", },
|
||||
@ -99,10 +65,6 @@ static int __init linkstation_add_bridge(struct device_node *dev)
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||||
static void __init linkstation_setup_arch(void)
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||||
{
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||||
struct device_node *np;
|
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#ifdef CONFIG_MTD_PHYSMAP
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||||
physmap_set_partitions(linkstation_physmap_partitions,
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ARRAY_SIZE(linkstation_physmap_partitions));
|
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#endif
|
||||
|
||||
/* Lookup PCI host bridges */
|
||||
for_each_compatible_node(np, "pci", "mpc10x-pci")
|
||||
|
||||
@ -14,7 +14,6 @@
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/initrd.h>
|
||||
#include <linux/mtd/physmap.h>
|
||||
#include <linux/of_platform.h>
|
||||
|
||||
#include <asm/system.h>
|
||||
@ -26,32 +25,6 @@
|
||||
#include "mpc10x.h"
|
||||
|
||||
|
||||
#ifdef CONFIG_MTD_PHYSMAP
|
||||
static struct mtd_partition storcenter_physmap_partitions[] = {
|
||||
{
|
||||
.name = "kernel",
|
||||
.offset = 0x000000,
|
||||
.size = 0x170000,
|
||||
},
|
||||
{
|
||||
.name = "rootfs",
|
||||
.offset = 0x170000,
|
||||
.size = 0x590000,
|
||||
},
|
||||
{
|
||||
.name = "uboot",
|
||||
.offset = 0x700000,
|
||||
.size = 0x040000,
|
||||
},
|
||||
{
|
||||
.name = "config",
|
||||
.offset = 0x740000,
|
||||
.size = 0x0c0000,
|
||||
},
|
||||
};
|
||||
#endif
|
||||
|
||||
|
||||
static __initdata struct of_device_id storcenter_of_bus[] = {
|
||||
{ .name = "soc", },
|
||||
{},
|
||||
@ -96,11 +69,6 @@ static void __init storcenter_setup_arch(void)
|
||||
{
|
||||
struct device_node *np;
|
||||
|
||||
#ifdef CONFIG_MTD_PHYSMAP
|
||||
physmap_set_partitions(storcenter_physmap_partitions,
|
||||
ARRAY_SIZE(storcenter_physmap_partitions));
|
||||
#endif
|
||||
|
||||
/* Lookup PCI host bridges */
|
||||
for_each_compatible_node(np, "pci", "mpc10x-pci")
|
||||
storcenter_add_bridge(np);
|
||||
|
||||
@ -931,6 +931,12 @@ config X86_CPUID
|
||||
with major 203 and minors 0 to 31 for /dev/cpu/0/cpuid to
|
||||
/dev/cpu/31/cpuid.
|
||||
|
||||
config X86_CPU_DEBUG
|
||||
tristate "/sys/kernel/debug/x86/cpu/* - CPU Debug support"
|
||||
---help---
|
||||
If you select this option, this will provide various x86 CPUs
|
||||
information through debugfs.
|
||||
|
||||
choice
|
||||
prompt "High Memory Support"
|
||||
default HIGHMEM4G if !X86_NUMAQ
|
||||
|
||||
@ -6,26 +6,23 @@
|
||||
# for more details.
|
||||
#
|
||||
# Copyright (C) 1994 by Linus Torvalds
|
||||
# Changed by many, many contributors over the years.
|
||||
#
|
||||
|
||||
# ROOT_DEV specifies the default root-device when making the image.
|
||||
# This can be either FLOPPY, CURRENT, /dev/xxxx or empty, in which case
|
||||
# the default of FLOPPY is used by 'build'.
|
||||
|
||||
ROOT_DEV := CURRENT
|
||||
ROOT_DEV := CURRENT
|
||||
|
||||
# If you want to preset the SVGA mode, uncomment the next line and
|
||||
# set SVGA_MODE to whatever number you want.
|
||||
# Set it to -DSVGA_MODE=NORMAL_VGA if you just want the EGA/VGA mode.
|
||||
# The number is the same as you would ordinarily press at bootup.
|
||||
|
||||
SVGA_MODE := -DSVGA_MODE=NORMAL_VGA
|
||||
SVGA_MODE := -DSVGA_MODE=NORMAL_VGA
|
||||
|
||||
# If you want the RAM disk device, define this to be the size in blocks.
|
||||
|
||||
#RAMDISK := -DRAMDISK=512
|
||||
|
||||
targets := vmlinux.bin setup.bin setup.elf zImage bzImage
|
||||
targets := vmlinux.bin setup.bin setup.elf bzImage
|
||||
subdir- := compressed
|
||||
|
||||
setup-y += a20.o cmdline.o copy.o cpu.o cpucheck.o edd.o
|
||||
@ -71,17 +68,13 @@ KBUILD_CFLAGS := $(LINUXINCLUDE) -g -Os -D_SETUP -D__KERNEL__ \
|
||||
KBUILD_CFLAGS += $(call cc-option,-m32)
|
||||
KBUILD_AFLAGS := $(KBUILD_CFLAGS) -D__ASSEMBLY__
|
||||
|
||||
$(obj)/zImage: asflags-y := $(SVGA_MODE) $(RAMDISK)
|
||||
$(obj)/bzImage: ccflags-y := -D__BIG_KERNEL__
|
||||
$(obj)/bzImage: asflags-y := $(SVGA_MODE) $(RAMDISK) -D__BIG_KERNEL__
|
||||
$(obj)/bzImage: BUILDFLAGS := -b
|
||||
$(obj)/bzImage: asflags-y := $(SVGA_MODE)
|
||||
|
||||
quiet_cmd_image = BUILD $@
|
||||
cmd_image = $(obj)/tools/build $(BUILDFLAGS) $(obj)/setup.bin \
|
||||
$(obj)/vmlinux.bin $(ROOT_DEV) > $@
|
||||
cmd_image = $(obj)/tools/build $(obj)/setup.bin $(obj)/vmlinux.bin \
|
||||
$(ROOT_DEV) > $@
|
||||
|
||||
$(obj)/zImage $(obj)/bzImage: $(obj)/setup.bin \
|
||||
$(obj)/vmlinux.bin $(obj)/tools/build FORCE
|
||||
$(obj)/bzImage: $(obj)/setup.bin $(obj)/vmlinux.bin $(obj)/tools/build FORCE
|
||||
$(call if_changed,image)
|
||||
@echo 'Kernel: $@ is ready' ' (#'`cat .version`')'
|
||||
|
||||
|
||||
@ -24,12 +24,8 @@
|
||||
#include "boot.h"
|
||||
#include "offsets.h"
|
||||
|
||||
SETUPSECTS = 4 /* default nr of setup-sectors */
|
||||
BOOTSEG = 0x07C0 /* original address of boot-sector */
|
||||
SYSSEG = DEF_SYSSEG /* system loaded at 0x10000 (65536) */
|
||||
SYSSIZE = DEF_SYSSIZE /* system size: # of 16-byte clicks */
|
||||
/* to be loaded */
|
||||
ROOT_DEV = 0 /* ROOT_DEV is now written by "build" */
|
||||
SYSSEG = 0x1000 /* historical load address >> 4 */
|
||||
|
||||
#ifndef SVGA_MODE
|
||||
#define SVGA_MODE ASK_VGA
|
||||
@ -97,12 +93,12 @@ bugger_off_msg:
|
||||
.section ".header", "a"
|
||||
.globl hdr
|
||||
hdr:
|
||||
setup_sects: .byte SETUPSECTS
|
||||
setup_sects: .byte 0 /* Filled in by build.c */
|
||||
root_flags: .word ROOT_RDONLY
|
||||
syssize: .long SYSSIZE
|
||||
ram_size: .word RAMDISK
|
||||
syssize: .long 0 /* Filled in by build.c */
|
||||
ram_size: .word 0 /* Obsolete */
|
||||
vid_mode: .word SVGA_MODE
|
||||
root_dev: .word ROOT_DEV
|
||||
root_dev: .word 0 /* Filled in by build.c */
|
||||
boot_flag: .word 0xAA55
|
||||
|
||||
# offset 512, entry point
|
||||
@ -123,14 +119,15 @@ _start:
|
||||
# or else old loadlin-1.5 will fail)
|
||||
.globl realmode_swtch
|
||||
realmode_swtch: .word 0, 0 # default_switch, SETUPSEG
|
||||
start_sys_seg: .word SYSSEG
|
||||
start_sys_seg: .word SYSSEG # obsolete and meaningless, but just
|
||||
# in case something decided to "use" it
|
||||
.word kernel_version-512 # pointing to kernel version string
|
||||
# above section of header is compatible
|
||||
# with loadlin-1.5 (header v1.5). Don't
|
||||
# change it.
|
||||
|
||||
type_of_loader: .byte 0 # = 0, old one (LILO, Loadlin,
|
||||
# Bootlin, SYSLX, bootsect...)
|
||||
type_of_loader: .byte 0 # 0 means ancient bootloader, newer
|
||||
# bootloaders know to change this.
|
||||
# See Documentation/i386/boot.txt for
|
||||
# assigned ids
|
||||
|
||||
@ -142,11 +139,7 @@ CAN_USE_HEAP = 0x80 # If set, the loader also has set
|
||||
# space behind setup.S can be used for
|
||||
# heap purposes.
|
||||
# Only the loader knows what is free
|
||||
#ifndef __BIG_KERNEL__
|
||||
.byte 0
|
||||
#else
|
||||
.byte LOADED_HIGH
|
||||
#endif
|
||||
|
||||
setup_move_size: .word 0x8000 # size to move, when setup is not
|
||||
# loaded at 0x90000. We will move setup
|
||||
@ -157,11 +150,7 @@ setup_move_size: .word 0x8000 # size to move, when setup is not
|
||||
|
||||
code32_start: # here loaders can put a different
|
||||
# start address for 32-bit code.
|
||||
#ifndef __BIG_KERNEL__
|
||||
.long 0x1000 # 0x1000 = default for zImage
|
||||
#else
|
||||
.long 0x100000 # 0x100000 = default for big kernel
|
||||
#endif
|
||||
|
||||
ramdisk_image: .long 0 # address of loaded ramdisk image
|
||||
# Here the loader puts the 32-bit
|
||||
|
||||
@ -32,47 +32,6 @@ static void realmode_switch_hook(void)
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* A zImage kernel is loaded at 0x10000 but wants to run at 0x1000.
|
||||
* A bzImage kernel is loaded and runs at 0x100000.
|
||||
*/
|
||||
static void move_kernel_around(void)
|
||||
{
|
||||
/* Note: rely on the compile-time option here rather than
|
||||
the LOADED_HIGH flag. The Qemu kernel loader unconditionally
|
||||
sets the loadflags to zero. */
|
||||
#ifndef __BIG_KERNEL__
|
||||
u16 dst_seg, src_seg;
|
||||
u32 syssize;
|
||||
|
||||
dst_seg = 0x1000 >> 4;
|
||||
src_seg = 0x10000 >> 4;
|
||||
syssize = boot_params.hdr.syssize; /* Size in 16-byte paragraphs */
|
||||
|
||||
while (syssize) {
|
||||
int paras = (syssize >= 0x1000) ? 0x1000 : syssize;
|
||||
int dwords = paras << 2;
|
||||
|
||||
asm volatile("pushw %%es ; "
|
||||
"pushw %%ds ; "
|
||||
"movw %1,%%es ; "
|
||||
"movw %2,%%ds ; "
|
||||
"xorw %%di,%%di ; "
|
||||
"xorw %%si,%%si ; "
|
||||
"rep;movsl ; "
|
||||
"popw %%ds ; "
|
||||
"popw %%es"
|
||||
: "+c" (dwords)
|
||||
: "r" (dst_seg), "r" (src_seg)
|
||||
: "esi", "edi");
|
||||
|
||||
syssize -= paras;
|
||||
dst_seg += paras;
|
||||
src_seg += paras;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
/*
|
||||
* Disable all interrupts at the legacy PIC.
|
||||
*/
|
||||
@ -147,9 +106,6 @@ void go_to_protected_mode(void)
|
||||
/* Hook before leaving real mode, also disables interrupts */
|
||||
realmode_switch_hook();
|
||||
|
||||
/* Move the kernel/setup to their final resting places */
|
||||
move_kernel_around();
|
||||
|
||||
/* Enable the A20 gate */
|
||||
if (enable_a20()) {
|
||||
puts("A20 gate not responding, unable to boot...\n");
|
||||
|
||||
@ -130,7 +130,7 @@ static void die(const char * str, ...)
|
||||
|
||||
static void usage(void)
|
||||
{
|
||||
die("Usage: build [-b] setup system [rootdev] [> image]");
|
||||
die("Usage: build setup system [rootdev] [> image]");
|
||||
}
|
||||
|
||||
int main(int argc, char ** argv)
|
||||
@ -145,11 +145,6 @@ int main(int argc, char ** argv)
|
||||
void *kernel;
|
||||
u32 crc = 0xffffffffUL;
|
||||
|
||||
if (argc > 2 && !strcmp(argv[1], "-b"))
|
||||
{
|
||||
is_big_kernel = 1;
|
||||
argc--, argv++;
|
||||
}
|
||||
if ((argc < 3) || (argc > 4))
|
||||
usage();
|
||||
if (argc > 3) {
|
||||
@ -216,8 +211,6 @@ int main(int argc, char ** argv)
|
||||
die("Unable to mmap '%s': %m", argv[2]);
|
||||
/* Number of 16-byte paragraphs, including space for a 4-byte CRC */
|
||||
sys_size = (sz + 15 + 4) / 16;
|
||||
if (!is_big_kernel && sys_size > DEF_SYSSIZE)
|
||||
die("System is too big. Try using bzImage or modules.");
|
||||
|
||||
/* Patch the setup code with the appropriate size parameters */
|
||||
buf[0x1f1] = setup_sectors-1;
|
||||
|
||||
@ -1,10 +1,6 @@
|
||||
#ifndef _ASM_X86_BOOT_H
|
||||
#define _ASM_X86_BOOT_H
|
||||
|
||||
/* Don't touch these, unless you really know what you're doing. */
|
||||
#define DEF_SYSSEG 0x1000
|
||||
#define DEF_SYSSIZE 0x7F00
|
||||
|
||||
/* Internal svga startup constants */
|
||||
#define NORMAL_VGA 0xffff /* 80x25 mode */
|
||||
#define EXTENDED_VGA 0xfffe /* 80x50 mode */
|
||||
|
||||
193
arch/x86/include/asm/cpu_debug.h
Executable file
193
arch/x86/include/asm/cpu_debug.h
Executable file
@ -0,0 +1,193 @@
|
||||
#ifndef _ASM_X86_CPU_DEBUG_H
|
||||
#define _ASM_X86_CPU_DEBUG_H
|
||||
|
||||
/*
|
||||
* CPU x86 architecture debug
|
||||
*
|
||||
* Copyright(C) 2009 Jaswinder Singh Rajput
|
||||
*/
|
||||
|
||||
/* Register flags */
|
||||
enum cpu_debug_bit {
|
||||
/* Model Specific Registers (MSRs) */
|
||||
CPU_MC_BIT, /* Machine Check */
|
||||
CPU_MONITOR_BIT, /* Monitor */
|
||||
CPU_TIME_BIT, /* Time */
|
||||
CPU_PMC_BIT, /* Performance Monitor */
|
||||
CPU_PLATFORM_BIT, /* Platform */
|
||||
CPU_APIC_BIT, /* APIC */
|
||||
CPU_POWERON_BIT, /* Power-on */
|
||||
CPU_CONTROL_BIT, /* Control */
|
||||
CPU_FEATURES_BIT, /* Features control */
|
||||
CPU_LBRANCH_BIT, /* Last Branch */
|
||||
CPU_BIOS_BIT, /* BIOS */
|
||||
CPU_FREQ_BIT, /* Frequency */
|
||||
CPU_MTTR_BIT, /* MTRR */
|
||||
CPU_PERF_BIT, /* Performance */
|
||||
CPU_CACHE_BIT, /* Cache */
|
||||
CPU_SYSENTER_BIT, /* Sysenter */
|
||||
CPU_THERM_BIT, /* Thermal */
|
||||
CPU_MISC_BIT, /* Miscellaneous */
|
||||
CPU_DEBUG_BIT, /* Debug */
|
||||
CPU_PAT_BIT, /* PAT */
|
||||
CPU_VMX_BIT, /* VMX */
|
||||
CPU_CALL_BIT, /* System Call */
|
||||
CPU_BASE_BIT, /* BASE Address */
|
||||
CPU_SMM_BIT, /* System mgmt mode */
|
||||
CPU_SVM_BIT, /*Secure Virtual Machine*/
|
||||
CPU_OSVM_BIT, /* OS-Visible Workaround*/
|
||||
/* Standard Registers */
|
||||
CPU_TSS_BIT, /* Task Stack Segment */
|
||||
CPU_CR_BIT, /* Control Registers */
|
||||
CPU_DT_BIT, /* Descriptor Table */
|
||||
/* End of Registers flags */
|
||||
CPU_REG_ALL_BIT, /* Select all Registers */
|
||||
};
|
||||
|
||||
#define CPU_REG_ALL (~0) /* Select all Registers */
|
||||
|
||||
#define CPU_MC (1 << CPU_MC_BIT)
|
||||
#define CPU_MONITOR (1 << CPU_MONITOR_BIT)
|
||||
#define CPU_TIME (1 << CPU_TIME_BIT)
|
||||
#define CPU_PMC (1 << CPU_PMC_BIT)
|
||||
#define CPU_PLATFORM (1 << CPU_PLATFORM_BIT)
|
||||
#define CPU_APIC (1 << CPU_APIC_BIT)
|
||||
#define CPU_POWERON (1 << CPU_POWERON_BIT)
|
||||
#define CPU_CONTROL (1 << CPU_CONTROL_BIT)
|
||||
#define CPU_FEATURES (1 << CPU_FEATURES_BIT)
|
||||
#define CPU_LBRANCH (1 << CPU_LBRANCH_BIT)
|
||||
#define CPU_BIOS (1 << CPU_BIOS_BIT)
|
||||
#define CPU_FREQ (1 << CPU_FREQ_BIT)
|
||||
#define CPU_MTRR (1 << CPU_MTTR_BIT)
|
||||
#define CPU_PERF (1 << CPU_PERF_BIT)
|
||||
#define CPU_CACHE (1 << CPU_CACHE_BIT)
|
||||
#define CPU_SYSENTER (1 << CPU_SYSENTER_BIT)
|
||||
#define CPU_THERM (1 << CPU_THERM_BIT)
|
||||
#define CPU_MISC (1 << CPU_MISC_BIT)
|
||||
#define CPU_DEBUG (1 << CPU_DEBUG_BIT)
|
||||
#define CPU_PAT (1 << CPU_PAT_BIT)
|
||||
#define CPU_VMX (1 << CPU_VMX_BIT)
|
||||
#define CPU_CALL (1 << CPU_CALL_BIT)
|
||||
#define CPU_BASE (1 << CPU_BASE_BIT)
|
||||
#define CPU_SMM (1 << CPU_SMM_BIT)
|
||||
#define CPU_SVM (1 << CPU_SVM_BIT)
|
||||
#define CPU_OSVM (1 << CPU_OSVM_BIT)
|
||||
#define CPU_TSS (1 << CPU_TSS_BIT)
|
||||
#define CPU_CR (1 << CPU_CR_BIT)
|
||||
#define CPU_DT (1 << CPU_DT_BIT)
|
||||
|
||||
/* Register file flags */
|
||||
enum cpu_file_bit {
|
||||
CPU_INDEX_BIT, /* index */
|
||||
CPU_VALUE_BIT, /* value */
|
||||
};
|
||||
|
||||
#define CPU_FILE_VALUE (1 << CPU_VALUE_BIT)
|
||||
|
||||
/*
|
||||
* DisplayFamily_DisplayModel Processor Families/Processor Number Series
|
||||
* -------------------------- ------------------------------------------
|
||||
* 05_01, 05_02, 05_04 Pentium, Pentium with MMX
|
||||
*
|
||||
* 06_01 Pentium Pro
|
||||
* 06_03, 06_05 Pentium II Xeon, Pentium II
|
||||
* 06_07, 06_08, 06_0A, 06_0B Pentium III Xeon, Pentum III
|
||||
*
|
||||
* 06_09, 060D Pentium M
|
||||
*
|
||||
* 06_0E Core Duo, Core Solo
|
||||
*
|
||||
* 06_0F Xeon 3000, 3200, 5100, 5300, 7300 series,
|
||||
* Core 2 Quad, Core 2 Extreme, Core 2 Duo,
|
||||
* Pentium dual-core
|
||||
* 06_17 Xeon 5200, 5400 series, Core 2 Quad Q9650
|
||||
*
|
||||
* 06_1C Atom
|
||||
*
|
||||
* 0F_00, 0F_01, 0F_02 Xeon, Xeon MP, Pentium 4
|
||||
* 0F_03, 0F_04 Xeon, Xeon MP, Pentium 4, Pentium D
|
||||
*
|
||||
* 0F_06 Xeon 7100, 5000 Series, Xeon MP,
|
||||
* Pentium 4, Pentium D
|
||||
*/
|
||||
|
||||
/* Register processors bits */
|
||||
enum cpu_processor_bit {
|
||||
CPU_NONE,
|
||||
/* Intel */
|
||||
CPU_INTEL_PENTIUM_BIT,
|
||||
CPU_INTEL_P6_BIT,
|
||||
CPU_INTEL_PENTIUM_M_BIT,
|
||||
CPU_INTEL_CORE_BIT,
|
||||
CPU_INTEL_CORE2_BIT,
|
||||
CPU_INTEL_ATOM_BIT,
|
||||
CPU_INTEL_XEON_P4_BIT,
|
||||
CPU_INTEL_XEON_MP_BIT,
|
||||
};
|
||||
|
||||
#define CPU_ALL (~0) /* Select all CPUs */
|
||||
|
||||
#define CPU_INTEL_PENTIUM (1 << CPU_INTEL_PENTIUM_BIT)
|
||||
#define CPU_INTEL_P6 (1 << CPU_INTEL_P6_BIT)
|
||||
#define CPU_INTEL_PENTIUM_M (1 << CPU_INTEL_PENTIUM_M_BIT)
|
||||
#define CPU_INTEL_CORE (1 << CPU_INTEL_CORE_BIT)
|
||||
#define CPU_INTEL_CORE2 (1 << CPU_INTEL_CORE2_BIT)
|
||||
#define CPU_INTEL_ATOM (1 << CPU_INTEL_ATOM_BIT)
|
||||
#define CPU_INTEL_XEON_P4 (1 << CPU_INTEL_XEON_P4_BIT)
|
||||
#define CPU_INTEL_XEON_MP (1 << CPU_INTEL_XEON_MP_BIT)
|
||||
|
||||
#define CPU_INTEL_PX (CPU_INTEL_P6 | CPU_INTEL_PENTIUM_M)
|
||||
#define CPU_INTEL_COREX (CPU_INTEL_CORE | CPU_INTEL_CORE2)
|
||||
#define CPU_INTEL_XEON (CPU_INTEL_XEON_P4 | CPU_INTEL_XEON_MP)
|
||||
#define CPU_CO_AT (CPU_INTEL_CORE | CPU_INTEL_ATOM)
|
||||
#define CPU_C2_AT (CPU_INTEL_CORE2 | CPU_INTEL_ATOM)
|
||||
#define CPU_CX_AT (CPU_INTEL_COREX | CPU_INTEL_ATOM)
|
||||
#define CPU_CX_XE (CPU_INTEL_COREX | CPU_INTEL_XEON)
|
||||
#define CPU_P6_XE (CPU_INTEL_P6 | CPU_INTEL_XEON)
|
||||
#define CPU_PM_CO_AT (CPU_INTEL_PENTIUM_M | CPU_CO_AT)
|
||||
#define CPU_C2_AT_XE (CPU_C2_AT | CPU_INTEL_XEON)
|
||||
#define CPU_CX_AT_XE (CPU_CX_AT | CPU_INTEL_XEON)
|
||||
#define CPU_P6_CX_AT (CPU_INTEL_P6 | CPU_CX_AT)
|
||||
#define CPU_P6_CX_XE (CPU_P6_XE | CPU_INTEL_COREX)
|
||||
#define CPU_P6_CX_AT_XE (CPU_INTEL_P6 | CPU_CX_AT_XE)
|
||||
#define CPU_PM_CX_AT_XE (CPU_INTEL_PENTIUM_M | CPU_CX_AT_XE)
|
||||
#define CPU_PM_CX_AT (CPU_INTEL_PENTIUM_M | CPU_CX_AT)
|
||||
#define CPU_PM_CX_XE (CPU_INTEL_PENTIUM_M | CPU_CX_XE)
|
||||
#define CPU_PX_CX_AT (CPU_INTEL_PX | CPU_CX_AT)
|
||||
#define CPU_PX_CX_AT_XE (CPU_INTEL_PX | CPU_CX_AT_XE)
|
||||
|
||||
/* Select all Intel CPUs*/
|
||||
#define CPU_INTEL_ALL (CPU_INTEL_PENTIUM | CPU_PX_CX_AT_XE)
|
||||
|
||||
#define MAX_CPU_FILES 512
|
||||
|
||||
struct cpu_private {
|
||||
unsigned cpu;
|
||||
unsigned type;
|
||||
unsigned reg;
|
||||
unsigned file;
|
||||
};
|
||||
|
||||
struct cpu_debug_base {
|
||||
char *name; /* Register name */
|
||||
unsigned flag; /* Register flag */
|
||||
};
|
||||
|
||||
struct cpu_cpuX_base {
|
||||
struct dentry *dentry; /* Register dentry */
|
||||
int init; /* Register index file */
|
||||
};
|
||||
|
||||
struct cpu_file_base {
|
||||
char *name; /* Register file name */
|
||||
unsigned flag; /* Register file flag */
|
||||
};
|
||||
|
||||
struct cpu_debug_range {
|
||||
unsigned min; /* Register range min */
|
||||
unsigned max; /* Register range max */
|
||||
unsigned flag; /* Supported flags */
|
||||
unsigned model; /* Supported models */
|
||||
};
|
||||
|
||||
#endif /* _ASM_X86_CPU_DEBUG_H */
|
||||
@ -91,7 +91,6 @@ static inline int desc_empty(const void *ptr)
|
||||
#define store_gdt(dtr) native_store_gdt(dtr)
|
||||
#define store_idt(dtr) native_store_idt(dtr)
|
||||
#define store_tr(tr) (tr = native_store_tr())
|
||||
#define store_ldt(ldt) asm("sldt %0":"=m" (ldt))
|
||||
|
||||
#define load_TLS(t, cpu) native_load_tls(t, cpu)
|
||||
#define set_ldt native_set_ldt
|
||||
@ -112,6 +111,8 @@ static inline void paravirt_free_ldt(struct desc_struct *ldt, unsigned entries)
|
||||
}
|
||||
#endif /* CONFIG_PARAVIRT */
|
||||
|
||||
#define store_ldt(ldt) asm("sldt %0" : "=m"(ldt))
|
||||
|
||||
static inline void native_write_idt_entry(gate_desc *idt, int entry,
|
||||
const gate_desc *gate)
|
||||
{
|
||||
|
||||
@ -63,6 +63,7 @@ void *kmap_atomic_prot(struct page *page, enum km_type type, pgprot_t prot);
|
||||
void *kmap_atomic(struct page *page, enum km_type type);
|
||||
void kunmap_atomic(void *kvaddr, enum km_type type);
|
||||
void *kmap_atomic_pfn(unsigned long pfn, enum km_type type);
|
||||
void *kmap_atomic_prot_pfn(unsigned long pfn, enum km_type type, pgprot_t prot);
|
||||
struct page *kmap_atomic_to_page(void *ptr);
|
||||
|
||||
#ifndef CONFIG_PARAVIRT
|
||||
|
||||
@ -14,6 +14,8 @@ obj-y += vmware.o hypervisor.o
|
||||
obj-$(CONFIG_X86_32) += bugs.o cmpxchg.o
|
||||
obj-$(CONFIG_X86_64) += bugs_64.o
|
||||
|
||||
obj-$(CONFIG_X86_CPU_DEBUG) += cpu_debug.o
|
||||
|
||||
obj-$(CONFIG_CPU_SUP_INTEL) += intel.o
|
||||
obj-$(CONFIG_CPU_SUP_AMD) += amd.o
|
||||
obj-$(CONFIG_CPU_SUP_CYRIX_32) += cyrix.o
|
||||
|
||||
@ -1078,8 +1078,7 @@ void __cpuinit cpu_init(void)
|
||||
|
||||
atomic_inc(&init_mm.mm_count);
|
||||
me->active_mm = &init_mm;
|
||||
if (me->mm)
|
||||
BUG();
|
||||
BUG_ON(me->mm);
|
||||
enter_lazy_tlb(&init_mm, me);
|
||||
|
||||
load_sp0(t, ¤t->thread);
|
||||
@ -1145,8 +1144,7 @@ void __cpuinit cpu_init(void)
|
||||
*/
|
||||
atomic_inc(&init_mm.mm_count);
|
||||
curr->active_mm = &init_mm;
|
||||
if (curr->mm)
|
||||
BUG();
|
||||
BUG_ON(curr->mm);
|
||||
enter_lazy_tlb(&init_mm, curr);
|
||||
|
||||
load_sp0(t, thread);
|
||||
|
||||
785
arch/x86/kernel/cpu/cpu_debug.c
Executable file
785
arch/x86/kernel/cpu/cpu_debug.c
Executable file
@ -0,0 +1,785 @@
|
||||
/*
|
||||
* CPU x86 architecture debug code
|
||||
*
|
||||
* Copyright(C) 2009 Jaswinder Singh Rajput
|
||||
*
|
||||
* For licencing details see kernel-base/COPYING
|
||||
*/
|
||||
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/compiler.h>
|
||||
#include <linux/seq_file.h>
|
||||
#include <linux/debugfs.h>
|
||||
#include <linux/kprobes.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/percpu.h>
|
||||
#include <linux/signal.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/smp.h>
|
||||
|
||||
#include <asm/cpu_debug.h>
|
||||
#include <asm/paravirt.h>
|
||||
#include <asm/system.h>
|
||||
#include <asm/traps.h>
|
||||
#include <asm/apic.h>
|
||||
#include <asm/desc.h>
|
||||
|
||||
static DEFINE_PER_CPU(struct cpu_cpuX_base, cpu_arr[CPU_REG_ALL_BIT]);
|
||||
static DEFINE_PER_CPU(struct cpu_private *, priv_arr[MAX_CPU_FILES]);
|
||||
static DEFINE_PER_CPU(unsigned, cpu_modelflag);
|
||||
static DEFINE_PER_CPU(int, cpu_priv_count);
|
||||
static DEFINE_PER_CPU(unsigned, cpu_model);
|
||||
|
||||
static DEFINE_MUTEX(cpu_debug_lock);
|
||||
|
||||
static struct dentry *cpu_debugfs_dir;
|
||||
|
||||
static struct cpu_debug_base cpu_base[] = {
|
||||
{ "mc", CPU_MC }, /* Machine Check */
|
||||
{ "monitor", CPU_MONITOR }, /* Monitor */
|
||||
{ "time", CPU_TIME }, /* Time */
|
||||
{ "pmc", CPU_PMC }, /* Performance Monitor */
|
||||
{ "platform", CPU_PLATFORM }, /* Platform */
|
||||
{ "apic", CPU_APIC }, /* APIC */
|
||||
{ "poweron", CPU_POWERON }, /* Power-on */
|
||||
{ "control", CPU_CONTROL }, /* Control */
|
||||
{ "features", CPU_FEATURES }, /* Features control */
|
||||
{ "lastbranch", CPU_LBRANCH }, /* Last Branch */
|
||||
{ "bios", CPU_BIOS }, /* BIOS */
|
||||
{ "freq", CPU_FREQ }, /* Frequency */
|
||||
{ "mtrr", CPU_MTRR }, /* MTRR */
|
||||
{ "perf", CPU_PERF }, /* Performance */
|
||||
{ "cache", CPU_CACHE }, /* Cache */
|
||||
{ "sysenter", CPU_SYSENTER }, /* Sysenter */
|
||||
{ "therm", CPU_THERM }, /* Thermal */
|
||||
{ "misc", CPU_MISC }, /* Miscellaneous */
|
||||
{ "debug", CPU_DEBUG }, /* Debug */
|
||||
{ "pat", CPU_PAT }, /* PAT */
|
||||
{ "vmx", CPU_VMX }, /* VMX */
|
||||
{ "call", CPU_CALL }, /* System Call */
|
||||
{ "base", CPU_BASE }, /* BASE Address */
|
||||
{ "smm", CPU_SMM }, /* System mgmt mode */
|
||||
{ "svm", CPU_SVM }, /*Secure Virtial Machine*/
|
||||
{ "osvm", CPU_OSVM }, /* OS-Visible Workaround*/
|
||||
{ "tss", CPU_TSS }, /* Task Stack Segment */
|
||||
{ "cr", CPU_CR }, /* Control Registers */
|
||||
{ "dt", CPU_DT }, /* Descriptor Table */
|
||||
{ "registers", CPU_REG_ALL }, /* Select all Registers */
|
||||
};
|
||||
|
||||
static struct cpu_file_base cpu_file[] = {
|
||||
{ "index", CPU_REG_ALL }, /* index */
|
||||
{ "value", CPU_REG_ALL }, /* value */
|
||||
};
|
||||
|
||||
/* Intel Registers Range */
|
||||
static struct cpu_debug_range cpu_intel_range[] = {
|
||||
{ 0x00000000, 0x00000001, CPU_MC, CPU_INTEL_ALL },
|
||||
{ 0x00000006, 0x00000007, CPU_MONITOR, CPU_CX_AT_XE },
|
||||
{ 0x00000010, 0x00000010, CPU_TIME, CPU_INTEL_ALL },
|
||||
{ 0x00000011, 0x00000013, CPU_PMC, CPU_INTEL_PENTIUM },
|
||||
{ 0x00000017, 0x00000017, CPU_PLATFORM, CPU_PX_CX_AT_XE },
|
||||
{ 0x0000001B, 0x0000001B, CPU_APIC, CPU_P6_CX_AT_XE },
|
||||
|
||||
{ 0x0000002A, 0x0000002A, CPU_POWERON, CPU_PX_CX_AT_XE },
|
||||
{ 0x0000002B, 0x0000002B, CPU_POWERON, CPU_INTEL_XEON },
|
||||
{ 0x0000002C, 0x0000002C, CPU_FREQ, CPU_INTEL_XEON },
|
||||
{ 0x0000003A, 0x0000003A, CPU_CONTROL, CPU_CX_AT_XE },
|
||||
|
||||
{ 0x00000040, 0x00000043, CPU_LBRANCH, CPU_PM_CX_AT_XE },
|
||||
{ 0x00000044, 0x00000047, CPU_LBRANCH, CPU_PM_CO_AT },
|
||||
{ 0x00000060, 0x00000063, CPU_LBRANCH, CPU_C2_AT },
|
||||
{ 0x00000064, 0x00000067, CPU_LBRANCH, CPU_INTEL_ATOM },
|
||||
|
||||
{ 0x00000079, 0x00000079, CPU_BIOS, CPU_P6_CX_AT_XE },
|
||||
{ 0x00000088, 0x0000008A, CPU_CACHE, CPU_INTEL_P6 },
|
||||
{ 0x0000008B, 0x0000008B, CPU_BIOS, CPU_P6_CX_AT_XE },
|
||||
{ 0x0000009B, 0x0000009B, CPU_MONITOR, CPU_INTEL_XEON },
|
||||
|
||||
{ 0x000000C1, 0x000000C2, CPU_PMC, CPU_P6_CX_AT },
|
||||
{ 0x000000CD, 0x000000CD, CPU_FREQ, CPU_CX_AT },
|
||||
{ 0x000000E7, 0x000000E8, CPU_PERF, CPU_CX_AT },
|
||||
{ 0x000000FE, 0x000000FE, CPU_MTRR, CPU_P6_CX_XE },
|
||||
|
||||
{ 0x00000116, 0x00000116, CPU_CACHE, CPU_INTEL_P6 },
|
||||
{ 0x00000118, 0x00000118, CPU_CACHE, CPU_INTEL_P6 },
|
||||
{ 0x00000119, 0x00000119, CPU_CACHE, CPU_INTEL_PX },
|
||||
{ 0x0000011A, 0x0000011B, CPU_CACHE, CPU_INTEL_P6 },
|
||||
{ 0x0000011E, 0x0000011E, CPU_CACHE, CPU_PX_CX_AT },
|
||||
|
||||
{ 0x00000174, 0x00000176, CPU_SYSENTER, CPU_P6_CX_AT_XE },
|
||||
{ 0x00000179, 0x0000017A, CPU_MC, CPU_PX_CX_AT_XE },
|
||||
{ 0x0000017B, 0x0000017B, CPU_MC, CPU_P6_XE },
|
||||
{ 0x00000186, 0x00000187, CPU_PMC, CPU_P6_CX_AT },
|
||||
{ 0x00000198, 0x00000199, CPU_PERF, CPU_PM_CX_AT_XE },
|
||||
{ 0x0000019A, 0x0000019A, CPU_TIME, CPU_PM_CX_AT_XE },
|
||||
{ 0x0000019B, 0x0000019D, CPU_THERM, CPU_PM_CX_AT_XE },
|
||||
{ 0x000001A0, 0x000001A0, CPU_MISC, CPU_PM_CX_AT_XE },
|
||||
|
||||
{ 0x000001C9, 0x000001C9, CPU_LBRANCH, CPU_PM_CX_AT },
|
||||
{ 0x000001D7, 0x000001D8, CPU_LBRANCH, CPU_INTEL_XEON },
|
||||
{ 0x000001D9, 0x000001D9, CPU_DEBUG, CPU_CX_AT_XE },
|
||||
{ 0x000001DA, 0x000001DA, CPU_LBRANCH, CPU_INTEL_XEON },
|
||||
{ 0x000001DB, 0x000001DB, CPU_LBRANCH, CPU_P6_XE },
|
||||
{ 0x000001DC, 0x000001DC, CPU_LBRANCH, CPU_INTEL_P6 },
|
||||
{ 0x000001DD, 0x000001DE, CPU_LBRANCH, CPU_PX_CX_AT_XE },
|
||||
{ 0x000001E0, 0x000001E0, CPU_LBRANCH, CPU_INTEL_P6 },
|
||||
|
||||
{ 0x00000200, 0x0000020F, CPU_MTRR, CPU_P6_CX_XE },
|
||||
{ 0x00000250, 0x00000250, CPU_MTRR, CPU_P6_CX_XE },
|
||||
{ 0x00000258, 0x00000259, CPU_MTRR, CPU_P6_CX_XE },
|
||||
{ 0x00000268, 0x0000026F, CPU_MTRR, CPU_P6_CX_XE },
|
||||
{ 0x00000277, 0x00000277, CPU_PAT, CPU_C2_AT_XE },
|
||||
{ 0x000002FF, 0x000002FF, CPU_MTRR, CPU_P6_CX_XE },
|
||||
|
||||
{ 0x00000300, 0x00000308, CPU_PMC, CPU_INTEL_XEON },
|
||||
{ 0x00000309, 0x0000030B, CPU_PMC, CPU_C2_AT_XE },
|
||||
{ 0x0000030C, 0x00000311, CPU_PMC, CPU_INTEL_XEON },
|
||||
{ 0x00000345, 0x00000345, CPU_PMC, CPU_C2_AT },
|
||||
{ 0x00000360, 0x00000371, CPU_PMC, CPU_INTEL_XEON },
|
||||
{ 0x0000038D, 0x00000390, CPU_PMC, CPU_C2_AT },
|
||||
{ 0x000003A0, 0x000003BE, CPU_PMC, CPU_INTEL_XEON },
|
||||
{ 0x000003C0, 0x000003CD, CPU_PMC, CPU_INTEL_XEON },
|
||||
{ 0x000003E0, 0x000003E1, CPU_PMC, CPU_INTEL_XEON },
|
||||
{ 0x000003F0, 0x000003F0, CPU_PMC, CPU_INTEL_XEON },
|
||||
{ 0x000003F1, 0x000003F1, CPU_PMC, CPU_C2_AT_XE },
|
||||
{ 0x000003F2, 0x000003F2, CPU_PMC, CPU_INTEL_XEON },
|
||||
|
||||
{ 0x00000400, 0x00000402, CPU_MC, CPU_PM_CX_AT_XE },
|
||||
{ 0x00000403, 0x00000403, CPU_MC, CPU_INTEL_XEON },
|
||||
{ 0x00000404, 0x00000406, CPU_MC, CPU_PM_CX_AT_XE },
|
||||
{ 0x00000407, 0x00000407, CPU_MC, CPU_INTEL_XEON },
|
||||
{ 0x00000408, 0x0000040A, CPU_MC, CPU_PM_CX_AT_XE },
|
||||
{ 0x0000040B, 0x0000040B, CPU_MC, CPU_INTEL_XEON },
|
||||
{ 0x0000040C, 0x0000040E, CPU_MC, CPU_PM_CX_XE },
|
||||
{ 0x0000040F, 0x0000040F, CPU_MC, CPU_INTEL_XEON },
|
||||
{ 0x00000410, 0x00000412, CPU_MC, CPU_PM_CX_AT_XE },
|
||||
{ 0x00000413, 0x00000417, CPU_MC, CPU_CX_AT_XE },
|
||||
{ 0x00000480, 0x0000048B, CPU_VMX, CPU_CX_AT_XE },
|
||||
|
||||
{ 0x00000600, 0x00000600, CPU_DEBUG, CPU_PM_CX_AT_XE },
|
||||
{ 0x00000680, 0x0000068F, CPU_LBRANCH, CPU_INTEL_XEON },
|
||||
{ 0x000006C0, 0x000006CF, CPU_LBRANCH, CPU_INTEL_XEON },
|
||||
|
||||
{ 0x000107CC, 0x000107D3, CPU_PMC, CPU_INTEL_XEON_MP },
|
||||
|
||||
{ 0xC0000080, 0xC0000080, CPU_FEATURES, CPU_INTEL_XEON },
|
||||
{ 0xC0000081, 0xC0000082, CPU_CALL, CPU_INTEL_XEON },
|
||||
{ 0xC0000084, 0xC0000084, CPU_CALL, CPU_INTEL_XEON },
|
||||
{ 0xC0000100, 0xC0000102, CPU_BASE, CPU_INTEL_XEON },
|
||||
};
|
||||
|
||||
/* AMD Registers Range */
|
||||
static struct cpu_debug_range cpu_amd_range[] = {
|
||||
{ 0x00000010, 0x00000010, CPU_TIME, CPU_ALL, },
|
||||
{ 0x0000001B, 0x0000001B, CPU_APIC, CPU_ALL, },
|
||||
{ 0x000000FE, 0x000000FE, CPU_MTRR, CPU_ALL, },
|
||||
|
||||
{ 0x00000174, 0x00000176, CPU_SYSENTER, CPU_ALL, },
|
||||
{ 0x00000179, 0x0000017A, CPU_MC, CPU_ALL, },
|
||||
{ 0x0000017B, 0x0000017B, CPU_MC, CPU_ALL, },
|
||||
{ 0x000001D9, 0x000001D9, CPU_DEBUG, CPU_ALL, },
|
||||
{ 0x000001DB, 0x000001DE, CPU_LBRANCH, CPU_ALL, },
|
||||
|
||||
{ 0x00000200, 0x0000020F, CPU_MTRR, CPU_ALL, },
|
||||
{ 0x00000250, 0x00000250, CPU_MTRR, CPU_ALL, },
|
||||
{ 0x00000258, 0x00000259, CPU_MTRR, CPU_ALL, },
|
||||
{ 0x00000268, 0x0000026F, CPU_MTRR, CPU_ALL, },
|
||||
{ 0x00000277, 0x00000277, CPU_PAT, CPU_ALL, },
|
||||
{ 0x000002FF, 0x000002FF, CPU_MTRR, CPU_ALL, },
|
||||
|
||||
{ 0x00000400, 0x00000417, CPU_MC, CPU_ALL, },
|
||||
|
||||
{ 0xC0000080, 0xC0000080, CPU_FEATURES, CPU_ALL, },
|
||||
{ 0xC0000081, 0xC0000084, CPU_CALL, CPU_ALL, },
|
||||
{ 0xC0000100, 0xC0000102, CPU_BASE, CPU_ALL, },
|
||||
{ 0xC0000103, 0xC0000103, CPU_TIME, CPU_ALL, },
|
||||
|
||||
{ 0xC0000408, 0xC000040A, CPU_MC, CPU_ALL, },
|
||||
|
||||
{ 0xc0010000, 0xc0010007, CPU_PMC, CPU_ALL, },
|
||||
{ 0xc0010010, 0xc0010010, CPU_MTRR, CPU_ALL, },
|
||||
{ 0xc0010016, 0xc001001A, CPU_MTRR, CPU_ALL, },
|
||||
{ 0xc001001D, 0xc001001D, CPU_MTRR, CPU_ALL, },
|
||||
{ 0xc0010030, 0xc0010035, CPU_BIOS, CPU_ALL, },
|
||||
{ 0xc0010056, 0xc0010056, CPU_SMM, CPU_ALL, },
|
||||
{ 0xc0010061, 0xc0010063, CPU_SMM, CPU_ALL, },
|
||||
{ 0xc0010074, 0xc0010074, CPU_MC, CPU_ALL, },
|
||||
{ 0xc0010111, 0xc0010113, CPU_SMM, CPU_ALL, },
|
||||
{ 0xc0010114, 0xc0010118, CPU_SVM, CPU_ALL, },
|
||||
{ 0xc0010119, 0xc001011A, CPU_SMM, CPU_ALL, },
|
||||
{ 0xc0010140, 0xc0010141, CPU_OSVM, CPU_ALL, },
|
||||
{ 0xc0010156, 0xc0010156, CPU_SMM, CPU_ALL, },
|
||||
};
|
||||
|
||||
|
||||
static int get_cpu_modelflag(unsigned cpu)
|
||||
{
|
||||
int flag;
|
||||
|
||||
switch (per_cpu(cpu_model, cpu)) {
|
||||
/* Intel */
|
||||
case 0x0501:
|
||||
case 0x0502:
|
||||
case 0x0504:
|
||||
flag = CPU_INTEL_PENTIUM;
|
||||
break;
|
||||
case 0x0601:
|
||||
case 0x0603:
|
||||
case 0x0605:
|
||||
case 0x0607:
|
||||
case 0x0608:
|
||||
case 0x060A:
|
||||
case 0x060B:
|
||||
flag = CPU_INTEL_P6;
|
||||
break;
|
||||
case 0x0609:
|
||||
case 0x060D:
|
||||
flag = CPU_INTEL_PENTIUM_M;
|
||||
break;
|
||||
case 0x060E:
|
||||
flag = CPU_INTEL_CORE;
|
||||
break;
|
||||
case 0x060F:
|
||||
case 0x0617:
|
||||
flag = CPU_INTEL_CORE2;
|
||||
break;
|
||||
case 0x061C:
|
||||
flag = CPU_INTEL_ATOM;
|
||||
break;
|
||||
case 0x0F00:
|
||||
case 0x0F01:
|
||||
case 0x0F02:
|
||||
case 0x0F03:
|
||||
case 0x0F04:
|
||||
flag = CPU_INTEL_XEON_P4;
|
||||
break;
|
||||
case 0x0F06:
|
||||
flag = CPU_INTEL_XEON_MP;
|
||||
break;
|
||||
default:
|
||||
flag = CPU_NONE;
|
||||
break;
|
||||
}
|
||||
|
||||
return flag;
|
||||
}
|
||||
|
||||
static int get_cpu_range_count(unsigned cpu)
|
||||
{
|
||||
int index;
|
||||
|
||||
switch (per_cpu(cpu_model, cpu) >> 16) {
|
||||
case X86_VENDOR_INTEL:
|
||||
index = ARRAY_SIZE(cpu_intel_range);
|
||||
break;
|
||||
case X86_VENDOR_AMD:
|
||||
index = ARRAY_SIZE(cpu_amd_range);
|
||||
break;
|
||||
default:
|
||||
index = 0;
|
||||
break;
|
||||
}
|
||||
|
||||
return index;
|
||||
}
|
||||
|
||||
static int is_typeflag_valid(unsigned cpu, unsigned flag)
|
||||
{
|
||||
unsigned vendor, modelflag;
|
||||
int i, index;
|
||||
|
||||
/* Standard Registers should be always valid */
|
||||
if (flag >= CPU_TSS)
|
||||
return 1;
|
||||
|
||||
modelflag = per_cpu(cpu_modelflag, cpu);
|
||||
vendor = per_cpu(cpu_model, cpu) >> 16;
|
||||
index = get_cpu_range_count(cpu);
|
||||
|
||||
for (i = 0; i < index; i++) {
|
||||
switch (vendor) {
|
||||
case X86_VENDOR_INTEL:
|
||||
if ((cpu_intel_range[i].model & modelflag) &&
|
||||
(cpu_intel_range[i].flag & flag))
|
||||
return 1;
|
||||
break;
|
||||
case X86_VENDOR_AMD:
|
||||
if (cpu_amd_range[i].flag & flag)
|
||||
return 1;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* Invalid */
|
||||
return 0;
|
||||
}
|
||||
|
||||
static unsigned get_cpu_range(unsigned cpu, unsigned *min, unsigned *max,
|
||||
int index, unsigned flag)
|
||||
{
|
||||
unsigned modelflag;
|
||||
|
||||
modelflag = per_cpu(cpu_modelflag, cpu);
|
||||
*max = 0;
|
||||
switch (per_cpu(cpu_model, cpu) >> 16) {
|
||||
case X86_VENDOR_INTEL:
|
||||
if ((cpu_intel_range[index].model & modelflag) &&
|
||||
(cpu_intel_range[index].flag & flag)) {
|
||||
*min = cpu_intel_range[index].min;
|
||||
*max = cpu_intel_range[index].max;
|
||||
}
|
||||
break;
|
||||
case X86_VENDOR_AMD:
|
||||
if (cpu_amd_range[index].flag & flag) {
|
||||
*min = cpu_amd_range[index].min;
|
||||
*max = cpu_amd_range[index].max;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
return *max;
|
||||
}
|
||||
|
||||
/* This function can also be called with seq = NULL for printk */
|
||||
static void print_cpu_data(struct seq_file *seq, unsigned type,
|
||||
u32 low, u32 high)
|
||||
{
|
||||
struct cpu_private *priv;
|
||||
u64 val = high;
|
||||
|
||||
if (seq) {
|
||||
priv = seq->private;
|
||||
if (priv->file) {
|
||||
val = (val << 32) | low;
|
||||
seq_printf(seq, "0x%llx\n", val);
|
||||
} else
|
||||
seq_printf(seq, " %08x: %08x_%08x\n",
|
||||
type, high, low);
|
||||
} else
|
||||
printk(KERN_INFO " %08x: %08x_%08x\n", type, high, low);
|
||||
}
|
||||
|
||||
/* This function can also be called with seq = NULL for printk */
|
||||
static void print_msr(struct seq_file *seq, unsigned cpu, unsigned flag)
|
||||
{
|
||||
unsigned msr, msr_min, msr_max;
|
||||
struct cpu_private *priv;
|
||||
u32 low, high;
|
||||
int i, range;
|
||||
|
||||
if (seq) {
|
||||
priv = seq->private;
|
||||
if (priv->file) {
|
||||
if (!rdmsr_safe_on_cpu(priv->cpu, priv->reg,
|
||||
&low, &high))
|
||||
print_cpu_data(seq, priv->reg, low, high);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
range = get_cpu_range_count(cpu);
|
||||
|
||||
for (i = 0; i < range; i++) {
|
||||
if (!get_cpu_range(cpu, &msr_min, &msr_max, i, flag))
|
||||
continue;
|
||||
|
||||
for (msr = msr_min; msr <= msr_max; msr++) {
|
||||
if (rdmsr_safe_on_cpu(cpu, msr, &low, &high))
|
||||
continue;
|
||||
print_cpu_data(seq, msr, low, high);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void print_tss(void *arg)
|
||||
{
|
||||
struct pt_regs *regs = task_pt_regs(current);
|
||||
struct seq_file *seq = arg;
|
||||
unsigned int seg;
|
||||
|
||||
seq_printf(seq, " RAX\t: %016lx\n", regs->ax);
|
||||
seq_printf(seq, " RBX\t: %016lx\n", regs->bx);
|
||||
seq_printf(seq, " RCX\t: %016lx\n", regs->cx);
|
||||
seq_printf(seq, " RDX\t: %016lx\n", regs->dx);
|
||||
|
||||
seq_printf(seq, " RSI\t: %016lx\n", regs->si);
|
||||
seq_printf(seq, " RDI\t: %016lx\n", regs->di);
|
||||
seq_printf(seq, " RBP\t: %016lx\n", regs->bp);
|
||||
seq_printf(seq, " ESP\t: %016lx\n", regs->sp);
|
||||
|
||||
#ifdef CONFIG_X86_64
|
||||
seq_printf(seq, " R08\t: %016lx\n", regs->r8);
|
||||
seq_printf(seq, " R09\t: %016lx\n", regs->r9);
|
||||
seq_printf(seq, " R10\t: %016lx\n", regs->r10);
|
||||
seq_printf(seq, " R11\t: %016lx\n", regs->r11);
|
||||
seq_printf(seq, " R12\t: %016lx\n", regs->r12);
|
||||
seq_printf(seq, " R13\t: %016lx\n", regs->r13);
|
||||
seq_printf(seq, " R14\t: %016lx\n", regs->r14);
|
||||
seq_printf(seq, " R15\t: %016lx\n", regs->r15);
|
||||
#endif
|
||||
|
||||
asm("movl %%cs,%0" : "=r" (seg));
|
||||
seq_printf(seq, " CS\t: %04x\n", seg);
|
||||
asm("movl %%ds,%0" : "=r" (seg));
|
||||
seq_printf(seq, " DS\t: %04x\n", seg);
|
||||
seq_printf(seq, " SS\t: %04lx\n", regs->ss & 0xffff);
|
||||
asm("movl %%es,%0" : "=r" (seg));
|
||||
seq_printf(seq, " ES\t: %04x\n", seg);
|
||||
asm("movl %%fs,%0" : "=r" (seg));
|
||||
seq_printf(seq, " FS\t: %04x\n", seg);
|
||||
asm("movl %%gs,%0" : "=r" (seg));
|
||||
seq_printf(seq, " GS\t: %04x\n", seg);
|
||||
|
||||
seq_printf(seq, " EFLAGS\t: %016lx\n", regs->flags);
|
||||
|
||||
seq_printf(seq, " EIP\t: %016lx\n", regs->ip);
|
||||
}
|
||||
|
||||
static void print_cr(void *arg)
|
||||
{
|
||||
struct seq_file *seq = arg;
|
||||
|
||||
seq_printf(seq, " cr0\t: %016lx\n", read_cr0());
|
||||
seq_printf(seq, " cr2\t: %016lx\n", read_cr2());
|
||||
seq_printf(seq, " cr3\t: %016lx\n", read_cr3());
|
||||
seq_printf(seq, " cr4\t: %016lx\n", read_cr4_safe());
|
||||
#ifdef CONFIG_X86_64
|
||||
seq_printf(seq, " cr8\t: %016lx\n", read_cr8());
|
||||
#endif
|
||||
}
|
||||
|
||||
static void print_desc_ptr(char *str, struct seq_file *seq, struct desc_ptr dt)
|
||||
{
|
||||
seq_printf(seq, " %s\t: %016llx\n", str, (u64)(dt.address | dt.size));
|
||||
}
|
||||
|
||||
static void print_dt(void *seq)
|
||||
{
|
||||
struct desc_ptr dt;
|
||||
unsigned long ldt;
|
||||
|
||||
/* IDT */
|
||||
store_idt((struct desc_ptr *)&dt);
|
||||
print_desc_ptr("IDT", seq, dt);
|
||||
|
||||
/* GDT */
|
||||
store_gdt((struct desc_ptr *)&dt);
|
||||
print_desc_ptr("GDT", seq, dt);
|
||||
|
||||
/* LDT */
|
||||
store_ldt(ldt);
|
||||
seq_printf(seq, " LDT\t: %016lx\n", ldt);
|
||||
|
||||
/* TR */
|
||||
store_tr(ldt);
|
||||
seq_printf(seq, " TR\t: %016lx\n", ldt);
|
||||
}
|
||||
|
||||
static void print_dr(void *arg)
|
||||
{
|
||||
struct seq_file *seq = arg;
|
||||
unsigned long dr;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < 8; i++) {
|
||||
/* Ignore db4, db5 */
|
||||
if ((i == 4) || (i == 5))
|
||||
continue;
|
||||
get_debugreg(dr, i);
|
||||
seq_printf(seq, " dr%d\t: %016lx\n", i, dr);
|
||||
}
|
||||
|
||||
seq_printf(seq, "\n MSR\t:\n");
|
||||
}
|
||||
|
||||
static void print_apic(void *arg)
|
||||
{
|
||||
struct seq_file *seq = arg;
|
||||
|
||||
#ifdef CONFIG_X86_LOCAL_APIC
|
||||
seq_printf(seq, " LAPIC\t:\n");
|
||||
seq_printf(seq, " ID\t\t: %08x\n", apic_read(APIC_ID) >> 24);
|
||||
seq_printf(seq, " LVR\t\t: %08x\n", apic_read(APIC_LVR));
|
||||
seq_printf(seq, " TASKPRI\t: %08x\n", apic_read(APIC_TASKPRI));
|
||||
seq_printf(seq, " ARBPRI\t\t: %08x\n", apic_read(APIC_ARBPRI));
|
||||
seq_printf(seq, " PROCPRI\t: %08x\n", apic_read(APIC_PROCPRI));
|
||||
seq_printf(seq, " LDR\t\t: %08x\n", apic_read(APIC_LDR));
|
||||
seq_printf(seq, " DFR\t\t: %08x\n", apic_read(APIC_DFR));
|
||||
seq_printf(seq, " SPIV\t\t: %08x\n", apic_read(APIC_SPIV));
|
||||
seq_printf(seq, " ISR\t\t: %08x\n", apic_read(APIC_ISR));
|
||||
seq_printf(seq, " ESR\t\t: %08x\n", apic_read(APIC_ESR));
|
||||
seq_printf(seq, " ICR\t\t: %08x\n", apic_read(APIC_ICR));
|
||||
seq_printf(seq, " ICR2\t\t: %08x\n", apic_read(APIC_ICR2));
|
||||
seq_printf(seq, " LVTT\t\t: %08x\n", apic_read(APIC_LVTT));
|
||||
seq_printf(seq, " LVTTHMR\t: %08x\n", apic_read(APIC_LVTTHMR));
|
||||
seq_printf(seq, " LVTPC\t\t: %08x\n", apic_read(APIC_LVTPC));
|
||||
seq_printf(seq, " LVT0\t\t: %08x\n", apic_read(APIC_LVT0));
|
||||
seq_printf(seq, " LVT1\t\t: %08x\n", apic_read(APIC_LVT1));
|
||||
seq_printf(seq, " LVTERR\t\t: %08x\n", apic_read(APIC_LVTERR));
|
||||
seq_printf(seq, " TMICT\t\t: %08x\n", apic_read(APIC_TMICT));
|
||||
seq_printf(seq, " TMCCT\t\t: %08x\n", apic_read(APIC_TMCCT));
|
||||
seq_printf(seq, " TDCR\t\t: %08x\n", apic_read(APIC_TDCR));
|
||||
#endif /* CONFIG_X86_LOCAL_APIC */
|
||||
|
||||
seq_printf(seq, "\n MSR\t:\n");
|
||||
}
|
||||
|
||||
static int cpu_seq_show(struct seq_file *seq, void *v)
|
||||
{
|
||||
struct cpu_private *priv = seq->private;
|
||||
|
||||
if (priv == NULL)
|
||||
return -EINVAL;
|
||||
|
||||
switch (cpu_base[priv->type].flag) {
|
||||
case CPU_TSS:
|
||||
smp_call_function_single(priv->cpu, print_tss, seq, 1);
|
||||
break;
|
||||
case CPU_CR:
|
||||
smp_call_function_single(priv->cpu, print_cr, seq, 1);
|
||||
break;
|
||||
case CPU_DT:
|
||||
smp_call_function_single(priv->cpu, print_dt, seq, 1);
|
||||
break;
|
||||
case CPU_DEBUG:
|
||||
if (priv->file == CPU_INDEX_BIT)
|
||||
smp_call_function_single(priv->cpu, print_dr, seq, 1);
|
||||
print_msr(seq, priv->cpu, cpu_base[priv->type].flag);
|
||||
break;
|
||||
case CPU_APIC:
|
||||
if (priv->file == CPU_INDEX_BIT)
|
||||
smp_call_function_single(priv->cpu, print_apic, seq, 1);
|
||||
print_msr(seq, priv->cpu, cpu_base[priv->type].flag);
|
||||
break;
|
||||
|
||||
default:
|
||||
print_msr(seq, priv->cpu, cpu_base[priv->type].flag);
|
||||
break;
|
||||
}
|
||||
seq_printf(seq, "\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void *cpu_seq_start(struct seq_file *seq, loff_t *pos)
|
||||
{
|
||||
if (*pos == 0) /* One time is enough ;-) */
|
||||
return seq;
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static void *cpu_seq_next(struct seq_file *seq, void *v, loff_t *pos)
|
||||
{
|
||||
(*pos)++;
|
||||
|
||||
return cpu_seq_start(seq, pos);
|
||||
}
|
||||
|
||||
static void cpu_seq_stop(struct seq_file *seq, void *v)
|
||||
{
|
||||
}
|
||||
|
||||
static const struct seq_operations cpu_seq_ops = {
|
||||
.start = cpu_seq_start,
|
||||
.next = cpu_seq_next,
|
||||
.stop = cpu_seq_stop,
|
||||
.show = cpu_seq_show,
|
||||
};
|
||||
|
||||
static int cpu_seq_open(struct inode *inode, struct file *file)
|
||||
{
|
||||
struct cpu_private *priv = inode->i_private;
|
||||
struct seq_file *seq;
|
||||
int err;
|
||||
|
||||
err = seq_open(file, &cpu_seq_ops);
|
||||
if (!err) {
|
||||
seq = file->private_data;
|
||||
seq->private = priv;
|
||||
}
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static const struct file_operations cpu_fops = {
|
||||
.open = cpu_seq_open,
|
||||
.read = seq_read,
|
||||
.llseek = seq_lseek,
|
||||
.release = seq_release,
|
||||
};
|
||||
|
||||
static int cpu_create_file(unsigned cpu, unsigned type, unsigned reg,
|
||||
unsigned file, struct dentry *dentry)
|
||||
{
|
||||
struct cpu_private *priv = NULL;
|
||||
|
||||
/* Already intialized */
|
||||
if (file == CPU_INDEX_BIT)
|
||||
if (per_cpu(cpu_arr[type].init, cpu))
|
||||
return 0;
|
||||
|
||||
priv = kzalloc(sizeof(*priv), GFP_KERNEL);
|
||||
if (priv == NULL)
|
||||
return -ENOMEM;
|
||||
|
||||
priv->cpu = cpu;
|
||||
priv->type = type;
|
||||
priv->reg = reg;
|
||||
priv->file = file;
|
||||
mutex_lock(&cpu_debug_lock);
|
||||
per_cpu(priv_arr[type], cpu) = priv;
|
||||
per_cpu(cpu_priv_count, cpu)++;
|
||||
mutex_unlock(&cpu_debug_lock);
|
||||
|
||||
if (file)
|
||||
debugfs_create_file(cpu_file[file].name, S_IRUGO,
|
||||
dentry, (void *)priv, &cpu_fops);
|
||||
else {
|
||||
debugfs_create_file(cpu_base[type].name, S_IRUGO,
|
||||
per_cpu(cpu_arr[type].dentry, cpu),
|
||||
(void *)priv, &cpu_fops);
|
||||
mutex_lock(&cpu_debug_lock);
|
||||
per_cpu(cpu_arr[type].init, cpu) = 1;
|
||||
mutex_unlock(&cpu_debug_lock);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int cpu_init_regfiles(unsigned cpu, unsigned int type, unsigned reg,
|
||||
struct dentry *dentry)
|
||||
{
|
||||
unsigned file;
|
||||
int err = 0;
|
||||
|
||||
for (file = 0; file < ARRAY_SIZE(cpu_file); file++) {
|
||||
err = cpu_create_file(cpu, type, reg, file, dentry);
|
||||
if (err)
|
||||
return err;
|
||||
}
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static int cpu_init_msr(unsigned cpu, unsigned type, struct dentry *dentry)
|
||||
{
|
||||
struct dentry *cpu_dentry = NULL;
|
||||
unsigned reg, reg_min, reg_max;
|
||||
int i, range, err = 0;
|
||||
char reg_dir[12];
|
||||
u32 low, high;
|
||||
|
||||
range = get_cpu_range_count(cpu);
|
||||
|
||||
for (i = 0; i < range; i++) {
|
||||
if (!get_cpu_range(cpu, ®_min, ®_max, i,
|
||||
cpu_base[type].flag))
|
||||
continue;
|
||||
|
||||
for (reg = reg_min; reg <= reg_max; reg++) {
|
||||
if (rdmsr_safe_on_cpu(cpu, reg, &low, &high))
|
||||
continue;
|
||||
|
||||
sprintf(reg_dir, "0x%x", reg);
|
||||
cpu_dentry = debugfs_create_dir(reg_dir, dentry);
|
||||
err = cpu_init_regfiles(cpu, type, reg, cpu_dentry);
|
||||
if (err)
|
||||
return err;
|
||||
}
|
||||
}
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static int cpu_init_allreg(unsigned cpu, struct dentry *dentry)
|
||||
{
|
||||
struct dentry *cpu_dentry = NULL;
|
||||
unsigned type;
|
||||
int err = 0;
|
||||
|
||||
for (type = 0; type < ARRAY_SIZE(cpu_base) - 1; type++) {
|
||||
if (!is_typeflag_valid(cpu, cpu_base[type].flag))
|
||||
continue;
|
||||
cpu_dentry = debugfs_create_dir(cpu_base[type].name, dentry);
|
||||
per_cpu(cpu_arr[type].dentry, cpu) = cpu_dentry;
|
||||
|
||||
if (type < CPU_TSS_BIT)
|
||||
err = cpu_init_msr(cpu, type, cpu_dentry);
|
||||
else
|
||||
err = cpu_create_file(cpu, type, 0, CPU_INDEX_BIT,
|
||||
cpu_dentry);
|
||||
if (err)
|
||||
return err;
|
||||
}
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static int cpu_init_cpu(void)
|
||||
{
|
||||
struct dentry *cpu_dentry = NULL;
|
||||
struct cpuinfo_x86 *cpui;
|
||||
char cpu_dir[12];
|
||||
unsigned cpu;
|
||||
int err = 0;
|
||||
|
||||
for (cpu = 0; cpu < nr_cpu_ids; cpu++) {
|
||||
cpui = &cpu_data(cpu);
|
||||
if (!cpu_has(cpui, X86_FEATURE_MSR))
|
||||
continue;
|
||||
per_cpu(cpu_model, cpu) = ((cpui->x86_vendor << 16) |
|
||||
(cpui->x86 << 8) |
|
||||
(cpui->x86_model));
|
||||
per_cpu(cpu_modelflag, cpu) = get_cpu_modelflag(cpu);
|
||||
|
||||
sprintf(cpu_dir, "cpu%d", cpu);
|
||||
cpu_dentry = debugfs_create_dir(cpu_dir, cpu_debugfs_dir);
|
||||
err = cpu_init_allreg(cpu, cpu_dentry);
|
||||
|
||||
pr_info("cpu%d(%d) debug files %d\n",
|
||||
cpu, nr_cpu_ids, per_cpu(cpu_priv_count, cpu));
|
||||
if (per_cpu(cpu_priv_count, cpu) > MAX_CPU_FILES) {
|
||||
pr_err("Register files count %d exceeds limit %d\n",
|
||||
per_cpu(cpu_priv_count, cpu), MAX_CPU_FILES);
|
||||
per_cpu(cpu_priv_count, cpu) = MAX_CPU_FILES;
|
||||
err = -ENFILE;
|
||||
}
|
||||
if (err)
|
||||
return err;
|
||||
}
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static int __init cpu_debug_init(void)
|
||||
{
|
||||
cpu_debugfs_dir = debugfs_create_dir("cpu", arch_debugfs_dir);
|
||||
|
||||
return cpu_init_cpu();
|
||||
}
|
||||
|
||||
static void __exit cpu_debug_exit(void)
|
||||
{
|
||||
int i, cpu;
|
||||
|
||||
if (cpu_debugfs_dir)
|
||||
debugfs_remove_recursive(cpu_debugfs_dir);
|
||||
|
||||
for (cpu = 0; cpu < nr_cpu_ids; cpu++)
|
||||
for (i = 0; i < per_cpu(cpu_priv_count, cpu); i++)
|
||||
kfree(per_cpu(priv_arr[i], cpu));
|
||||
}
|
||||
|
||||
module_init(cpu_debug_init);
|
||||
module_exit(cpu_debug_exit);
|
||||
|
||||
MODULE_AUTHOR("Jaswinder Singh Rajput");
|
||||
MODULE_DESCRIPTION("CPU Debug module");
|
||||
MODULE_LICENSE("GPL");
|
||||
@ -74,8 +74,7 @@ static void ich_force_hpet_resume(void)
|
||||
if (!force_hpet_address)
|
||||
return;
|
||||
|
||||
if (rcba_base == NULL)
|
||||
BUG();
|
||||
BUG_ON(rcba_base == NULL);
|
||||
|
||||
/* read the Function Disable register, dword mode only */
|
||||
val = readl(rcba_base + 0x3404);
|
||||
|
||||
@ -121,23 +121,30 @@ void kunmap_atomic(void *kvaddr, enum km_type type)
|
||||
pagefault_enable();
|
||||
}
|
||||
|
||||
/* This is the same as kmap_atomic() but can map memory that doesn't
|
||||
* have a struct page associated with it.
|
||||
*/
|
||||
void *kmap_atomic_pfn(unsigned long pfn, enum km_type type)
|
||||
void *kmap_atomic_prot_pfn(unsigned long pfn, enum km_type type, pgprot_t prot)
|
||||
{
|
||||
enum fixed_addresses idx;
|
||||
unsigned long vaddr;
|
||||
|
||||
pagefault_disable();
|
||||
|
||||
idx = type + KM_TYPE_NR*smp_processor_id();
|
||||
debug_kmap_atomic_prot(type);
|
||||
|
||||
idx = type + KM_TYPE_NR * smp_processor_id();
|
||||
vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx);
|
||||
set_pte(kmap_pte-idx, pfn_pte(pfn, kmap_prot));
|
||||
set_pte(kmap_pte - idx, pfn_pte(pfn, prot));
|
||||
arch_flush_lazy_mmu_mode();
|
||||
|
||||
return (void*) vaddr;
|
||||
}
|
||||
|
||||
/* This is the same as kmap_atomic() but can map memory that doesn't
|
||||
* have a struct page associated with it.
|
||||
*/
|
||||
void *kmap_atomic_pfn(unsigned long pfn, enum km_type type)
|
||||
{
|
||||
return kmap_atomic_prot_pfn(pfn, type, kmap_prot);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(kmap_atomic_pfn); /* temporarily in use by i915 GEM until vmap */
|
||||
|
||||
struct page *kmap_atomic_to_page(void *ptr)
|
||||
|
||||
@ -18,6 +18,7 @@
|
||||
|
||||
#include <asm/iomap.h>
|
||||
#include <asm/pat.h>
|
||||
#include <asm/highmem.h>
|
||||
#include <linux/module.h>
|
||||
|
||||
int is_io_mapping_possible(resource_size_t base, unsigned long size)
|
||||
@ -36,11 +37,6 @@ EXPORT_SYMBOL_GPL(is_io_mapping_possible);
|
||||
void *
|
||||
iomap_atomic_prot_pfn(unsigned long pfn, enum km_type type, pgprot_t prot)
|
||||
{
|
||||
enum fixed_addresses idx;
|
||||
unsigned long vaddr;
|
||||
|
||||
pagefault_disable();
|
||||
|
||||
/*
|
||||
* For non-PAT systems, promote PAGE_KERNEL_WC to PAGE_KERNEL_UC_MINUS.
|
||||
* PAGE_KERNEL_WC maps to PWT, which translates to uncached if the
|
||||
@ -50,12 +46,7 @@ iomap_atomic_prot_pfn(unsigned long pfn, enum km_type type, pgprot_t prot)
|
||||
if (!pat_enabled && pgprot_val(prot) == pgprot_val(PAGE_KERNEL_WC))
|
||||
prot = PAGE_KERNEL_UC_MINUS;
|
||||
|
||||
idx = type + KM_TYPE_NR*smp_processor_id();
|
||||
vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx);
|
||||
set_pte(kmap_pte-idx, pfn_pte(pfn, prot));
|
||||
arch_flush_lazy_mmu_mode();
|
||||
|
||||
return (void*) vaddr;
|
||||
return kmap_atomic_prot_pfn(pfn, type, prot);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(iomap_atomic_prot_pfn);
|
||||
|
||||
|
||||
@ -310,7 +310,7 @@ static int post_kmmio_handler(unsigned long condition, struct pt_regs *regs)
|
||||
struct kmmio_context *ctx = &get_cpu_var(kmmio_ctx);
|
||||
|
||||
if (!ctx->active) {
|
||||
pr_warning("kmmio: spurious debug trap on CPU %d.\n",
|
||||
pr_debug("kmmio: spurious debug trap on CPU %d.\n",
|
||||
smp_processor_id());
|
||||
goto out;
|
||||
}
|
||||
|
||||
@ -522,6 +522,17 @@ static int split_large_page(pte_t *kpte, unsigned long address)
|
||||
* primary protection behavior:
|
||||
*/
|
||||
__set_pmd_pte(kpte, address, mk_pte(base, __pgprot(_KERNPG_TABLE)));
|
||||
|
||||
/*
|
||||
* Intel Atom errata AAH41 workaround.
|
||||
*
|
||||
* The real fix should be in hw or in a microcode update, but
|
||||
* we also probabilistically try to reduce the window of having
|
||||
* a large TLB mixed with 4K TLBs while instruction fetches are
|
||||
* going on.
|
||||
*/
|
||||
__flush_tlb_all();
|
||||
|
||||
base = NULL;
|
||||
|
||||
out_unlock:
|
||||
|
||||
@ -1139,15 +1139,6 @@ static int hvcs_open(struct tty_struct *tty, struct file *filp)
|
||||
hvcsd->tty = tty;
|
||||
tty->driver_data = hvcsd;
|
||||
|
||||
/*
|
||||
* Set this driver to low latency so that we actually have a chance at
|
||||
* catching a throttled TTY after we flip_buffer_push. Otherwise the
|
||||
* flush_to_async may not execute until after the kernel_thread has
|
||||
* yielded and resumed the next flip_buffer_push resulting in data
|
||||
* loss.
|
||||
*/
|
||||
tty->low_latency = 1;
|
||||
|
||||
memset(&hvcsd->buffer[0], 0x00, HVCS_BUFF_LEN);
|
||||
|
||||
/*
|
||||
|
||||
@ -810,7 +810,6 @@ static int hvsi_open(struct tty_struct *tty, struct file *filp)
|
||||
hp = &hvsi_ports[line];
|
||||
|
||||
tty->driver_data = hp;
|
||||
tty->low_latency = 1; /* avoid throttle/tty_flip_buffer_push race */
|
||||
|
||||
mb();
|
||||
if (hp->state == HVSI_FSP_DIED)
|
||||
|
||||
@ -1105,7 +1105,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
|
||||
1024 * 1024,
|
||||
MTRR_TYPE_WRCOMB, 1);
|
||||
if (dev_priv->mm.gtt_mtrr < 0) {
|
||||
DRM_INFO("MTRR allocation failed\n. Graphics "
|
||||
DRM_INFO("MTRR allocation failed. Graphics "
|
||||
"performance may suffer.\n");
|
||||
}
|
||||
|
||||
|
||||
@ -279,7 +279,6 @@ typedef struct drm_i915_private {
|
||||
u8 saveAR_INDEX;
|
||||
u8 saveAR[21];
|
||||
u8 saveDACMASK;
|
||||
u8 saveDACDATA[256*3]; /* 256 3-byte colors */
|
||||
u8 saveCR[37];
|
||||
|
||||
struct {
|
||||
@ -457,6 +456,12 @@ struct drm_i915_gem_object {
|
||||
|
||||
/** for phy allocated objects */
|
||||
struct drm_i915_gem_phys_object *phys_obj;
|
||||
|
||||
/**
|
||||
* Used for checking the object doesn't appear more than once
|
||||
* in an execbuffer object list.
|
||||
*/
|
||||
int in_execbuffer;
|
||||
};
|
||||
|
||||
/**
|
||||
|
||||
@ -1476,7 +1476,7 @@ static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
|
||||
struct drm_i915_gem_object *obj_priv = obj->driver_private;
|
||||
int regnum = obj_priv->fence_reg;
|
||||
int tile_width;
|
||||
uint32_t val;
|
||||
uint32_t fence_reg, val;
|
||||
uint32_t pitch_val;
|
||||
|
||||
if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
|
||||
@ -1503,7 +1503,11 @@ static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
|
||||
val |= pitch_val << I830_FENCE_PITCH_SHIFT;
|
||||
val |= I830_FENCE_REG_VALID;
|
||||
|
||||
I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
|
||||
if (regnum < 8)
|
||||
fence_reg = FENCE_REG_830_0 + (regnum * 4);
|
||||
else
|
||||
fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4);
|
||||
I915_WRITE(fence_reg, val);
|
||||
}
|
||||
|
||||
static void i830_write_fence_reg(struct drm_i915_fence_reg *reg)
|
||||
@ -1557,7 +1561,8 @@ i915_gem_object_get_fence_reg(struct drm_gem_object *obj, bool write)
|
||||
struct drm_i915_private *dev_priv = dev->dev_private;
|
||||
struct drm_i915_gem_object *obj_priv = obj->driver_private;
|
||||
struct drm_i915_fence_reg *reg = NULL;
|
||||
int i, ret;
|
||||
struct drm_i915_gem_object *old_obj_priv = NULL;
|
||||
int i, ret, avail;
|
||||
|
||||
switch (obj_priv->tiling_mode) {
|
||||
case I915_TILING_NONE:
|
||||
@ -1580,25 +1585,46 @@ i915_gem_object_get_fence_reg(struct drm_gem_object *obj, bool write)
|
||||
}
|
||||
|
||||
/* First try to find a free reg */
|
||||
try_again:
|
||||
avail = 0;
|
||||
for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
|
||||
reg = &dev_priv->fence_regs[i];
|
||||
if (!reg->obj)
|
||||
break;
|
||||
|
||||
old_obj_priv = reg->obj->driver_private;
|
||||
if (!old_obj_priv->pin_count)
|
||||
avail++;
|
||||
}
|
||||
|
||||
/* None available, try to steal one or wait for a user to finish */
|
||||
if (i == dev_priv->num_fence_regs) {
|
||||
struct drm_i915_gem_object *old_obj_priv = NULL;
|
||||
uint32_t seqno = dev_priv->mm.next_gem_seqno;
|
||||
loff_t offset;
|
||||
|
||||
try_again:
|
||||
/* Could try to use LRU here instead... */
|
||||
if (avail == 0)
|
||||
return -ENOMEM;
|
||||
|
||||
for (i = dev_priv->fence_reg_start;
|
||||
i < dev_priv->num_fence_regs; i++) {
|
||||
uint32_t this_seqno;
|
||||
|
||||
reg = &dev_priv->fence_regs[i];
|
||||
old_obj_priv = reg->obj->driver_private;
|
||||
if (!old_obj_priv->pin_count)
|
||||
|
||||
if (old_obj_priv->pin_count)
|
||||
continue;
|
||||
|
||||
/* i915 uses fences for GPU access to tiled buffers */
|
||||
if (IS_I965G(dev) || !old_obj_priv->active)
|
||||
break;
|
||||
|
||||
/* find the seqno of the first available fence */
|
||||
this_seqno = old_obj_priv->last_rendering_seqno;
|
||||
if (this_seqno != 0 &&
|
||||
reg->obj->write_domain == 0 &&
|
||||
i915_seqno_passed(seqno, this_seqno))
|
||||
seqno = this_seqno;
|
||||
}
|
||||
|
||||
/*
|
||||
@ -1606,15 +1632,25 @@ try_again:
|
||||
* objects to finish before trying again.
|
||||
*/
|
||||
if (i == dev_priv->num_fence_regs) {
|
||||
ret = i915_gem_object_set_to_gtt_domain(reg->obj, 0);
|
||||
if (ret) {
|
||||
WARN(ret != -ERESTARTSYS,
|
||||
"switch to GTT domain failed: %d\n", ret);
|
||||
return ret;
|
||||
if (seqno == dev_priv->mm.next_gem_seqno) {
|
||||
i915_gem_flush(dev,
|
||||
I915_GEM_GPU_DOMAINS,
|
||||
I915_GEM_GPU_DOMAINS);
|
||||
seqno = i915_add_request(dev,
|
||||
I915_GEM_GPU_DOMAINS);
|
||||
if (seqno == 0)
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
ret = i915_wait_request(dev, seqno);
|
||||
if (ret)
|
||||
return ret;
|
||||
goto try_again;
|
||||
}
|
||||
|
||||
BUG_ON(old_obj_priv->active ||
|
||||
(reg->obj->write_domain & I915_GEM_GPU_DOMAINS));
|
||||
|
||||
/*
|
||||
* Zap this virtual mapping so we can set up a fence again
|
||||
* for this object next time we need it.
|
||||
@ -1655,8 +1691,17 @@ i915_gem_clear_fence_reg(struct drm_gem_object *obj)
|
||||
|
||||
if (IS_I965G(dev))
|
||||
I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0);
|
||||
else
|
||||
I915_WRITE(FENCE_REG_830_0 + (obj_priv->fence_reg * 4), 0);
|
||||
else {
|
||||
uint32_t fence_reg;
|
||||
|
||||
if (obj_priv->fence_reg < 8)
|
||||
fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4;
|
||||
else
|
||||
fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg -
|
||||
8) * 4;
|
||||
|
||||
I915_WRITE(fence_reg, 0);
|
||||
}
|
||||
|
||||
dev_priv->fence_regs[obj_priv->fence_reg].obj = NULL;
|
||||
obj_priv->fence_reg = I915_FENCE_REG_NONE;
|
||||
@ -2469,6 +2514,7 @@ i915_gem_execbuffer(struct drm_device *dev, void *data,
|
||||
struct drm_i915_gem_exec_object *exec_list = NULL;
|
||||
struct drm_gem_object **object_list = NULL;
|
||||
struct drm_gem_object *batch_obj;
|
||||
struct drm_i915_gem_object *obj_priv;
|
||||
int ret, i, pinned = 0;
|
||||
uint64_t exec_offset;
|
||||
uint32_t seqno, flush_domains;
|
||||
@ -2533,6 +2579,15 @@ i915_gem_execbuffer(struct drm_device *dev, void *data,
|
||||
ret = -EBADF;
|
||||
goto err;
|
||||
}
|
||||
|
||||
obj_priv = object_list[i]->driver_private;
|
||||
if (obj_priv->in_execbuffer) {
|
||||
DRM_ERROR("Object %p appears more than once in object list\n",
|
||||
object_list[i]);
|
||||
ret = -EBADF;
|
||||
goto err;
|
||||
}
|
||||
obj_priv->in_execbuffer = true;
|
||||
}
|
||||
|
||||
/* Pin and relocate */
|
||||
@ -2674,8 +2729,13 @@ err:
|
||||
for (i = 0; i < pinned; i++)
|
||||
i915_gem_object_unpin(object_list[i]);
|
||||
|
||||
for (i = 0; i < args->buffer_count; i++)
|
||||
for (i = 0; i < args->buffer_count; i++) {
|
||||
if (object_list[i]) {
|
||||
obj_priv = object_list[i]->driver_private;
|
||||
obj_priv->in_execbuffer = false;
|
||||
}
|
||||
drm_gem_object_unreference(object_list[i]);
|
||||
}
|
||||
|
||||
mutex_unlock(&dev->struct_mutex);
|
||||
|
||||
@ -2712,17 +2772,24 @@ i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
|
||||
ret = i915_gem_object_bind_to_gtt(obj, alignment);
|
||||
if (ret != 0) {
|
||||
if (ret != -EBUSY && ret != -ERESTARTSYS)
|
||||
DRM_ERROR("Failure to bind: %d", ret);
|
||||
DRM_ERROR("Failure to bind: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
/*
|
||||
* Pre-965 chips need a fence register set up in order to
|
||||
* properly handle tiled surfaces.
|
||||
*/
|
||||
if (!IS_I965G(dev) &&
|
||||
obj_priv->fence_reg == I915_FENCE_REG_NONE &&
|
||||
obj_priv->tiling_mode != I915_TILING_NONE) {
|
||||
ret = i915_gem_object_get_fence_reg(obj, true);
|
||||
if (ret != 0) {
|
||||
if (ret != -EBUSY && ret != -ERESTARTSYS)
|
||||
DRM_ERROR("Failure to install fence: %d\n",
|
||||
ret);
|
||||
return ret;
|
||||
}
|
||||
/*
|
||||
* Pre-965 chips need a fence register set up in order to
|
||||
* properly handle tiled surfaces.
|
||||
*/
|
||||
if (!IS_I965G(dev) &&
|
||||
obj_priv->fence_reg == I915_FENCE_REG_NONE &&
|
||||
obj_priv->tiling_mode != I915_TILING_NONE)
|
||||
i915_gem_object_get_fence_reg(obj, true);
|
||||
}
|
||||
obj_priv->pin_count++;
|
||||
|
||||
|
||||
@ -184,6 +184,7 @@
|
||||
* Fence registers
|
||||
*/
|
||||
#define FENCE_REG_830_0 0x2000
|
||||
#define FENCE_REG_945_8 0x3000
|
||||
#define I830_FENCE_START_MASK 0x07f80000
|
||||
#define I830_FENCE_TILING_Y_SHIFT 12
|
||||
#define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8)
|
||||
|
||||
@ -119,11 +119,6 @@ static void i915_save_vga(struct drm_device *dev)
|
||||
|
||||
/* VGA color palette registers */
|
||||
dev_priv->saveDACMASK = I915_READ8(VGA_DACMASK);
|
||||
/* DACCRX automatically increments during read */
|
||||
I915_WRITE8(VGA_DACRX, 0);
|
||||
/* Read 3 bytes of color data from each index */
|
||||
for (i = 0; i < 256 * 3; i++)
|
||||
dev_priv->saveDACDATA[i] = I915_READ8(VGA_DACDATA);
|
||||
|
||||
/* MSR bits */
|
||||
dev_priv->saveMSR = I915_READ8(VGA_MSR_READ);
|
||||
@ -225,12 +220,6 @@ static void i915_restore_vga(struct drm_device *dev)
|
||||
|
||||
/* VGA color palette registers */
|
||||
I915_WRITE8(VGA_DACMASK, dev_priv->saveDACMASK);
|
||||
/* DACCRX automatically increments during read */
|
||||
I915_WRITE8(VGA_DACWX, 0);
|
||||
/* Read 3 bytes of color data from each index */
|
||||
for (i = 0; i < 256 * 3; i++)
|
||||
I915_WRITE8(VGA_DACDATA, dev_priv->saveDACDATA[i]);
|
||||
|
||||
}
|
||||
|
||||
int i915_save_state(struct drm_device *dev)
|
||||
|
||||
@ -1853,13 +1853,14 @@ static void aty128_bl_exit(struct backlight_device *bd)
|
||||
* Initialisation
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_PPC_PMAC
|
||||
#ifdef CONFIG_PPC_PMAC__disabled
|
||||
static void aty128_early_resume(void *data)
|
||||
{
|
||||
struct aty128fb_par *par = data;
|
||||
|
||||
if (try_acquire_console_sem())
|
||||
return;
|
||||
pci_restore_state(par->pdev);
|
||||
aty128_do_resume(par->pdev);
|
||||
release_console_sem();
|
||||
}
|
||||
@ -1907,7 +1908,14 @@ static int __devinit aty128_init(struct pci_dev *pdev, const struct pci_device_i
|
||||
/* Indicate sleep capability */
|
||||
if (par->chip_gen == rage_M3) {
|
||||
pmac_call_feature(PMAC_FTR_DEVICE_CAN_WAKE, NULL, 0, 1);
|
||||
#if 0 /* Disable the early video resume hack for now as it's causing problems, among
|
||||
* others we now rely on the PCI core restoring the config space for us, which
|
||||
* isn't the case with that hack, and that code path causes various things to
|
||||
* be called with interrupts off while they shouldn't. I'm leaving the code in
|
||||
* as it can be useful for debugging purposes
|
||||
*/
|
||||
pmac_set_early_video_resume(aty128_early_resume, par);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* Find default mode */
|
||||
|
||||
@ -2762,12 +2762,13 @@ int radeonfb_pci_resume(struct pci_dev *pdev)
|
||||
return rc;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PPC_OF
|
||||
#ifdef CONFIG_PPC_OF__disabled
|
||||
static void radeonfb_early_resume(void *data)
|
||||
{
|
||||
struct radeonfb_info *rinfo = data;
|
||||
|
||||
rinfo->no_schedule = 1;
|
||||
pci_restore_state(rinfo->pdev);
|
||||
radeonfb_pci_resume(rinfo->pdev);
|
||||
rinfo->no_schedule = 0;
|
||||
}
|
||||
@ -2834,7 +2835,14 @@ void radeonfb_pm_init(struct radeonfb_info *rinfo, int dynclk, int ignore_devlis
|
||||
*/
|
||||
if (rinfo->pm_mode != radeon_pm_none) {
|
||||
pmac_call_feature(PMAC_FTR_DEVICE_CAN_WAKE, rinfo->of_node, 0, 1);
|
||||
#if 0 /* Disable the early video resume hack for now as it's causing problems, among
|
||||
* others we now rely on the PCI core restoring the config space for us, which
|
||||
* isn't the case with that hack, and that code path causes various things to
|
||||
* be called with interrupts off while they shouldn't. I'm leaving the code in
|
||||
* as it can be useful for debugging purposes
|
||||
*/
|
||||
pmac_set_early_video_resume(radeonfb_early_resume, rinfo);
|
||||
#endif
|
||||
}
|
||||
|
||||
#if 0
|
||||
|
||||
@ -202,9 +202,9 @@ static sector_t _fat_bmap(struct address_space *mapping, sector_t block)
|
||||
sector_t blocknr;
|
||||
|
||||
/* fat_get_cluster() assumes the requested blocknr isn't truncated. */
|
||||
mutex_lock(&mapping->host->i_mutex);
|
||||
down_read(&mapping->host->i_alloc_sem);
|
||||
blocknr = generic_block_bmap(mapping, block, fat_get_block);
|
||||
mutex_unlock(&mapping->host->i_mutex);
|
||||
up_read(&mapping->host->i_alloc_sem);
|
||||
|
||||
return blocknr;
|
||||
}
|
||||
|
||||
@ -80,7 +80,7 @@ static const struct file_operations proc_kpagecount_operations = {
|
||||
#define KPF_RECLAIM 9
|
||||
#define KPF_BUDDY 10
|
||||
|
||||
#define kpf_copy_bit(flags, srcpos, dstpos) (((flags >> srcpos) & 1) << dstpos)
|
||||
#define kpf_copy_bit(flags, dstpos, srcpos) (((flags >> srcpos) & 1) << dstpos)
|
||||
|
||||
static ssize_t kpageflags_read(struct file *file, char __user *buf,
|
||||
size_t count, loff_t *ppos)
|
||||
|
||||
@ -69,8 +69,8 @@ struct detailed_pixel_timing {
|
||||
u8 hborder;
|
||||
u8 vborder;
|
||||
u8 unknown0:1;
|
||||
u8 vsync_positive:1;
|
||||
u8 hsync_positive:1;
|
||||
u8 vsync_positive:1;
|
||||
u8 separate_sync:2;
|
||||
u8 stereo:1;
|
||||
u8 unknown6:1;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user