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ioat1: trim ioat_dma_desc_sw
Save 4 bytes per software descriptor by transmitting tx_cnt in an unused portion of the hardware descriptor. Signed-off-by: Maciej Sosnowski <maciej.sosnowski@intel.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
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@ -396,7 +396,7 @@ static dma_cookie_t ioat1_tx_submit(struct dma_async_tx_descriptor *tx)
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dump_desc_dbg(ioat, chain_tail);
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dump_desc_dbg(ioat, first);
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ioat->pending += desc->tx_cnt;
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ioat->pending += desc->hw->tx_cnt;
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if (ioat->pending >= ioat_pending_level)
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__ioat1_dma_memcpy_issue_pending(ioat);
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spin_unlock_bh(&ioat->desc_lock);
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@ -655,11 +655,11 @@ ioat1_dma_prep_memcpy(struct dma_chan *c, dma_addr_t dma_dest,
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spin_unlock_bh(&ioat->desc_lock);
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desc->txd.flags = flags;
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desc->tx_cnt = tx_cnt;
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desc->len = total_len;
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list_splice(&chain, &desc->txd.tx_list);
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hw->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT);
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hw->ctl_f.compl_write = 1;
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hw->tx_cnt = tx_cnt;
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dump_desc_dbg(ioat, desc);
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return &desc->txd;
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@ -165,14 +165,12 @@ ioat_is_complete(struct dma_chan *c, dma_cookie_t cookie,
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* @hw: hardware DMA descriptor
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* @node: this descriptor will either be on the free list,
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* or attached to a transaction list (async_tx.tx_list)
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* @tx_cnt: number of descriptors required to complete the transaction
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* @txd: the generic software descriptor for all engines
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* @id: identifier for debug
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*/
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struct ioat_desc_sw {
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struct ioat_dma_descriptor *hw;
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struct list_head node;
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int tx_cnt;
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size_t len;
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struct dma_async_tx_descriptor txd;
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#ifdef DEBUG
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@ -63,7 +63,11 @@ struct ioat_dma_descriptor {
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uint64_t next;
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uint64_t rsv1;
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uint64_t rsv2;
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uint64_t user1;
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/* store some driver data in an unused portion of the descriptor */
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union {
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uint64_t user1;
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uint64_t tx_cnt;
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};
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uint64_t user2;
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};
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#endif
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