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Disintegrate asm/system.h for Tile

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Disintegrate asm/system.h for Tile.

Signed-off-by: David Howells <dhowells@redhat.com>
Acked-by: Chris Metcalf <cmetcalf@tilera.com>
This commit is contained in:
David Howells 2012-03-28 18:30:03 +01:00
parent d550bbd40c
commit bd119c6923
26 changed files with 309 additions and 273 deletions
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2
arch/tile/include/asm/atomic.h
View File

@ -20,7 +20,7 @@
#ifndef __ASSEMBLY__
#include <linux/compiler.h>
#include <asm/system.h>
#include <linux/types.h>
#define ATOMIC_INIT(i) { (i) }

1
arch/tile/include/asm/atomic_32.h
View File

@ -17,6 +17,7 @@
#ifndef _ASM_TILE_ATOMIC_32_H
#define _ASM_TILE_ATOMIC_32_H
#include <asm/barrier.h>
#include <arch/chip.h>
#ifndef __ASSEMBLY__

1
arch/tile/include/asm/atomic_64.h
View File

@ -19,6 +19,7 @@
#ifndef __ASSEMBLY__
#include <asm/barrier.h>
#include <arch/spr_def.h>
/* First, the 32-bit atomic ops that are "real" on our 64-bit platform. */

148
arch/tile/include/asm/barrier.h Normal file
View File

@ -0,0 +1,148 @@
/*
* Copyright 2010 Tilera Corporation. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation, version 2.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
* NON INFRINGEMENT. See the GNU General Public License for
* more details.
*/
#ifndef _ASM_TILE_BARRIER_H
#define _ASM_TILE_BARRIER_H
#ifndef __ASSEMBLY__
#include <linux/types.h>
#include <arch/chip.h>
#include <arch/spr_def.h>
#include <asm/timex.h>
/*
* read_barrier_depends - Flush all pending reads that subsequents reads
* depend on.
*
* No data-dependent reads from memory-like regions are ever reordered
* over this barrier. All reads preceding this primitive are guaranteed
* to access memory (but not necessarily other CPUs' caches) before any
* reads following this primitive that depend on the data return by
* any of the preceding reads. This primitive is much lighter weight than
* rmb() on most CPUs, and is never heavier weight than is
* rmb().
*
* These ordering constraints are respected by both the local CPU
* and the compiler.
*
* Ordering is not guaranteed by anything other than these primitives,
* not even by data dependencies. See the documentation for
* memory_barrier() for examples and URLs to more information.
*
* For example, the following code would force ordering (the initial
* value of "a" is zero, "b" is one, and "p" is "&a"):
*
* <programlisting>
* CPU 0 CPU 1
*
* b = 2;
* memory_barrier();
* p = &b; q = p;
* read_barrier_depends();
* d = *q;
* </programlisting>
*
* because the read of "*q" depends on the read of "p" and these
* two reads are separated by a read_barrier_depends(). However,
* the following code, with the same initial values for "a" and "b":
*
* <programlisting>
* CPU 0 CPU 1
*
* a = 2;
* memory_barrier();
* b = 3; y = b;
* read_barrier_depends();
* x = a;
* </programlisting>
*
* does not enforce ordering, since there is no data dependency between
* the read of "a" and the read of "b". Therefore, on some CPUs, such
* as Alpha, "y" could be set to 3 and "x" to 0. Use rmb()
* in cases like this where there are no data dependencies.
*/
#define read_barrier_depends() do { } while (0)
#define __sync() __insn_mf()
#if !CHIP_HAS_MF_WAITS_FOR_VICTIMS()
#include <hv/syscall_public.h>
/*
* Issue an uncacheable load to each memory controller, then
* wait until those loads have completed.
*/
static inline void __mb_incoherent(void)
{
long clobber_r10;
asm volatile("swint2"
: "=R10" (clobber_r10)
: "R10" (HV_SYS_fence_incoherent)
: "r0", "r1", "r2", "r3", "r4",
"r5", "r6", "r7", "r8", "r9",
"r11", "r12", "r13", "r14",
"r15", "r16", "r17", "r18", "r19",
"r20", "r21", "r22", "r23", "r24",
"r25", "r26", "r27", "r28", "r29");
}
#endif
/* Fence to guarantee visibility of stores to incoherent memory. */
static inline void
mb_incoherent(void)
{
__insn_mf();
#if !CHIP_HAS_MF_WAITS_FOR_VICTIMS()
{
#if CHIP_HAS_TILE_WRITE_PENDING()
const unsigned long WRITE_TIMEOUT_CYCLES = 400;
unsigned long start = get_cycles_low();
do {
if (__insn_mfspr(SPR_TILE_WRITE_PENDING) == 0)
return;
} while ((get_cycles_low() - start) < WRITE_TIMEOUT_CYCLES);
#endif /* CHIP_HAS_TILE_WRITE_PENDING() */
(void) __mb_incoherent();
}
#endif /* CHIP_HAS_MF_WAITS_FOR_VICTIMS() */
}
#define fast_wmb() __sync()
#define fast_rmb() __sync()
#define fast_mb() __sync()
#define fast_iob() mb_incoherent()
#define wmb() fast_wmb()
#define rmb() fast_rmb()
#define mb() fast_mb()
#define iob() fast_iob()
#ifdef CONFIG_SMP
#define smp_mb() mb()
#define smp_rmb() rmb()
#define smp_wmb() wmb()
#define smp_read_barrier_depends() read_barrier_depends()
#else
#define smp_mb() barrier()
#define smp_rmb() barrier()
#define smp_wmb() barrier()
#define smp_read_barrier_depends() do { } while (0)
#endif
#define set_mb(var, value) \
do { var = value; mb(); } while (0)
#endif /* !__ASSEMBLY__ */
#endif /* _ASM_TILE_BARRIER_H */

1
arch/tile/include/asm/bitops_32.h
View File

@ -17,7 +17,6 @@
#include <linux/compiler.h>
#include <linux/atomic.h>
#include <asm/system.h>
/* Tile-specific routines to support <asm/bitops.h>. */
unsigned long _atomic_or(volatile unsigned long *p, unsigned long mask);

1
arch/tile/include/asm/bitops_64.h
View File

@ -17,7 +17,6 @@
#include <linux/compiler.h>
#include <linux/atomic.h>
#include <asm/system.h>
/* See <asm/bitops.h> for API comments. */

11
arch/tile/include/asm/cacheflush.h
View File

@ -20,7 +20,6 @@
/* Keep includes the same across arches. */
#include <linux/mm.h>
#include <linux/cache.h>
#include <asm/system.h>
#include <arch/icache.h>
/* Caches are physically-indexed and so don't need special treatment */
@ -152,4 +151,14 @@ static inline void finv_buffer_local(void *buffer, size_t size)
*/
void finv_buffer_remote(void *buffer, size_t size, int hfh);
/*
* On SMP systems, when the scheduler does migration-cost autodetection,
* it needs a way to flush as much of the CPU's caches as possible:
*
* TODO: fill this in!
*/
static inline void sched_cacheflush(void)
{
}
#endif /* _ASM_TILE_CACHEFLUSH_H */

20
arch/tile/include/asm/exec.h Normal file
View File

@ -0,0 +1,20 @@
/*
* Copyright 2010 Tilera Corporation. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation, version 2.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
* NON INFRINGEMENT. See the GNU General Public License for
* more details.
*/
#ifndef _ASM_TILE_EXEC_H
#define _ASM_TILE_EXEC_H
#define arch_align_stack(x) (x)
#endif /* _ASM_TILE_EXEC_H */

1
arch/tile/include/asm/pgtable.h
View File

@ -29,7 +29,6 @@
#include <linux/spinlock.h>
#include <asm/processor.h>
#include <asm/fixmap.h>
#include <asm/system.h>
struct mm_struct;
struct vm_area_struct;

22
arch/tile/include/asm/setup.h
View File

@ -31,6 +31,28 @@ void early_panic(const char *fmt, ...);
void warn_early_printk(void);
void __init disable_early_printk(void);
/* Init-time routine to do tile-specific per-cpu setup. */
void setup_cpu(int boot);
/* User-level DMA management functions */
void grant_dma_mpls(void);
void restrict_dma_mpls(void);
#ifdef CONFIG_HARDWALL
/* User-level network management functions */
void reset_network_state(void);
void grant_network_mpls(void);
void restrict_network_mpls(void);
struct task_struct;
int hardwall_deactivate(struct task_struct *task);
/* Hook hardwall code into changes in affinity. */
#define arch_set_cpus_allowed(p, new_mask) do { \
if (p->thread.hardwall && !cpumask_equal(&p->cpus_allowed, new_mask)) \
hardwall_deactivate(p); \
} while (0)
#endif
#endif /* __KERNEL__ */
#endif /* _ASM_TILE_SETUP_H */

1
arch/tile/include/asm/spinlock_32.h
View File

@ -19,7 +19,6 @@
#include <linux/atomic.h>
#include <asm/page.h>
#include <asm/system.h>
#include <linux/compiler.h>
/*

76
arch/tile/include/asm/switch_to.h Normal file
View File

@ -0,0 +1,76 @@
/*
* Copyright 2010 Tilera Corporation. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation, version 2.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
* NON INFRINGEMENT. See the GNU General Public License for
* more details.
*/
#ifndef _ASM_TILE_SWITCH_TO_H
#define _ASM_TILE_SWITCH_TO_H
#include <arch/sim_def.h>
/*
* switch_to(n) should switch tasks to task nr n, first
* checking that n isn't the current task, in which case it does nothing.
* The number of callee-saved registers saved on the kernel stack
* is defined here for use in copy_thread() and must agree with __switch_to().
*/
#define CALLEE_SAVED_FIRST_REG 30
#define CALLEE_SAVED_REGS_COUNT 24 /* r30 to r52, plus an empty to align */
#ifndef __ASSEMBLY__
struct task_struct;
/*
* Pause the DMA engine and static network before task switching.
*/
#define prepare_arch_switch(next) _prepare_arch_switch(next)
void _prepare_arch_switch(struct task_struct *next);
struct task_struct;
#define switch_to(prev, next, last) ((last) = _switch_to((prev), (next)))
extern struct task_struct *_switch_to(struct task_struct *prev,
struct task_struct *next);
/* Helper function for _switch_to(). */
extern struct task_struct *__switch_to(struct task_struct *prev,
struct task_struct *next,
unsigned long new_system_save_k_0);
/* Address that switched-away from tasks are at. */
extern unsigned long get_switch_to_pc(void);
/*
* Kernel threads can check to see if they need to migrate their
* stack whenever they return from a context switch; for user
* threads, we defer until they are returning to user-space.
*/
#define finish_arch_switch(prev) do { \
if (unlikely((prev)->state == TASK_DEAD)) \
__insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_OS_EXIT | \
((prev)->pid << _SIM_CONTROL_OPERATOR_BITS)); \
__insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_OS_SWITCH | \
(current->pid << _SIM_CONTROL_OPERATOR_BITS)); \
if (current->mm == NULL && !kstack_hash && \
current_thread_info()->homecache_cpu != smp_processor_id()) \
homecache_migrate_kthread(); \
} while (0)
/* Support function for forking a new task. */
void ret_from_fork(void);
/* Called from ret_from_fork() when a new process starts up. */
struct task_struct *sim_notify_fork(struct task_struct *prev);
#endif /* !__ASSEMBLY__ */
#endif /* _ASM_TILE_SWITCH_TO_H */

265
arch/tile/include/asm/system.h
View File

@ -1,261 +1,4 @@
/*
* Copyright 2010 Tilera Corporation. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation, version 2.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
* NON INFRINGEMENT. See the GNU General Public License for
* more details.
*/
#ifndef _ASM_TILE_SYSTEM_H
#define _ASM_TILE_SYSTEM_H
#ifndef __ASSEMBLY__
#include <linux/types.h>
#include <linux/irqflags.h>
/* NOTE: we can't include <linux/ptrace.h> due to #include dependencies. */
#include <asm/ptrace.h>
#include <arch/chip.h>
#include <arch/sim_def.h>
#include <arch/spr_def.h>
/*
* read_barrier_depends - Flush all pending reads that subsequents reads
* depend on.
*
* No data-dependent reads from memory-like regions are ever reordered
* over this barrier. All reads preceding this primitive are guaranteed
* to access memory (but not necessarily other CPUs' caches) before any
* reads following this primitive that depend on the data return by
* any of the preceding reads. This primitive is much lighter weight than
* rmb() on most CPUs, and is never heavier weight than is
* rmb().
*
* These ordering constraints are respected by both the local CPU
* and the compiler.
*
* Ordering is not guaranteed by anything other than these primitives,
* not even by data dependencies. See the documentation for
* memory_barrier() for examples and URLs to more information.
*
* For example, the following code would force ordering (the initial
* value of "a" is zero, "b" is one, and "p" is "&a"):
*
* <programlisting>
* CPU 0 CPU 1
*
* b = 2;
* memory_barrier();
* p = &b; q = p;
* read_barrier_depends();
* d = *q;
* </programlisting>
*
* because the read of "*q" depends on the read of "p" and these
* two reads are separated by a read_barrier_depends(). However,
* the following code, with the same initial values for "a" and "b":
*
* <programlisting>
* CPU 0 CPU 1
*
* a = 2;
* memory_barrier();
* b = 3; y = b;
* read_barrier_depends();
* x = a;
* </programlisting>
*
* does not enforce ordering, since there is no data dependency between
* the read of "a" and the read of "b". Therefore, on some CPUs, such
* as Alpha, "y" could be set to 3 and "x" to 0. Use rmb()
* in cases like this where there are no data dependencies.
*/
#define read_barrier_depends() do { } while (0)
#define __sync() __insn_mf()
#if CHIP_HAS_SPLIT_CYCLE()
#define get_cycles_low() __insn_mfspr(SPR_CYCLE_LOW)
#else
#define get_cycles_low() __insn_mfspr(SPR_CYCLE) /* just get all 64 bits */
#endif
#if !CHIP_HAS_MF_WAITS_FOR_VICTIMS()
#include <hv/syscall_public.h>
/*
* Issue an uncacheable load to each memory controller, then
* wait until those loads have completed.
*/
static inline void __mb_incoherent(void)
{
long clobber_r10;
asm volatile("swint2"
: "=R10" (clobber_r10)
: "R10" (HV_SYS_fence_incoherent)
: "r0", "r1", "r2", "r3", "r4",
"r5", "r6", "r7", "r8", "r9",
"r11", "r12", "r13", "r14",
"r15", "r16", "r17", "r18", "r19",
"r20", "r21", "r22", "r23", "r24",
"r25", "r26", "r27", "r28", "r29");
}
#endif
/* Fence to guarantee visibility of stores to incoherent memory. */
static inline void
mb_incoherent(void)
{
__insn_mf();
#if !CHIP_HAS_MF_WAITS_FOR_VICTIMS()
{
#if CHIP_HAS_TILE_WRITE_PENDING()
const unsigned long WRITE_TIMEOUT_CYCLES = 400;
unsigned long start = get_cycles_low();
do {
if (__insn_mfspr(SPR_TILE_WRITE_PENDING) == 0)
return;
} while ((get_cycles_low() - start) < WRITE_TIMEOUT_CYCLES);
#endif /* CHIP_HAS_TILE_WRITE_PENDING() */
(void) __mb_incoherent();
}
#endif /* CHIP_HAS_MF_WAITS_FOR_VICTIMS() */
}
#define fast_wmb() __sync()
#define fast_rmb() __sync()
#define fast_mb() __sync()
#define fast_iob() mb_incoherent()
#define wmb() fast_wmb()
#define rmb() fast_rmb()
#define mb() fast_mb()
#define iob() fast_iob()
#ifdef CONFIG_SMP
#define smp_mb() mb()
#define smp_rmb() rmb()
#define smp_wmb() wmb()
#define smp_read_barrier_depends() read_barrier_depends()
#else
#define smp_mb() barrier()
#define smp_rmb() barrier()
#define smp_wmb() barrier()
#define smp_read_barrier_depends() do { } while (0)
#endif
#define set_mb(var, value) \
do { var = value; mb(); } while (0)
/*
* Pause the DMA engine and static network before task switching.
*/
#define prepare_arch_switch(next) _prepare_arch_switch(next)
void _prepare_arch_switch(struct task_struct *next);
/*
* switch_to(n) should switch tasks to task nr n, first
* checking that n isn't the current task, in which case it does nothing.
* The number of callee-saved registers saved on the kernel stack
* is defined here for use in copy_thread() and must agree with __switch_to().
*/
#endif /* !__ASSEMBLY__ */
#define CALLEE_SAVED_FIRST_REG 30
#define CALLEE_SAVED_REGS_COUNT 24 /* r30 to r52, plus an empty to align */
#ifndef __ASSEMBLY__
struct task_struct;
#define switch_to(prev, next, last) ((last) = _switch_to((prev), (next)))
extern struct task_struct *_switch_to(struct task_struct *prev,
struct task_struct *next);
/* Helper function for _switch_to(). */
extern struct task_struct *__switch_to(struct task_struct *prev,
struct task_struct *next,
unsigned long new_system_save_k_0);
/* Address that switched-away from tasks are at. */
extern unsigned long get_switch_to_pc(void);
/*
* On SMP systems, when the scheduler does migration-cost autodetection,
* it needs a way to flush as much of the CPU's caches as possible:
*
* TODO: fill this in!
*/
static inline void sched_cacheflush(void)
{
}
#define arch_align_stack(x) (x)
/*
* Is the kernel doing fixups of unaligned accesses? If <0, no kernel
* intervention occurs and SIGBUS is delivered with no data address
* info. If 0, the kernel single-steps the instruction to discover
* the data address to provide with the SIGBUS. If 1, the kernel does
* a fixup.
*/
extern int unaligned_fixup;
/* Is the kernel printing on each unaligned fixup? */
extern int unaligned_printk;
/* Number of unaligned fixups performed */
extern unsigned int unaligned_fixup_count;
/* Init-time routine to do tile-specific per-cpu setup. */
void setup_cpu(int boot);
/* User-level DMA management functions */
void grant_dma_mpls(void);
void restrict_dma_mpls(void);
#ifdef CONFIG_HARDWALL
/* User-level network management functions */
void reset_network_state(void);
void grant_network_mpls(void);
void restrict_network_mpls(void);
int hardwall_deactivate(struct task_struct *task);
/* Hook hardwall code into changes in affinity. */
#define arch_set_cpus_allowed(p, new_mask) do { \
if (p->thread.hardwall && !cpumask_equal(&p->cpus_allowed, new_mask)) \
hardwall_deactivate(p); \
} while (0)
#endif
/*
* Kernel threads can check to see if they need to migrate their
* stack whenever they return from a context switch; for user
* threads, we defer until they are returning to user-space.
*/
#define finish_arch_switch(prev) do { \
if (unlikely((prev)->state == TASK_DEAD)) \
__insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_OS_EXIT | \
((prev)->pid << _SIM_CONTROL_OPERATOR_BITS)); \
__insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_OS_SWITCH | \
(current->pid << _SIM_CONTROL_OPERATOR_BITS)); \
if (current->mm == NULL && !kstack_hash && \
current_thread_info()->homecache_cpu != smp_processor_id()) \
homecache_migrate_kthread(); \
} while (0)
/* Support function for forking a new task. */
void ret_from_fork(void);
/* Called from ret_from_fork() when a new process starts up. */
struct task_struct *sim_notify_fork(struct task_struct *prev);
#endif /* !__ASSEMBLY__ */
#endif /* _ASM_TILE_SYSTEM_H */
/* FILE TO BE DELETED. DO NOT ADD STUFF HERE! */
#include <asm/barrier.h>
#include <asm/exec.h>
#include <asm/switch_to.h>

2
arch/tile/include/asm/timex.h
View File

@ -29,11 +29,13 @@ typedef unsigned long long cycles_t;
#if CHIP_HAS_SPLIT_CYCLE()
cycles_t get_cycles(void);
#define get_cycles_low() __insn_mfspr(SPR_CYCLE_LOW)
#else
static inline cycles_t get_cycles(void)
{
return __insn_mfspr(SPR_CYCLE);
}
#define get_cycles_low() __insn_mfspr(SPR_CYCLE) /* just get all 64 bits */
#endif
cycles_t get_clock_rate(void);

15
arch/tile/include/asm/unaligned.h
View File

@ -21,4 +21,19 @@
#define get_unaligned __get_unaligned_le
#define put_unaligned __put_unaligned_le
/*
* Is the kernel doing fixups of unaligned accesses? If <0, no kernel
* intervention occurs and SIGBUS is delivered with no data address
* info. If 0, the kernel single-steps the instruction to discover
* the data address to provide with the SIGBUS. If 1, the kernel does
* a fixup.
*/
extern int unaligned_fixup;
/* Is the kernel printing on each unaligned fixup? */
extern int unaligned_printk;
/* Number of unaligned fixups performed */
extern unsigned int unaligned_fixup_count;
#endif /* _ASM_TILE_UNALIGNED_H */

1
arch/tile/kernel/early_printk.c
View File

@ -16,6 +16,7 @@
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/string.h>
#include <linux/irqflags.h>
#include <asm/setup.h>
#include <hv/hypervisor.h>

1
arch/tile/kernel/proc.c
View File

@ -23,6 +23,7 @@
#include <linux/sysctl.h>
#include <linux/hardirq.h>
#include <linux/mman.h>
#include <asm/unaligned.h>
#include <asm/pgtable.h>
#include <asm/processor.h>
#include <asm/sections.h>

3
arch/tile/kernel/process.c
View File

@ -27,16 +27,17 @@
#include <linux/kernel.h>
#include <linux/tracehook.h>
#include <linux/signal.h>
#include <asm/system.h>
#include <asm/stack.h>
#include <asm/homecache.h>
#include <asm/syscalls.h>
#include <asm/traps.h>
#include <asm/setup.h>
#ifdef CONFIG_HARDWALL
#include <asm/hardwall.h>
#endif
#include <arch/chip.h>
#include <arch/abi.h>
#include <arch/sim_def.h>
/*

2
arch/tile/kernel/regs_32.S
View File

@ -13,11 +13,11 @@
*/
#include <linux/linkage.h>
#include <asm/system.h>
#include <asm/ptrace.h>
#include <asm/asm-offsets.h>
#include <arch/spr_def.h>
#include <asm/processor.h>
#include <asm/switch_to.h>
/*
* See <asm/system.h>; called with prev and next task_struct pointers.

2
arch/tile/kernel/regs_64.S
View File

@ -13,11 +13,11 @@
*/
#include <linux/linkage.h>
#include <asm/system.h>
#include <asm/ptrace.h>
#include <asm/asm-offsets.h>
#include <arch/spr_def.h>
#include <asm/processor.h>
#include <asm/switch_to.h>
/*
* See <asm/system.h>; called with prev and next task_struct pointers.

1
arch/tile/kernel/single_step.c
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@ -25,6 +25,7 @@
#include <linux/types.h>
#include <linux/err.h>
#include <asm/cacheflush.h>
#include <asm/unaligned.h>
#include <arch/abi.h>
#include <arch/opcode.h>

1
arch/tile/kernel/traps.c
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@ -21,6 +21,7 @@
#include <linux/ptrace.h>
#include <asm/stack.h>
#include <asm/traps.h>
#include <asm/setup.h>
#include <arch/interrupts.h>
#include <arch/spr_def.h>

1
arch/tile/mm/elf.c
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@ -21,6 +21,7 @@
#include <asm/pgtable.h>
#include <asm/pgalloc.h>
#include <asm/sections.h>
#include <arch/sim_def.h>
/* Notify a running simulator, if any, that an exec just occurred. */
static void sim_notify_exec(const char *binary_name)

1
arch/tile/mm/fault.c
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@ -35,7 +35,6 @@
#include <linux/syscalls.h>
#include <linux/uaccess.h>
#include <asm/system.h>
#include <asm/pgalloc.h>
#include <asm/sections.h>
#include <asm/traps.h>

1
arch/tile/mm/init.c
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@ -38,7 +38,6 @@
#include <linux/uaccess.h>
#include <asm/mmu_context.h>
#include <asm/processor.h>
#include <asm/system.h>
#include <asm/pgtable.h>
#include <asm/pgalloc.h>
#include <asm/dma.h>

1
arch/tile/mm/pgtable.c
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@ -27,7 +27,6 @@
#include <linux/vmalloc.h>
#include <linux/smp.h>
#include <asm/system.h>
#include <asm/pgtable.h>
#include <asm/pgalloc.h>
#include <asm/fixmap.h>